2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_pci.h>
10 #include <linux/pci_hotplug.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/cpumask.h>
14 #include <linux/pci-aspm.h>
15 #include <asm-generic/pci-bridge.h>
18 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
19 #define CARDBUS_RESERVE_BUSNR 3
21 static struct resource busn_resource = {
25 .flags = IORESOURCE_BUS,
28 /* Ugh. Need to stop exporting this to modules. */
29 LIST_HEAD(pci_root_buses);
30 EXPORT_SYMBOL(pci_root_buses);
32 static LIST_HEAD(pci_domain_busn_res_list);
34 struct pci_domain_busn_res {
35 struct list_head list;
40 static struct resource *get_pci_domain_busn_res(int domain_nr)
42 struct pci_domain_busn_res *r;
44 list_for_each_entry(r, &pci_domain_busn_res_list, list)
45 if (r->domain_nr == domain_nr)
48 r = kzalloc(sizeof(*r), GFP_KERNEL);
52 r->domain_nr = domain_nr;
55 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
57 list_add_tail(&r->list, &pci_domain_busn_res_list);
62 static int find_anything(struct device *dev, void *data)
68 * Some device drivers need know if pci is initiated.
69 * Basically, we think pci is not initiated when there
70 * is no device to be found on the pci_bus_type.
72 int no_pci_devices(void)
77 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
78 no_devices = (dev == NULL);
82 EXPORT_SYMBOL(no_pci_devices);
87 static void release_pcibus_dev(struct device *dev)
89 struct pci_bus *pci_bus = to_pci_bus(dev);
91 put_device(pci_bus->bridge);
92 pci_bus_remove_resources(pci_bus);
93 pci_release_bus_of_node(pci_bus);
97 static struct class pcibus_class = {
99 .dev_release = &release_pcibus_dev,
100 .dev_groups = pcibus_groups,
103 static int __init pcibus_class_init(void)
105 return class_register(&pcibus_class);
107 postcore_initcall(pcibus_class_init);
109 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
111 u64 size = mask & maxbase; /* Find the significant bits */
115 /* Get the lowest of them to find the decode size, and
116 from that the extent. */
117 size = (size & ~(size-1)) - 1;
119 /* base == maxbase can be valid only if the BAR has
120 already been programmed with all 1s. */
121 if (base == maxbase && ((base | size) & mask) != mask)
127 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
132 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
133 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
134 flags |= IORESOURCE_IO;
138 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
139 flags |= IORESOURCE_MEM;
140 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
141 flags |= IORESOURCE_PREFETCH;
143 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
145 case PCI_BASE_ADDRESS_MEM_TYPE_32:
147 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
148 /* 1M mem BAR treated as 32-bit BAR */
150 case PCI_BASE_ADDRESS_MEM_TYPE_64:
151 flags |= IORESOURCE_MEM_64;
154 /* mem unknown type treated as 32-bit BAR */
160 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
163 * pci_read_base - read a PCI BAR
164 * @dev: the PCI device
165 * @type: type of the BAR
166 * @res: resource buffer to be filled in
167 * @pos: BAR position in the config space
169 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
171 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
172 struct resource *res, unsigned int pos)
175 u64 l64, sz64, mask64;
177 struct pci_bus_region region, inverted_region;
179 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
181 /* No printks while decoding is disabled! */
182 if (!dev->mmio_always_on) {
183 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
184 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
185 pci_write_config_word(dev, PCI_COMMAND,
186 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
190 res->name = pci_name(dev);
192 pci_read_config_dword(dev, pos, &l);
193 pci_write_config_dword(dev, pos, l | mask);
194 pci_read_config_dword(dev, pos, &sz);
195 pci_write_config_dword(dev, pos, l);
198 * All bits set in sz means the device isn't working properly.
199 * If the BAR isn't implemented, all bits must be 0. If it's a
200 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
203 if (sz == 0xffffffff)
207 * I don't know how l can have all bits set. Copied from old code.
208 * Maybe it fixes a bug on some ancient platform.
213 if (type == pci_bar_unknown) {
214 res->flags = decode_bar(dev, l);
215 res->flags |= IORESOURCE_SIZEALIGN;
216 if (res->flags & IORESOURCE_IO) {
217 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
218 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
219 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
221 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
223 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
226 res->flags |= (l & IORESOURCE_ROM_ENABLE);
227 l64 = l & PCI_ROM_ADDRESS_MASK;
228 sz64 = sz & PCI_ROM_ADDRESS_MASK;
229 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
232 if (res->flags & IORESOURCE_MEM_64) {
233 pci_read_config_dword(dev, pos + 4, &l);
234 pci_write_config_dword(dev, pos + 4, ~0);
235 pci_read_config_dword(dev, pos + 4, &sz);
236 pci_write_config_dword(dev, pos + 4, l);
238 l64 |= ((u64)l << 32);
239 sz64 |= ((u64)sz << 32);
240 mask64 |= ((u64)~0 << 32);
243 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
244 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
249 sz64 = pci_size(l64, sz64, mask64);
251 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
256 if (res->flags & IORESOURCE_MEM_64) {
257 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
258 && sz64 > 0x100000000ULL) {
259 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
262 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
263 pos, (unsigned long long)sz64);
267 if ((sizeof(pci_bus_addr_t) < 8) && l) {
268 /* Above 32-bit boundary; try to reallocate */
269 res->flags |= IORESOURCE_UNSET;
272 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
273 pos, (unsigned long long)l64);
279 region.end = l64 + sz64;
281 pcibios_bus_to_resource(dev->bus, res, ®ion);
282 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
285 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
286 * the corresponding resource address (the physical address used by
287 * the CPU. Converting that resource address back to a bus address
288 * should yield the original BAR value:
290 * resource_to_bus(bus_to_resource(A)) == A
292 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
293 * be claimed by the device.
295 if (inverted_region.start != region.start) {
296 res->flags |= IORESOURCE_UNSET;
298 res->end = region.end - region.start;
299 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
300 pos, (unsigned long long)region.start);
310 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
312 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
315 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
317 unsigned int pos, reg;
319 for (pos = 0; pos < howmany; pos++) {
320 struct resource *res = &dev->resource[pos];
321 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
322 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
326 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
327 dev->rom_base_reg = rom;
328 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
329 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
330 IORESOURCE_SIZEALIGN;
331 __pci_read_base(dev, pci_bar_mem32, res, rom);
335 static void pci_read_bridge_io(struct pci_bus *child)
337 struct pci_dev *dev = child->self;
338 u8 io_base_lo, io_limit_lo;
339 unsigned long io_mask, io_granularity, base, limit;
340 struct pci_bus_region region;
341 struct resource *res;
343 io_mask = PCI_IO_RANGE_MASK;
344 io_granularity = 0x1000;
345 if (dev->io_window_1k) {
346 /* Support 1K I/O space granularity */
347 io_mask = PCI_IO_1K_RANGE_MASK;
348 io_granularity = 0x400;
351 res = child->resource[0];
352 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
353 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
354 base = (io_base_lo & io_mask) << 8;
355 limit = (io_limit_lo & io_mask) << 8;
357 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
358 u16 io_base_hi, io_limit_hi;
360 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
361 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
362 base |= ((unsigned long) io_base_hi << 16);
363 limit |= ((unsigned long) io_limit_hi << 16);
367 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
369 region.end = limit + io_granularity - 1;
370 pcibios_bus_to_resource(dev->bus, res, ®ion);
371 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
375 static void pci_read_bridge_mmio(struct pci_bus *child)
377 struct pci_dev *dev = child->self;
378 u16 mem_base_lo, mem_limit_lo;
379 unsigned long base, limit;
380 struct pci_bus_region region;
381 struct resource *res;
383 res = child->resource[1];
384 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
385 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
386 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
387 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
389 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
391 region.end = limit + 0xfffff;
392 pcibios_bus_to_resource(dev->bus, res, ®ion);
393 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
397 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
399 struct pci_dev *dev = child->self;
400 u16 mem_base_lo, mem_limit_lo;
402 pci_bus_addr_t base, limit;
403 struct pci_bus_region region;
404 struct resource *res;
406 res = child->resource[2];
407 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
408 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
409 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
410 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
412 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
413 u32 mem_base_hi, mem_limit_hi;
415 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
416 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
419 * Some bridges set the base > limit by default, and some
420 * (broken) BIOSes do not initialize them. If we find
421 * this, just assume they are not being used.
423 if (mem_base_hi <= mem_limit_hi) {
424 base64 |= (u64) mem_base_hi << 32;
425 limit64 |= (u64) mem_limit_hi << 32;
429 base = (pci_bus_addr_t) base64;
430 limit = (pci_bus_addr_t) limit64;
432 if (base != base64) {
433 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
434 (unsigned long long) base64);
439 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
440 IORESOURCE_MEM | IORESOURCE_PREFETCH;
441 if (res->flags & PCI_PREF_RANGE_TYPE_64)
442 res->flags |= IORESOURCE_MEM_64;
444 region.end = limit + 0xfffff;
445 pcibios_bus_to_resource(dev->bus, res, ®ion);
446 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
450 void pci_read_bridge_bases(struct pci_bus *child)
452 struct pci_dev *dev = child->self;
453 struct resource *res;
456 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
459 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
461 dev->transparent ? " (subtractive decode)" : "");
463 pci_bus_remove_resources(child);
464 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
465 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
467 pci_read_bridge_io(child);
468 pci_read_bridge_mmio(child);
469 pci_read_bridge_mmio_pref(child);
471 if (dev->transparent) {
472 pci_bus_for_each_resource(child->parent, res, i) {
473 if (res && res->flags) {
474 pci_bus_add_resource(child, res,
475 PCI_SUBTRACTIVE_DECODE);
476 dev_printk(KERN_DEBUG, &dev->dev,
477 " bridge window %pR (subtractive decode)\n",
484 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
488 b = kzalloc(sizeof(*b), GFP_KERNEL);
492 INIT_LIST_HEAD(&b->node);
493 INIT_LIST_HEAD(&b->children);
494 INIT_LIST_HEAD(&b->devices);
495 INIT_LIST_HEAD(&b->slots);
496 INIT_LIST_HEAD(&b->resources);
497 b->max_bus_speed = PCI_SPEED_UNKNOWN;
498 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
499 #ifdef CONFIG_PCI_DOMAINS_GENERIC
501 b->domain_nr = parent->domain_nr;
506 static void pci_release_host_bridge_dev(struct device *dev)
508 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
510 if (bridge->release_fn)
511 bridge->release_fn(bridge);
513 pci_free_resource_list(&bridge->windows);
518 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
520 struct pci_host_bridge *bridge;
522 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
526 INIT_LIST_HEAD(&bridge->windows);
531 static const unsigned char pcix_bus_speed[] = {
532 PCI_SPEED_UNKNOWN, /* 0 */
533 PCI_SPEED_66MHz_PCIX, /* 1 */
534 PCI_SPEED_100MHz_PCIX, /* 2 */
535 PCI_SPEED_133MHz_PCIX, /* 3 */
536 PCI_SPEED_UNKNOWN, /* 4 */
537 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
538 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
539 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
540 PCI_SPEED_UNKNOWN, /* 8 */
541 PCI_SPEED_66MHz_PCIX_266, /* 9 */
542 PCI_SPEED_100MHz_PCIX_266, /* A */
543 PCI_SPEED_133MHz_PCIX_266, /* B */
544 PCI_SPEED_UNKNOWN, /* C */
545 PCI_SPEED_66MHz_PCIX_533, /* D */
546 PCI_SPEED_100MHz_PCIX_533, /* E */
547 PCI_SPEED_133MHz_PCIX_533 /* F */
550 const unsigned char pcie_link_speed[] = {
551 PCI_SPEED_UNKNOWN, /* 0 */
552 PCIE_SPEED_2_5GT, /* 1 */
553 PCIE_SPEED_5_0GT, /* 2 */
554 PCIE_SPEED_8_0GT, /* 3 */
555 PCI_SPEED_UNKNOWN, /* 4 */
556 PCI_SPEED_UNKNOWN, /* 5 */
557 PCI_SPEED_UNKNOWN, /* 6 */
558 PCI_SPEED_UNKNOWN, /* 7 */
559 PCI_SPEED_UNKNOWN, /* 8 */
560 PCI_SPEED_UNKNOWN, /* 9 */
561 PCI_SPEED_UNKNOWN, /* A */
562 PCI_SPEED_UNKNOWN, /* B */
563 PCI_SPEED_UNKNOWN, /* C */
564 PCI_SPEED_UNKNOWN, /* D */
565 PCI_SPEED_UNKNOWN, /* E */
566 PCI_SPEED_UNKNOWN /* F */
569 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
571 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
573 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
575 static unsigned char agp_speeds[] = {
583 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
589 else if (agpstat & 2)
591 else if (agpstat & 1)
603 return agp_speeds[index];
606 static void pci_set_bus_speed(struct pci_bus *bus)
608 struct pci_dev *bridge = bus->self;
611 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
613 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
617 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
618 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
620 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
621 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
624 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
627 enum pci_bus_speed max;
629 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
632 if (status & PCI_X_SSTATUS_533MHZ) {
633 max = PCI_SPEED_133MHz_PCIX_533;
634 } else if (status & PCI_X_SSTATUS_266MHZ) {
635 max = PCI_SPEED_133MHz_PCIX_266;
636 } else if (status & PCI_X_SSTATUS_133MHZ) {
637 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
638 max = PCI_SPEED_133MHz_PCIX_ECC;
640 max = PCI_SPEED_133MHz_PCIX;
642 max = PCI_SPEED_66MHz_PCIX;
645 bus->max_bus_speed = max;
646 bus->cur_bus_speed = pcix_bus_speed[
647 (status & PCI_X_SSTATUS_FREQ) >> 6];
652 if (pci_is_pcie(bridge)) {
656 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
657 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
659 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
660 pcie_update_link_speed(bus, linksta);
664 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
665 struct pci_dev *bridge, int busnr)
667 struct pci_bus *child;
672 * Allocate a new bus, and inherit stuff from the parent..
674 child = pci_alloc_bus(parent);
678 child->parent = parent;
679 child->ops = parent->ops;
680 child->msi = parent->msi;
681 child->sysdata = parent->sysdata;
682 child->bus_flags = parent->bus_flags;
684 /* initialize some portions of the bus device, but don't register it
685 * now as the parent is not properly set up yet.
687 child->dev.class = &pcibus_class;
688 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
691 * Set up the primary, secondary and subordinate
694 child->number = child->busn_res.start = busnr;
695 child->primary = parent->busn_res.start;
696 child->busn_res.end = 0xff;
699 child->dev.parent = parent->bridge;
703 child->self = bridge;
704 child->bridge = get_device(&bridge->dev);
705 child->dev.parent = child->bridge;
706 pci_set_bus_of_node(child);
707 pci_set_bus_speed(child);
709 /* Set up default resource pointers and names.. */
710 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
711 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
712 child->resource[i]->name = child->name;
714 bridge->subordinate = child;
717 ret = device_register(&child->dev);
720 pcibios_add_bus(child);
722 /* Create legacy_io and legacy_mem files for this bus */
723 pci_create_legacy_files(child);
728 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
731 struct pci_bus *child;
733 child = pci_alloc_child_bus(parent, dev, busnr);
735 down_write(&pci_bus_sem);
736 list_add_tail(&child->node, &parent->children);
737 up_write(&pci_bus_sem);
741 EXPORT_SYMBOL(pci_add_new_bus);
743 static void pci_enable_crs(struct pci_dev *pdev)
747 /* Enable CRS Software Visibility if supported */
748 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
749 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
750 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
751 PCI_EXP_RTCTL_CRSSVE);
755 * If it's a bridge, configure it and scan the bus behind it.
756 * For CardBus bridges, we don't scan behind as the devices will
757 * be handled by the bridge driver itself.
759 * We need to process bridges in two passes -- first we scan those
760 * already configured by the BIOS and after we are done with all of
761 * them, we proceed to assigning numbers to the remaining buses in
762 * order to avoid overlaps between old and new bus numbers.
764 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
766 struct pci_bus *child;
767 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
770 u8 primary, secondary, subordinate;
773 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
774 primary = buses & 0xFF;
775 secondary = (buses >> 8) & 0xFF;
776 subordinate = (buses >> 16) & 0xFF;
778 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
779 secondary, subordinate, pass);
781 if (!primary && (primary != bus->number) && secondary && subordinate) {
782 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
783 primary = bus->number;
786 /* Check if setup is sensible at all */
788 (primary != bus->number || secondary <= bus->number ||
789 secondary > subordinate)) {
790 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
791 secondary, subordinate);
795 /* Disable MasterAbortMode during probing to avoid reporting
796 of bus errors (in some architectures) */
797 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
798 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
799 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
803 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
804 !is_cardbus && !broken) {
807 * Bus already configured by firmware, process it in the first
808 * pass and just note the configuration.
814 * The bus might already exist for two reasons: Either we are
815 * rescanning the bus or the bus is reachable through more than
816 * one bridge. The second case can happen with the i450NX
819 child = pci_find_bus(pci_domain_nr(bus), secondary);
821 child = pci_add_new_bus(bus, dev, secondary);
824 child->primary = primary;
825 pci_bus_insert_busn_res(child, secondary, subordinate);
826 child->bridge_ctl = bctl;
829 cmax = pci_scan_child_bus(child);
830 if (cmax > subordinate)
831 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
833 /* subordinate should equal child->busn_res.end */
834 if (subordinate > max)
838 * We need to assign a number to this bus which we always
839 * do in the second pass.
842 if (pcibios_assign_all_busses() || broken || is_cardbus)
843 /* Temporarily disable forwarding of the
844 configuration cycles on all bridges in
845 this bus segment to avoid possible
846 conflicts in the second pass between two
847 bridges programmed with overlapping
849 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
855 pci_write_config_word(dev, PCI_STATUS, 0xffff);
857 /* Prevent assigning a bus number that already exists.
858 * This can happen when a bridge is hot-plugged, so in
859 * this case we only re-scan this bus. */
860 child = pci_find_bus(pci_domain_nr(bus), max+1);
862 child = pci_add_new_bus(bus, dev, max+1);
865 pci_bus_insert_busn_res(child, max+1, 0xff);
868 buses = (buses & 0xff000000)
869 | ((unsigned int)(child->primary) << 0)
870 | ((unsigned int)(child->busn_res.start) << 8)
871 | ((unsigned int)(child->busn_res.end) << 16);
874 * yenta.c forces a secondary latency timer of 176.
875 * Copy that behaviour here.
878 buses &= ~0xff000000;
879 buses |= CARDBUS_LATENCY_TIMER << 24;
883 * We need to blast all three values with a single write.
885 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
888 child->bridge_ctl = bctl;
889 max = pci_scan_child_bus(child);
892 * For CardBus bridges, we leave 4 bus numbers
893 * as cards with a PCI-to-PCI bridge can be
896 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
897 struct pci_bus *parent = bus;
898 if (pci_find_bus(pci_domain_nr(bus),
901 while (parent->parent) {
902 if ((!pcibios_assign_all_busses()) &&
903 (parent->busn_res.end > max) &&
904 (parent->busn_res.end <= max+i)) {
907 parent = parent->parent;
911 * Often, there are two cardbus bridges
912 * -- try to leave one valid bus number
922 * Set the subordinate bus number to its real value.
924 pci_bus_update_busn_res_end(child, max);
925 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
929 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
930 pci_domain_nr(bus), child->number);
932 /* Has only triggered on CardBus, fixup is in yenta_socket */
933 while (bus->parent) {
934 if ((child->busn_res.end > bus->busn_res.end) ||
935 (child->number > bus->busn_res.end) ||
936 (child->number < bus->number) ||
937 (child->busn_res.end < bus->number)) {
938 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
940 (bus->number > child->busn_res.end &&
941 bus->busn_res.end < child->number) ?
942 "wholly" : "partially",
943 bus->self->transparent ? " transparent" : "",
951 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
955 EXPORT_SYMBOL(pci_scan_bridge);
958 * Read interrupt line and base address registers.
959 * The architecture-dependent code can tweak these, of course.
961 static void pci_read_irq(struct pci_dev *dev)
965 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
968 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
972 void set_pcie_port_type(struct pci_dev *pdev)
977 struct pci_dev *parent;
979 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
982 pdev->pcie_cap = pos;
983 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
984 pdev->pcie_flags_reg = reg16;
985 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
986 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
989 * A Root Port is always the upstream end of a Link. No PCIe
990 * component has two Links. Two Links are connected by a Switch
991 * that has a Port on each Link and internal logic to connect the
994 type = pci_pcie_type(pdev);
995 if (type == PCI_EXP_TYPE_ROOT_PORT)
996 pdev->has_secondary_link = 1;
997 else if (type == PCI_EXP_TYPE_UPSTREAM ||
998 type == PCI_EXP_TYPE_DOWNSTREAM) {
999 parent = pci_upstream_bridge(pdev);
1002 * Usually there's an upstream device (Root Port or Switch
1003 * Downstream Port), but we can't assume one exists.
1005 if (parent && !parent->has_secondary_link)
1006 pdev->has_secondary_link = 1;
1010 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1014 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1015 if (reg32 & PCI_EXP_SLTCAP_HPC)
1016 pdev->is_hotplug_bridge = 1;
1020 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1023 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1024 * when forwarding a type1 configuration request the bridge must check that
1025 * the extended register address field is zero. The bridge is not permitted
1026 * to forward the transactions and must handle it as an Unsupported Request.
1027 * Some bridges do not follow this rule and simply drop the extended register
1028 * bits, resulting in the standard config space being aliased, every 256
1029 * bytes across the entire configuration space. Test for this condition by
1030 * comparing the first dword of each potential alias to the vendor/device ID.
1032 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1033 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1035 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1037 #ifdef CONFIG_PCI_QUIRKS
1041 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1043 for (pos = PCI_CFG_SPACE_SIZE;
1044 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1045 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1057 * pci_cfg_space_size - get the configuration space size of the PCI device.
1060 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1061 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1062 * access it. Maybe we don't have a way to generate extended config space
1063 * accesses, or the device is behind a reverse Express bridge. So we try
1064 * reading the dword at 0x100 which must either be 0 or a valid extended
1065 * capability header.
1067 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1070 int pos = PCI_CFG_SPACE_SIZE;
1072 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1074 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1077 return PCI_CFG_SPACE_EXP_SIZE;
1080 return PCI_CFG_SPACE_SIZE;
1083 int pci_cfg_space_size(struct pci_dev *dev)
1089 class = dev->class >> 8;
1090 if (class == PCI_CLASS_BRIDGE_HOST)
1091 return pci_cfg_space_size_ext(dev);
1093 if (!pci_is_pcie(dev)) {
1094 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1098 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1099 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1103 return pci_cfg_space_size_ext(dev);
1106 return PCI_CFG_SPACE_SIZE;
1109 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1111 void pci_msi_setup_pci_dev(struct pci_dev *dev)
1114 * Disable the MSI hardware to avoid screaming interrupts
1115 * during boot. This is the power on reset default so
1116 * usually this should be a noop.
1118 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1120 pci_msi_set_enable(dev, 0);
1122 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1124 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1128 * pci_setup_device - fill in class and map information of a device
1129 * @dev: the device structure to fill
1131 * Initialize the device structure with information about the device's
1132 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1133 * Called at initialisation of the PCI subsystem and by CardBus services.
1134 * Returns 0 on success and negative if unknown type of device (not normal,
1135 * bridge or CardBus).
1137 int pci_setup_device(struct pci_dev *dev)
1141 struct pci_slot *slot;
1143 struct pci_bus_region region;
1144 struct resource *res;
1146 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1149 dev->sysdata = dev->bus->sysdata;
1150 dev->dev.parent = dev->bus->bridge;
1151 dev->dev.bus = &pci_bus_type;
1152 dev->hdr_type = hdr_type & 0x7f;
1153 dev->multifunction = !!(hdr_type & 0x80);
1154 dev->error_state = pci_channel_io_normal;
1155 set_pcie_port_type(dev);
1157 list_for_each_entry(slot, &dev->bus->slots, list)
1158 if (PCI_SLOT(dev->devfn) == slot->number)
1161 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1162 set this higher, assuming the system even supports it. */
1163 dev->dma_mask = 0xffffffff;
1165 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1166 dev->bus->number, PCI_SLOT(dev->devfn),
1167 PCI_FUNC(dev->devfn));
1169 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1170 dev->revision = class & 0xff;
1171 dev->class = class >> 8; /* upper 3 bytes */
1173 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1174 dev->vendor, dev->device, dev->hdr_type, dev->class);
1176 /* need to have dev->class ready */
1177 dev->cfg_size = pci_cfg_space_size(dev);
1179 /* "Unknown power state" */
1180 dev->current_state = PCI_UNKNOWN;
1182 pci_msi_setup_pci_dev(dev);
1184 /* Early fixups, before probing the BARs */
1185 pci_fixup_device(pci_fixup_early, dev);
1186 /* device class may be changed after fixup */
1187 class = dev->class >> 8;
1189 switch (dev->hdr_type) { /* header type */
1190 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1191 if (class == PCI_CLASS_BRIDGE_PCI)
1194 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1195 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1196 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1199 * Do the ugly legacy mode stuff here rather than broken chip
1200 * quirk code. Legacy mode ATA controllers have fixed
1201 * addresses. These are not always echoed in BAR0-3, and
1202 * BAR0-3 in a few cases contain junk!
1204 if (class == PCI_CLASS_STORAGE_IDE) {
1206 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1207 if ((progif & 1) == 0) {
1208 region.start = 0x1F0;
1210 res = &dev->resource[0];
1211 res->flags = LEGACY_IO_RESOURCE;
1212 pcibios_bus_to_resource(dev->bus, res, ®ion);
1213 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1215 region.start = 0x3F6;
1217 res = &dev->resource[1];
1218 res->flags = LEGACY_IO_RESOURCE;
1219 pcibios_bus_to_resource(dev->bus, res, ®ion);
1220 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1223 if ((progif & 4) == 0) {
1224 region.start = 0x170;
1226 res = &dev->resource[2];
1227 res->flags = LEGACY_IO_RESOURCE;
1228 pcibios_bus_to_resource(dev->bus, res, ®ion);
1229 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1231 region.start = 0x376;
1233 res = &dev->resource[3];
1234 res->flags = LEGACY_IO_RESOURCE;
1235 pcibios_bus_to_resource(dev->bus, res, ®ion);
1236 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1242 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1243 if (class != PCI_CLASS_BRIDGE_PCI)
1245 /* The PCI-to-PCI bridge spec requires that subtractive
1246 decoding (i.e. transparent) bridge must have programming
1247 interface code of 0x01. */
1249 dev->transparent = ((dev->class & 0xff) == 1);
1250 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1251 set_pcie_hotplug_bridge(dev);
1252 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1254 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1255 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1259 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1260 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1263 pci_read_bases(dev, 1, 0);
1264 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1265 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1268 default: /* unknown header */
1269 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1274 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1275 dev->class, dev->hdr_type);
1276 dev->class = PCI_CLASS_NOT_DEFINED;
1279 /* We found a fine healthy device, go go go... */
1283 static struct hpp_type0 pci_default_type0 = {
1285 .cache_line_size = 8,
1286 .latency_timer = 0x40,
1291 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1293 u16 pci_cmd, pci_bctl;
1296 hpp = &pci_default_type0;
1298 if (hpp->revision > 1) {
1300 "PCI settings rev %d not supported; using defaults\n",
1302 hpp = &pci_default_type0;
1305 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1306 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1307 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1308 if (hpp->enable_serr)
1309 pci_cmd |= PCI_COMMAND_SERR;
1310 if (hpp->enable_perr)
1311 pci_cmd |= PCI_COMMAND_PARITY;
1312 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1314 /* Program bridge control value */
1315 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1316 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1317 hpp->latency_timer);
1318 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1319 if (hpp->enable_serr)
1320 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1321 if (hpp->enable_perr)
1322 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1323 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1327 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1330 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1333 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1341 if (hpp->revision > 1) {
1342 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1348 * Don't allow _HPX to change MPS or MRRS settings. We manage
1349 * those to make sure they're consistent with the rest of the
1352 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1353 PCI_EXP_DEVCTL_READRQ;
1354 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1355 PCI_EXP_DEVCTL_READRQ);
1357 /* Initialize Device Control Register */
1358 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1359 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1361 /* Initialize Link Control Register */
1362 if (pcie_cap_has_lnkctl(dev))
1363 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1364 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1366 /* Find Advanced Error Reporting Enhanced Capability */
1367 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1371 /* Initialize Uncorrectable Error Mask Register */
1372 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1373 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1374 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1376 /* Initialize Uncorrectable Error Severity Register */
1377 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1378 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1379 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1381 /* Initialize Correctable Error Mask Register */
1382 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1383 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1384 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1386 /* Initialize Advanced Error Capabilities and Control Register */
1387 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1388 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1389 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1392 * FIXME: The following two registers are not supported yet.
1394 * o Secondary Uncorrectable Error Severity Register
1395 * o Secondary Uncorrectable Error Mask Register
1399 static void pci_configure_device(struct pci_dev *dev)
1401 struct hotplug_params hpp;
1404 memset(&hpp, 0, sizeof(hpp));
1405 ret = pci_get_hp_params(dev, &hpp);
1409 program_hpp_type2(dev, hpp.t2);
1410 program_hpp_type1(dev, hpp.t1);
1411 program_hpp_type0(dev, hpp.t0);
1414 static void pci_release_capabilities(struct pci_dev *dev)
1416 pci_vpd_release(dev);
1417 pci_iov_release(dev);
1418 pci_free_cap_save_buffers(dev);
1422 * pci_release_dev - free a pci device structure when all users of it are finished.
1423 * @dev: device that's been disconnected
1425 * Will be called only by the device core when all users of this pci device are
1428 static void pci_release_dev(struct device *dev)
1430 struct pci_dev *pci_dev;
1432 pci_dev = to_pci_dev(dev);
1433 pci_release_capabilities(pci_dev);
1434 pci_release_of_node(pci_dev);
1435 pcibios_release_device(pci_dev);
1436 pci_bus_put(pci_dev->bus);
1437 kfree(pci_dev->driver_override);
1441 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1443 struct pci_dev *dev;
1445 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1449 INIT_LIST_HEAD(&dev->bus_list);
1450 dev->dev.type = &pci_dev_type;
1451 dev->bus = pci_bus_get(bus);
1455 EXPORT_SYMBOL(pci_alloc_dev);
1457 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1462 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1465 /* some broken boards return 0 or ~0 if a slot is empty: */
1466 if (*l == 0xffffffff || *l == 0x00000000 ||
1467 *l == 0x0000ffff || *l == 0xffff0000)
1471 * Configuration Request Retry Status. Some root ports return the
1472 * actual device ID instead of the synthetic ID (0xFFFF) required
1473 * by the PCIe spec. Ignore the device ID and only check for
1476 while ((*l & 0xffff) == 0x0001) {
1482 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1484 /* Card hasn't responded in 60 seconds? Must be stuck. */
1485 if (delay > crs_timeout) {
1486 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1487 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1495 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1498 * Read the config data for a PCI device, sanity-check it
1499 * and fill in the dev structure...
1501 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1503 struct pci_dev *dev;
1506 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1509 dev = pci_alloc_dev(bus);
1514 dev->vendor = l & 0xffff;
1515 dev->device = (l >> 16) & 0xffff;
1517 pci_set_of_node(dev);
1519 if (pci_setup_device(dev)) {
1520 pci_bus_put(dev->bus);
1528 static void pci_init_capabilities(struct pci_dev *dev)
1530 /* MSI/MSI-X list */
1531 pci_msi_init_pci_dev(dev);
1533 /* Buffers for saving PCIe and PCI-X capabilities */
1534 pci_allocate_cap_save_buffers(dev);
1536 /* Power Management */
1539 /* Vital Product Data */
1540 pci_vpd_pci22_init(dev);
1542 /* Alternative Routing-ID Forwarding */
1543 pci_configure_ari(dev);
1545 /* Single Root I/O Virtualization */
1548 /* Enable ACS P2P upstream forwarding */
1549 pci_enable_acs(dev);
1552 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1556 pci_configure_device(dev);
1558 device_initialize(&dev->dev);
1559 dev->dev.release = pci_release_dev;
1561 set_dev_node(&dev->dev, pcibus_to_node(bus));
1562 dev->dev.dma_mask = &dev->dma_mask;
1563 dev->dev.dma_parms = &dev->dma_parms;
1564 dev->dev.coherent_dma_mask = 0xffffffffull;
1565 of_pci_dma_configure(dev);
1567 pci_set_dma_max_seg_size(dev, 65536);
1568 pci_set_dma_seg_boundary(dev, 0xffffffff);
1570 /* Fix up broken headers */
1571 pci_fixup_device(pci_fixup_header, dev);
1573 /* moved out from quirk header fixup code */
1574 pci_reassigndev_resource_alignment(dev);
1576 /* Clear the state_saved flag. */
1577 dev->state_saved = false;
1579 /* Initialize various capabilities */
1580 pci_init_capabilities(dev);
1583 * Add the device to our list of discovered devices
1584 * and the bus list for fixup functions, etc.
1586 down_write(&pci_bus_sem);
1587 list_add_tail(&dev->bus_list, &bus->devices);
1588 up_write(&pci_bus_sem);
1590 ret = pcibios_add_device(dev);
1593 /* Notifier could use PCI capabilities */
1594 dev->match_driver = false;
1595 ret = device_add(&dev->dev);
1599 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1601 struct pci_dev *dev;
1603 dev = pci_get_slot(bus, devfn);
1609 dev = pci_scan_device(bus, devfn);
1613 pci_device_add(dev, bus);
1617 EXPORT_SYMBOL(pci_scan_single_device);
1619 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1625 if (pci_ari_enabled(bus)) {
1628 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1632 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1633 next_fn = PCI_ARI_CAP_NFN(cap);
1635 return 0; /* protect against malformed list */
1640 /* dev may be NULL for non-contiguous multifunction devices */
1641 if (!dev || dev->multifunction)
1642 return (fn + 1) % 8;
1647 static int only_one_child(struct pci_bus *bus)
1649 struct pci_dev *parent = bus->self;
1651 if (!parent || !pci_is_pcie(parent))
1653 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1655 if (parent->has_secondary_link &&
1656 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1662 * pci_scan_slot - scan a PCI slot on a bus for devices.
1663 * @bus: PCI bus to scan
1664 * @devfn: slot number to scan (must have zero function.)
1666 * Scan a PCI slot on the specified PCI bus for devices, adding
1667 * discovered devices to the @bus->devices list. New devices
1668 * will not have is_added set.
1670 * Returns the number of new devices found.
1672 int pci_scan_slot(struct pci_bus *bus, int devfn)
1674 unsigned fn, nr = 0;
1675 struct pci_dev *dev;
1677 if (only_one_child(bus) && (devfn > 0))
1678 return 0; /* Already scanned the entire slot */
1680 dev = pci_scan_single_device(bus, devfn);
1686 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1687 dev = pci_scan_single_device(bus, devfn + fn);
1691 dev->multifunction = 1;
1695 /* only one slot has pcie device */
1696 if (bus->self && nr)
1697 pcie_aspm_init_link_state(bus->self);
1701 EXPORT_SYMBOL(pci_scan_slot);
1703 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1707 if (!pci_is_pcie(dev))
1711 * We don't have a way to change MPS settings on devices that have
1712 * drivers attached. A hot-added device might support only the minimum
1713 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1714 * where devices may be hot-added, we limit the fabric MPS to 128 so
1715 * hot-added devices will work correctly.
1717 * However, if we hot-add a device to a slot directly below a Root
1718 * Port, it's impossible for there to be other existing devices below
1719 * the port. We don't limit the MPS in this case because we can
1720 * reconfigure MPS on both the Root Port and the hot-added device,
1721 * and there are no other devices involved.
1723 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1725 if (dev->is_hotplug_bridge &&
1726 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1729 if (*smpss > dev->pcie_mpss)
1730 *smpss = dev->pcie_mpss;
1735 static void pcie_write_mps(struct pci_dev *dev, int mps)
1739 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1740 mps = 128 << dev->pcie_mpss;
1742 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1744 /* For "Performance", the assumption is made that
1745 * downstream communication will never be larger than
1746 * the MRRS. So, the MPS only needs to be configured
1747 * for the upstream communication. This being the case,
1748 * walk from the top down and set the MPS of the child
1749 * to that of the parent bus.
1751 * Configure the device MPS with the smaller of the
1752 * device MPSS or the bridge MPS (which is assumed to be
1753 * properly configured at this point to the largest
1754 * allowable MPS based on its parent bus).
1756 mps = min(mps, pcie_get_mps(dev->bus->self));
1759 rc = pcie_set_mps(dev, mps);
1761 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1764 static void pcie_write_mrrs(struct pci_dev *dev)
1768 /* In the "safe" case, do not configure the MRRS. There appear to be
1769 * issues with setting MRRS to 0 on a number of devices.
1771 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1774 /* For Max performance, the MRRS must be set to the largest supported
1775 * value. However, it cannot be configured larger than the MPS the
1776 * device or the bus can support. This should already be properly
1777 * configured by a prior call to pcie_write_mps.
1779 mrrs = pcie_get_mps(dev);
1781 /* MRRS is a R/W register. Invalid values can be written, but a
1782 * subsequent read will verify if the value is acceptable or not.
1783 * If the MRRS value provided is not acceptable (e.g., too large),
1784 * shrink the value until it is acceptable to the HW.
1786 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1787 rc = pcie_set_readrq(dev, mrrs);
1791 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1796 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1799 static void pcie_bus_detect_mps(struct pci_dev *dev)
1801 struct pci_dev *bridge = dev->bus->self;
1807 mps = pcie_get_mps(dev);
1808 p_mps = pcie_get_mps(bridge);
1811 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1812 mps, pci_name(bridge), p_mps);
1815 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1819 if (!pci_is_pcie(dev))
1822 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1823 pcie_bus_detect_mps(dev);
1827 mps = 128 << *(u8 *)data;
1828 orig_mps = pcie_get_mps(dev);
1830 pcie_write_mps(dev, mps);
1831 pcie_write_mrrs(dev);
1833 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1834 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1835 orig_mps, pcie_get_readrq(dev));
1840 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1841 * parents then children fashion. If this changes, then this code will not
1844 void pcie_bus_configure_settings(struct pci_bus *bus)
1851 if (!pci_is_pcie(bus->self))
1854 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1855 * to be aware of the MPS of the destination. To work around this,
1856 * simply force the MPS of the entire system to the smallest possible.
1858 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1861 if (pcie_bus_config == PCIE_BUS_SAFE) {
1862 smpss = bus->self->pcie_mpss;
1864 pcie_find_smpss(bus->self, &smpss);
1865 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1868 pcie_bus_configure_set(bus->self, &smpss);
1869 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1871 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1873 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1875 unsigned int devfn, pass, max = bus->busn_res.start;
1876 struct pci_dev *dev;
1878 dev_dbg(&bus->dev, "scanning bus\n");
1880 /* Go find them, Rover! */
1881 for (devfn = 0; devfn < 0x100; devfn += 8)
1882 pci_scan_slot(bus, devfn);
1884 /* Reserve buses for SR-IOV capability. */
1885 max += pci_iov_bus_range(bus);
1888 * After performing arch-dependent fixup of the bus, look behind
1889 * all PCI-to-PCI bridges on this bus.
1891 if (!bus->is_added) {
1892 dev_dbg(&bus->dev, "fixups for bus\n");
1893 pcibios_fixup_bus(bus);
1897 for (pass = 0; pass < 2; pass++)
1898 list_for_each_entry(dev, &bus->devices, bus_list) {
1899 if (pci_is_bridge(dev))
1900 max = pci_scan_bridge(bus, dev, max, pass);
1904 * We've scanned the bus and so we know all about what's on
1905 * the other side of any bridges that may be on this bus plus
1908 * Return how far we've got finding sub-buses.
1910 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1913 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1916 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1917 * @bridge: Host bridge to set up.
1919 * Default empty implementation. Replace with an architecture-specific setup
1920 * routine, if necessary.
1922 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
1927 void __weak pcibios_add_bus(struct pci_bus *bus)
1931 void __weak pcibios_remove_bus(struct pci_bus *bus)
1935 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1936 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1939 struct pci_host_bridge *bridge;
1940 struct pci_bus *b, *b2;
1941 struct resource_entry *window, *n;
1942 struct resource *res;
1943 resource_size_t offset;
1947 b = pci_alloc_bus(NULL);
1951 b->sysdata = sysdata;
1953 b->number = b->busn_res.start = bus;
1954 pci_bus_assign_domain_nr(b, parent);
1955 b2 = pci_find_bus(pci_domain_nr(b), bus);
1957 /* If we already got to this bus through a different bridge, ignore it */
1958 dev_dbg(&b2->dev, "bus already known\n");
1962 bridge = pci_alloc_host_bridge(b);
1966 bridge->dev.parent = parent;
1967 bridge->dev.release = pci_release_host_bridge_dev;
1968 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1969 error = pcibios_root_bridge_prepare(bridge);
1975 error = device_register(&bridge->dev);
1977 put_device(&bridge->dev);
1980 b->bridge = get_device(&bridge->dev);
1981 device_enable_async_suspend(b->bridge);
1982 pci_set_bus_of_node(b);
1985 set_dev_node(b->bridge, pcibus_to_node(b));
1987 b->dev.class = &pcibus_class;
1988 b->dev.parent = b->bridge;
1989 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1990 error = device_register(&b->dev);
1992 goto class_dev_reg_err;
1996 /* Create legacy_io and legacy_mem files for this bus */
1997 pci_create_legacy_files(b);
2000 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2002 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2004 /* Add initial resources to the bus */
2005 resource_list_for_each_entry_safe(window, n, resources) {
2006 list_move_tail(&window->node, &bridge->windows);
2008 offset = window->offset;
2009 if (res->flags & IORESOURCE_BUS)
2010 pci_bus_insert_busn_res(b, bus, res->end);
2012 pci_bus_add_resource(b, res, 0);
2014 if (resource_type(res) == IORESOURCE_IO)
2015 fmt = " (bus address [%#06llx-%#06llx])";
2017 fmt = " (bus address [%#010llx-%#010llx])";
2018 snprintf(bus_addr, sizeof(bus_addr), fmt,
2019 (unsigned long long) (res->start - offset),
2020 (unsigned long long) (res->end - offset));
2023 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2026 down_write(&pci_bus_sem);
2027 list_add_tail(&b->node, &pci_root_buses);
2028 up_write(&pci_bus_sem);
2033 put_device(&bridge->dev);
2034 device_unregister(&bridge->dev);
2039 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2041 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2043 struct resource *res = &b->busn_res;
2044 struct resource *parent_res, *conflict;
2048 res->flags = IORESOURCE_BUS;
2050 if (!pci_is_root_bus(b))
2051 parent_res = &b->parent->busn_res;
2053 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2054 res->flags |= IORESOURCE_PCI_FIXED;
2057 conflict = request_resource_conflict(parent_res, res);
2060 dev_printk(KERN_DEBUG, &b->dev,
2061 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2062 res, pci_is_root_bus(b) ? "domain " : "",
2063 parent_res, conflict->name, conflict);
2065 return conflict == NULL;
2068 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2070 struct resource *res = &b->busn_res;
2071 struct resource old_res = *res;
2072 resource_size_t size;
2075 if (res->start > bus_max)
2078 size = bus_max - res->start + 1;
2079 ret = adjust_resource(res, res->start, size);
2080 dev_printk(KERN_DEBUG, &b->dev,
2081 "busn_res: %pR end %s updated to %02x\n",
2082 &old_res, ret ? "can not be" : "is", bus_max);
2084 if (!ret && !res->parent)
2085 pci_bus_insert_busn_res(b, res->start, res->end);
2090 void pci_bus_release_busn_res(struct pci_bus *b)
2092 struct resource *res = &b->busn_res;
2095 if (!res->flags || !res->parent)
2098 ret = release_resource(res);
2099 dev_printk(KERN_DEBUG, &b->dev,
2100 "busn_res: %pR %s released\n",
2101 res, ret ? "can not be" : "is");
2104 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2105 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2107 struct resource_entry *window;
2112 resource_list_for_each_entry(window, resources)
2113 if (window->res->flags & IORESOURCE_BUS) {
2118 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2124 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2126 pci_bus_insert_busn_res(b, bus, 255);
2129 max = pci_scan_child_bus(b);
2132 pci_bus_update_busn_res_end(b, max);
2136 EXPORT_SYMBOL(pci_scan_root_bus);
2138 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2141 LIST_HEAD(resources);
2144 pci_add_resource(&resources, &ioport_resource);
2145 pci_add_resource(&resources, &iomem_resource);
2146 pci_add_resource(&resources, &busn_resource);
2147 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2149 pci_scan_child_bus(b);
2151 pci_free_resource_list(&resources);
2155 EXPORT_SYMBOL(pci_scan_bus);
2158 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2159 * @bridge: PCI bridge for the bus to scan
2161 * Scan a PCI bus and child buses for new devices, add them,
2162 * and enable them, resizing bridge mmio/io resource if necessary
2163 * and possible. The caller must ensure the child devices are already
2164 * removed for resizing to occur.
2166 * Returns the max number of subordinate bus discovered.
2168 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2171 struct pci_bus *bus = bridge->subordinate;
2173 max = pci_scan_child_bus(bus);
2175 pci_assign_unassigned_bridge_resources(bridge);
2177 pci_bus_add_devices(bus);
2183 * pci_rescan_bus - scan a PCI bus for devices.
2184 * @bus: PCI bus to scan
2186 * Scan a PCI bus and child buses for new devices, adds them,
2189 * Returns the max number of subordinate bus discovered.
2191 unsigned int pci_rescan_bus(struct pci_bus *bus)
2195 max = pci_scan_child_bus(bus);
2196 pci_assign_unassigned_bus_resources(bus);
2197 pci_bus_add_devices(bus);
2201 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2204 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2205 * routines should always be executed under this mutex.
2207 static DEFINE_MUTEX(pci_rescan_remove_lock);
2209 void pci_lock_rescan_remove(void)
2211 mutex_lock(&pci_rescan_remove_lock);
2213 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2215 void pci_unlock_rescan_remove(void)
2217 mutex_unlock(&pci_rescan_remove_lock);
2219 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2221 static int __init pci_sort_bf_cmp(const struct device *d_a,
2222 const struct device *d_b)
2224 const struct pci_dev *a = to_pci_dev(d_a);
2225 const struct pci_dev *b = to_pci_dev(d_b);
2227 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2228 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2230 if (a->bus->number < b->bus->number) return -1;
2231 else if (a->bus->number > b->bus->number) return 1;
2233 if (a->devfn < b->devfn) return -1;
2234 else if (a->devfn > b->devfn) return 1;
2239 void __init pci_sort_breadthfirst(void)
2241 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);