2 * Procfs interface for the PCI bus.
4 * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/proc_fs.h>
12 #include <linux/seq_file.h>
13 #include <linux/smp_lock.h>
14 #include <linux/capability.h>
15 #include <asm/uaccess.h>
16 #include <asm/byteorder.h>
19 static int proc_initialized; /* = 0 */
22 proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
25 struct inode *inode = file->f_path.dentry->d_inode;
27 mutex_lock(&inode->i_mutex);
33 new = file->f_pos + off;
36 new = inode->i_size + off;
39 if (new < 0 || new > inode->i_size)
43 mutex_unlock(&inode->i_mutex);
48 proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
50 const struct inode *ino = file->f_path.dentry->d_inode;
51 const struct proc_dir_entry *dp = PDE(ino);
52 struct pci_dev *dev = dp->data;
53 unsigned int pos = *ppos;
54 unsigned int cnt, size;
57 * Normal users can read only the standardized portion of the
58 * configuration space as several chips lock up when trying to read
59 * undefined locations (think of Intel PIIX4 as a typical example).
62 if (capable(CAP_SYS_ADMIN))
64 else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
73 if (pos + nbytes > size)
77 if (!access_ok(VERIFY_WRITE, buf, cnt))
80 if ((pos & 1) && cnt) {
82 pci_user_read_config_byte(dev, pos, &val);
89 if ((pos & 3) && cnt > 2) {
91 pci_user_read_config_word(dev, pos, &val);
92 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
100 pci_user_read_config_dword(dev, pos, &val);
101 __put_user(cpu_to_le32(val), (__le32 __user *) buf);
109 pci_user_read_config_word(dev, pos, &val);
110 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
118 pci_user_read_config_byte(dev, pos, &val);
119 __put_user(val, buf);
130 proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, loff_t *ppos)
132 struct inode *ino = file->f_path.dentry->d_inode;
133 const struct proc_dir_entry *dp = PDE(ino);
134 struct pci_dev *dev = dp->data;
143 if (pos + nbytes > size)
147 if (!access_ok(VERIFY_READ, buf, cnt))
150 if ((pos & 1) && cnt) {
152 __get_user(val, buf);
153 pci_user_write_config_byte(dev, pos, val);
159 if ((pos & 3) && cnt > 2) {
161 __get_user(val, (__le16 __user *) buf);
162 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
170 __get_user(val, (__le32 __user *) buf);
171 pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
179 __get_user(val, (__le16 __user *) buf);
180 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
188 __get_user(val, buf);
189 pci_user_write_config_byte(dev, pos, val);
196 i_size_write(ino, dp->size);
200 struct pci_filp_private {
201 enum pci_mmap_state mmap_state;
205 static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
208 const struct proc_dir_entry *dp = PDE(file->f_dentry->d_inode);
209 struct pci_dev *dev = dp->data;
211 struct pci_filp_private *fpriv = file->private_data;
212 #endif /* HAVE_PCI_MMAP */
216 case PCIIOC_CONTROLLER:
217 ret = pci_domain_nr(dev->bus);
221 case PCIIOC_MMAP_IS_IO:
222 fpriv->mmap_state = pci_mmap_io;
225 case PCIIOC_MMAP_IS_MEM:
226 fpriv->mmap_state = pci_mmap_mem;
229 case PCIIOC_WRITE_COMBINE:
231 fpriv->write_combine = 1;
233 fpriv->write_combine = 0;
236 #endif /* HAVE_PCI_MMAP */
247 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
249 struct inode *inode = file->f_path.dentry->d_inode;
250 const struct proc_dir_entry *dp = PDE(inode);
251 struct pci_dev *dev = dp->data;
252 struct pci_filp_private *fpriv = file->private_data;
255 if (!capable(CAP_SYS_RAWIO))
258 /* Make sure the caller is mapping a real resource for this device */
259 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
260 if (pci_mmap_fits(dev, i, vma))
264 if (i >= PCI_ROM_RESOURCE)
267 ret = pci_mmap_page_range(dev, vma,
269 fpriv->write_combine);
276 static int proc_bus_pci_open(struct inode *inode, struct file *file)
278 struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
283 fpriv->mmap_state = pci_mmap_io;
284 fpriv->write_combine = 0;
286 file->private_data = fpriv;
291 static int proc_bus_pci_release(struct inode *inode, struct file *file)
293 kfree(file->private_data);
294 file->private_data = NULL;
298 #endif /* HAVE_PCI_MMAP */
300 static const struct file_operations proc_bus_pci_operations = {
301 .owner = THIS_MODULE,
302 .llseek = proc_bus_pci_lseek,
303 .read = proc_bus_pci_read,
304 .write = proc_bus_pci_write,
305 .unlocked_ioctl = proc_bus_pci_ioctl,
306 .compat_ioctl = proc_bus_pci_ioctl,
308 .open = proc_bus_pci_open,
309 .release = proc_bus_pci_release,
310 .mmap = proc_bus_pci_mmap,
311 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
312 .get_unmapped_area = get_pci_unmapped_area,
313 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
314 #endif /* HAVE_PCI_MMAP */
318 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
320 struct pci_dev *dev = NULL;
323 for_each_pci_dev(dev) {
330 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
332 struct pci_dev *dev = v;
335 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
339 static void pci_seq_stop(struct seq_file *m, void *v)
342 struct pci_dev *dev = v;
347 static int show_device(struct seq_file *m, void *v)
349 const struct pci_dev *dev = v;
350 const struct pci_driver *drv;
356 drv = pci_dev_driver(dev);
357 seq_printf(m, "%02x%02x\t%04x%04x\t%x",
364 /* only print standard and ROM resources to preserve compatibility */
365 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
366 resource_size_t start, end;
367 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
368 seq_printf(m, "\t%16llx",
369 (unsigned long long)(start |
370 (dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
372 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
373 resource_size_t start, end;
374 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
375 seq_printf(m, "\t%16llx",
376 dev->resource[i].start < dev->resource[i].end ?
377 (unsigned long long)(end - start) + 1 : 0);
381 seq_printf(m, "%s", drv->name);
386 static const struct seq_operations proc_bus_pci_devices_op = {
387 .start = pci_seq_start,
388 .next = pci_seq_next,
389 .stop = pci_seq_stop,
393 static struct proc_dir_entry *proc_bus_pci_dir;
395 int pci_proc_attach_device(struct pci_dev *dev)
397 struct pci_bus *bus = dev->bus;
398 struct proc_dir_entry *e;
401 if (!proc_initialized)
405 if (pci_proc_domain(bus)) {
406 sprintf(name, "%04x:%02x", pci_domain_nr(bus),
409 sprintf(name, "%02x", bus->number);
411 bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
416 sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
417 e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
418 &proc_bus_pci_operations, dev);
421 e->size = dev->cfg_size;
427 int pci_proc_detach_device(struct pci_dev *dev)
429 struct proc_dir_entry *e;
431 if ((e = dev->procent)) {
432 remove_proc_entry(e->name, dev->bus->procdir);
439 int pci_proc_attach_bus(struct pci_bus* bus)
441 struct proc_dir_entry *de = bus->procdir;
443 if (!proc_initialized)
448 sprintf(name, "%02x", bus->number);
449 de = bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
457 int pci_proc_detach_bus(struct pci_bus* bus)
459 struct proc_dir_entry *de = bus->procdir;
461 remove_proc_entry(de->name, proc_bus_pci_dir);
465 static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
467 return seq_open(file, &proc_bus_pci_devices_op);
469 static const struct file_operations proc_bus_pci_dev_operations = {
470 .owner = THIS_MODULE,
471 .open = proc_bus_pci_dev_open,
474 .release = seq_release,
477 static int __init pci_proc_init(void)
479 struct pci_dev *dev = NULL;
480 proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
481 proc_create("devices", 0, proc_bus_pci_dir,
482 &proc_bus_pci_dev_operations);
483 proc_initialized = 1;
484 for_each_pci_dev(dev)
485 pci_proc_attach_device(dev);
490 device_initcall(pci_proc_init);