2 * drivers/pci/setup-bus.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
28 #include <asm-generic/pci-bridge.h>
31 unsigned int pci_flags;
33 struct pci_dev_resource {
34 struct list_head list;
37 resource_size_t start;
39 resource_size_t add_size;
40 resource_size_t min_align;
44 static void free_list(struct list_head *head)
46 struct pci_dev_resource *dev_res, *tmp;
48 list_for_each_entry_safe(dev_res, tmp, head, list) {
49 list_del(&dev_res->list);
55 * add_to_list() - add a new resource tracker to the list
56 * @head: Head of the list
57 * @dev: device corresponding to which the resource
59 * @res: The resource to be tracked
60 * @add_size: additional size to be optionally added
63 static int add_to_list(struct list_head *head,
64 struct pci_dev *dev, struct resource *res,
65 resource_size_t add_size, resource_size_t min_align)
67 struct pci_dev_resource *tmp;
69 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
71 pr_warning("add_to_list: kmalloc() failed!\n");
77 tmp->start = res->start;
79 tmp->flags = res->flags;
80 tmp->add_size = add_size;
81 tmp->min_align = min_align;
83 list_add(&tmp->list, head);
88 static void remove_from_list(struct list_head *head,
91 struct pci_dev_resource *dev_res, *tmp;
93 list_for_each_entry_safe(dev_res, tmp, head, list) {
94 if (dev_res->res == res) {
95 list_del(&dev_res->list);
102 static resource_size_t get_res_add_size(struct list_head *head,
103 struct resource *res)
105 struct pci_dev_resource *dev_res;
107 list_for_each_entry(dev_res, head, list) {
108 if (dev_res->res == res) {
109 int idx = res - &dev_res->dev->resource[0];
111 dev_printk(KERN_DEBUG, &dev_res->dev->dev,
112 "res[%d]=%pR get_res_add_size add_size %llx\n",
114 (unsigned long long)dev_res->add_size);
116 return dev_res->add_size;
123 /* Sort resources by alignment */
124 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
128 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
130 struct pci_dev_resource *dev_res, *tmp;
131 resource_size_t r_align;
134 r = &dev->resource[i];
136 if (r->flags & IORESOURCE_PCI_FIXED)
139 if (!(r->flags) || r->parent)
142 r_align = pci_resource_alignment(dev, r);
144 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
149 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
151 panic("pdev_sort_resources(): "
152 "kmalloc() failed!\n");
156 /* fallback is smallest one or list is empty*/
158 list_for_each_entry(dev_res, head, list) {
159 resource_size_t align;
161 align = pci_resource_alignment(dev_res->dev,
164 if (r_align > align) {
169 /* Insert it just before n*/
170 list_add_tail(&tmp->list, n);
174 static void __dev_sort_resources(struct pci_dev *dev,
175 struct list_head *head)
177 u16 class = dev->class >> 8;
179 /* Don't touch classless devices or host bridges or ioapics. */
180 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
183 /* Don't touch ioapic devices already enabled by firmware */
184 if (class == PCI_CLASS_SYSTEM_PIC) {
186 pci_read_config_word(dev, PCI_COMMAND, &command);
187 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
191 pdev_sort_resources(dev, head);
194 static inline void reset_resource(struct resource *res)
202 * reassign_resources_sorted() - satisfy any additional resource requests
204 * @realloc_head : head of the list tracking requests requiring additional
206 * @head : head of the list tracking requests with allocated
209 * Walk through each element of the realloc_head and try to procure
210 * additional resources for the element, provided the element
211 * is in the head list.
213 static void reassign_resources_sorted(struct list_head *realloc_head,
214 struct list_head *head)
216 struct resource *res;
217 struct pci_dev_resource *add_res, *tmp;
218 struct pci_dev_resource *dev_res;
219 resource_size_t add_size;
222 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
223 bool found_match = false;
226 /* skip resource that has been reset */
230 /* skip this resource if not found in head list */
231 list_for_each_entry(dev_res, head, list) {
232 if (dev_res->res == res) {
237 if (!found_match)/* just skip */
240 idx = res - &add_res->dev->resource[0];
241 add_size = add_res->add_size;
242 if (!resource_size(res)) {
243 res->start = add_res->start;
244 res->end = res->start + add_size - 1;
245 if (pci_assign_resource(add_res->dev, idx))
248 resource_size_t align = add_res->min_align;
249 res->flags |= add_res->flags &
250 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
251 if (pci_reassign_resource(add_res->dev, idx,
253 dev_printk(KERN_DEBUG, &add_res->dev->dev,
254 "failed to add %llx res[%d]=%pR\n",
255 (unsigned long long)add_size,
259 list_del(&add_res->list);
265 * assign_requested_resources_sorted() - satisfy resource requests
267 * @head : head of the list tracking requests for resources
268 * @fail_head : head of the list tracking requests that could
271 * Satisfy resource requests of each element in the list. Add
272 * requests that could not satisfied to the failed_list.
274 static void assign_requested_resources_sorted(struct list_head *head,
275 struct list_head *fail_head)
277 struct resource *res;
278 struct pci_dev_resource *dev_res;
281 list_for_each_entry(dev_res, head, list) {
283 idx = res - &dev_res->dev->resource[0];
284 if (resource_size(res) &&
285 pci_assign_resource(dev_res->dev, idx)) {
288 * if the failed res is for ROM BAR, and it will
289 * be enabled later, don't add it to the list
291 if (!((idx == PCI_ROM_RESOURCE) &&
292 (!(res->flags & IORESOURCE_ROM_ENABLE))))
293 add_to_list(fail_head,
303 static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
305 struct pci_dev_resource *fail_res;
306 unsigned long mask = 0;
308 /* check failed type */
309 list_for_each_entry(fail_res, fail_head, list)
310 mask |= fail_res->flags;
313 * one pref failed resource will set IORESOURCE_MEM,
314 * as we can allocate pref in non-pref range.
315 * Will release all assigned non-pref sibling resources
316 * according to that bit.
318 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
321 static bool pci_need_to_release(unsigned long mask, struct resource *res)
323 if (res->flags & IORESOURCE_IO)
324 return !!(mask & IORESOURCE_IO);
326 /* check pref at first */
327 if (res->flags & IORESOURCE_PREFETCH) {
328 if (mask & IORESOURCE_PREFETCH)
330 /* count pref if its parent is non-pref */
331 else if ((mask & IORESOURCE_MEM) &&
332 !(res->parent->flags & IORESOURCE_PREFETCH))
338 if (res->flags & IORESOURCE_MEM)
339 return !!(mask & IORESOURCE_MEM);
341 return false; /* should not get here */
344 static void __assign_resources_sorted(struct list_head *head,
345 struct list_head *realloc_head,
346 struct list_head *fail_head)
349 * Should not assign requested resources at first.
350 * they could be adjacent, so later reassign can not reallocate
351 * them one by one in parent resource window.
352 * Try to assign requested + add_size at beginning
353 * if could do that, could get out early.
354 * if could not do that, we still try to assign requested at first,
355 * then try to reassign add_size for some resources.
357 * Separate three resource type checking if we need to release
358 * assigned resource after requested + add_size try.
359 * 1. if there is io port assign fail, will release assigned
361 * 2. if there is pref mmio assign fail, release assigned
363 * if assigned pref mmio's parent is non-pref mmio and there
364 * is non-pref mmio assign fail, will release that assigned
366 * 3. if there is non-pref mmio assign fail or pref mmio
367 * assigned fail, will release assigned non-pref mmio.
369 LIST_HEAD(save_head);
370 LIST_HEAD(local_fail_head);
371 struct pci_dev_resource *save_res;
372 struct pci_dev_resource *dev_res, *tmp_res;
373 unsigned long fail_type;
375 /* Check if optional add_size is there */
376 if (!realloc_head || list_empty(realloc_head))
377 goto requested_and_reassign;
379 /* Save original start, end, flags etc at first */
380 list_for_each_entry(dev_res, head, list) {
381 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
382 free_list(&save_head);
383 goto requested_and_reassign;
387 /* Update res in head list with add_size in realloc_head list */
388 list_for_each_entry(dev_res, head, list)
389 dev_res->res->end += get_res_add_size(realloc_head,
392 /* Try updated head list with add_size added */
393 assign_requested_resources_sorted(head, &local_fail_head);
395 /* all assigned with add_size ? */
396 if (list_empty(&local_fail_head)) {
397 /* Remove head list from realloc_head list */
398 list_for_each_entry(dev_res, head, list)
399 remove_from_list(realloc_head, dev_res->res);
400 free_list(&save_head);
405 /* check failed type */
406 fail_type = pci_fail_res_type_mask(&local_fail_head);
407 /* remove not need to be released assigned res from head list etc */
408 list_for_each_entry_safe(dev_res, tmp_res, head, list)
409 if (dev_res->res->parent &&
410 !pci_need_to_release(fail_type, dev_res->res)) {
411 /* remove it from realloc_head list */
412 remove_from_list(realloc_head, dev_res->res);
413 remove_from_list(&save_head, dev_res->res);
414 list_del(&dev_res->list);
418 free_list(&local_fail_head);
419 /* Release assigned resource */
420 list_for_each_entry(dev_res, head, list)
421 if (dev_res->res->parent)
422 release_resource(dev_res->res);
423 /* Restore start/end/flags from saved list */
424 list_for_each_entry(save_res, &save_head, list) {
425 struct resource *res = save_res->res;
427 res->start = save_res->start;
428 res->end = save_res->end;
429 res->flags = save_res->flags;
431 free_list(&save_head);
433 requested_and_reassign:
434 /* Satisfy the must-have resource requests */
435 assign_requested_resources_sorted(head, fail_head);
437 /* Try to satisfy any additional optional resource
440 reassign_resources_sorted(realloc_head, head);
444 static void pdev_assign_resources_sorted(struct pci_dev *dev,
445 struct list_head *add_head,
446 struct list_head *fail_head)
450 __dev_sort_resources(dev, &head);
451 __assign_resources_sorted(&head, add_head, fail_head);
455 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
456 struct list_head *realloc_head,
457 struct list_head *fail_head)
462 list_for_each_entry(dev, &bus->devices, bus_list)
463 __dev_sort_resources(dev, &head);
465 __assign_resources_sorted(&head, realloc_head, fail_head);
468 void pci_setup_cardbus(struct pci_bus *bus)
470 struct pci_dev *bridge = bus->self;
471 struct resource *res;
472 struct pci_bus_region region;
474 dev_info(&bridge->dev, "CardBus bridge to %pR\n",
477 res = bus->resource[0];
478 pcibios_resource_to_bus(bridge->bus, ®ion, res);
479 if (res->flags & IORESOURCE_IO) {
481 * The IO resource is allocated a range twice as large as it
482 * would normally need. This allows us to set both IO regs.
484 dev_info(&bridge->dev, " bridge window %pR\n", res);
485 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
487 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
491 res = bus->resource[1];
492 pcibios_resource_to_bus(bridge->bus, ®ion, res);
493 if (res->flags & IORESOURCE_IO) {
494 dev_info(&bridge->dev, " bridge window %pR\n", res);
495 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
497 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
501 res = bus->resource[2];
502 pcibios_resource_to_bus(bridge->bus, ®ion, res);
503 if (res->flags & IORESOURCE_MEM) {
504 dev_info(&bridge->dev, " bridge window %pR\n", res);
505 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
507 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
511 res = bus->resource[3];
512 pcibios_resource_to_bus(bridge->bus, ®ion, res);
513 if (res->flags & IORESOURCE_MEM) {
514 dev_info(&bridge->dev, " bridge window %pR\n", res);
515 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
517 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
521 EXPORT_SYMBOL(pci_setup_cardbus);
523 /* Initialize bridges with base/limit values we have collected.
524 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
525 requires that if there is no I/O ports or memory behind the
526 bridge, corresponding range must be turned off by writing base
527 value greater than limit to the bridge's base/limit registers.
529 Note: care must be taken when updating I/O base/limit registers
530 of bridges which support 32-bit I/O. This update requires two
531 config space writes, so it's quite possible that an I/O window of
532 the bridge will have some undesirable address (e.g. 0) after the
533 first write. Ditto 64-bit prefetchable MMIO. */
534 static void pci_setup_bridge_io(struct pci_bus *bus)
536 struct pci_dev *bridge = bus->self;
537 struct resource *res;
538 struct pci_bus_region region;
539 unsigned long io_mask;
540 u8 io_base_lo, io_limit_lo;
544 io_mask = PCI_IO_RANGE_MASK;
545 if (bridge->io_window_1k)
546 io_mask = PCI_IO_1K_RANGE_MASK;
548 /* Set up the top and bottom of the PCI I/O segment for this bus. */
549 res = bus->resource[0];
550 pcibios_resource_to_bus(bridge->bus, ®ion, res);
551 if (res->flags & IORESOURCE_IO) {
552 pci_read_config_word(bridge, PCI_IO_BASE, &l);
553 io_base_lo = (region.start >> 8) & io_mask;
554 io_limit_lo = (region.end >> 8) & io_mask;
555 l = ((u16) io_limit_lo << 8) | io_base_lo;
556 /* Set up upper 16 bits of I/O base/limit. */
557 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
558 dev_info(&bridge->dev, " bridge window %pR\n", res);
560 /* Clear upper 16 bits of I/O base/limit. */
564 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
565 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
566 /* Update lower 16 bits of I/O base/limit. */
567 pci_write_config_word(bridge, PCI_IO_BASE, l);
568 /* Update upper 16 bits of I/O base/limit. */
569 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
572 static void pci_setup_bridge_mmio(struct pci_bus *bus)
574 struct pci_dev *bridge = bus->self;
575 struct resource *res;
576 struct pci_bus_region region;
579 /* Set up the top and bottom of the PCI Memory segment for this bus. */
580 res = bus->resource[1];
581 pcibios_resource_to_bus(bridge->bus, ®ion, res);
582 if (res->flags & IORESOURCE_MEM) {
583 l = (region.start >> 16) & 0xfff0;
584 l |= region.end & 0xfff00000;
585 dev_info(&bridge->dev, " bridge window %pR\n", res);
589 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
592 static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
594 struct pci_dev *bridge = bus->self;
595 struct resource *res;
596 struct pci_bus_region region;
599 /* Clear out the upper 32 bits of PREF limit.
600 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
601 disables PREF range, which is ok. */
602 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
604 /* Set up PREF base/limit. */
606 res = bus->resource[2];
607 pcibios_resource_to_bus(bridge->bus, ®ion, res);
608 if (res->flags & IORESOURCE_PREFETCH) {
609 l = (region.start >> 16) & 0xfff0;
610 l |= region.end & 0xfff00000;
611 if (res->flags & IORESOURCE_MEM_64) {
612 bu = upper_32_bits(region.start);
613 lu = upper_32_bits(region.end);
615 dev_info(&bridge->dev, " bridge window %pR\n", res);
619 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
621 /* Set the upper 32 bits of PREF base & limit. */
622 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
623 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
626 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
628 struct pci_dev *bridge = bus->self;
630 dev_info(&bridge->dev, "PCI bridge to %pR\n",
633 if (type & IORESOURCE_IO)
634 pci_setup_bridge_io(bus);
636 if (type & IORESOURCE_MEM)
637 pci_setup_bridge_mmio(bus);
639 if (type & IORESOURCE_PREFETCH)
640 pci_setup_bridge_mmio_pref(bus);
642 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
645 void pci_setup_bridge(struct pci_bus *bus)
647 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
650 __pci_setup_bridge(bus, type);
653 /* Check whether the bridge supports optional I/O and
654 prefetchable memory ranges. If not, the respective
655 base/limit registers must be read-only and read as 0. */
656 static void pci_bridge_check_ranges(struct pci_bus *bus)
660 struct pci_dev *bridge = bus->self;
661 struct resource *b_res;
663 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
664 b_res[1].flags |= IORESOURCE_MEM;
666 pci_read_config_word(bridge, PCI_IO_BASE, &io);
668 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
669 pci_read_config_word(bridge, PCI_IO_BASE, &io);
670 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
673 b_res[0].flags |= IORESOURCE_IO;
675 /* DECchip 21050 pass 2 errata: the bridge may miss an address
676 disconnect boundary by one PCI data phase.
677 Workaround: do not use prefetching on this device. */
678 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
681 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
683 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
685 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
686 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
689 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
690 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
691 PCI_PREF_RANGE_TYPE_64) {
692 b_res[2].flags |= IORESOURCE_MEM_64;
693 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
697 /* double check if bridge does support 64 bit pref */
698 if (b_res[2].flags & IORESOURCE_MEM_64) {
699 u32 mem_base_hi, tmp;
700 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
702 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
704 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
706 b_res[2].flags &= ~IORESOURCE_MEM_64;
707 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
712 /* Helper function for sizing routines: find first available
713 bus resource of a given type. Note: we intentionally skip
714 the bus resources which have already been assigned (that is,
715 have non-NULL parent resource). */
716 static struct resource *find_free_bus_resource(struct pci_bus *bus,
717 unsigned long type_mask, unsigned long type)
722 pci_bus_for_each_resource(bus, r, i) {
723 if (r == &ioport_resource || r == &iomem_resource)
725 if (r && (r->flags & type_mask) == type && !r->parent)
731 static resource_size_t calculate_iosize(resource_size_t size,
732 resource_size_t min_size,
733 resource_size_t size1,
734 resource_size_t old_size,
735 resource_size_t align)
741 /* To be fixed in 2.5: we should have sort of HAVE_ISA
742 flag in the struct pci_bus. */
743 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
744 size = (size & 0xff) + ((size & ~0xffUL) << 2);
746 size = ALIGN(size + size1, align);
752 static resource_size_t calculate_memsize(resource_size_t size,
753 resource_size_t min_size,
754 resource_size_t size1,
755 resource_size_t old_size,
756 resource_size_t align)
764 size = ALIGN(size + size1, align);
768 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
774 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
775 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
776 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
778 static resource_size_t window_alignment(struct pci_bus *bus,
781 resource_size_t align = 1, arch_align;
783 if (type & IORESOURCE_MEM)
784 align = PCI_P2P_DEFAULT_MEM_ALIGN;
785 else if (type & IORESOURCE_IO) {
787 * Per spec, I/O windows are 4K-aligned, but some
788 * bridges have an extension to support 1K alignment.
790 if (bus->self->io_window_1k)
791 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
793 align = PCI_P2P_DEFAULT_IO_ALIGN;
796 arch_align = pcibios_window_alignment(bus, type);
797 return max(align, arch_align);
801 * pbus_size_io() - size the io window of a given bus
804 * @min_size : the minimum io window that must to be allocated
805 * @add_size : additional optional io window
806 * @realloc_head : track the additional io window on this list
808 * Sizing the IO windows of the PCI-PCI bridge is trivial,
809 * since these windows have 1K or 4K granularity and the IO ranges
810 * of non-bridge PCI devices are limited to 256 bytes.
811 * We must be careful with the ISA aliasing though.
813 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
814 resource_size_t add_size, struct list_head *realloc_head)
817 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
819 resource_size_t size = 0, size0 = 0, size1 = 0;
820 resource_size_t children_add_size = 0;
821 resource_size_t min_align, align;
826 min_align = window_alignment(bus, IORESOURCE_IO);
827 list_for_each_entry(dev, &bus->devices, bus_list) {
830 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
831 struct resource *r = &dev->resource[i];
832 unsigned long r_size;
834 if (r->parent || !(r->flags & IORESOURCE_IO))
836 r_size = resource_size(r);
839 /* Might be re-aligned for ISA */
844 align = pci_resource_alignment(dev, r);
845 if (align > min_align)
849 children_add_size += get_res_add_size(realloc_head, r);
853 size0 = calculate_iosize(size, min_size, size1,
854 resource_size(b_res), min_align);
855 if (children_add_size > add_size)
856 add_size = children_add_size;
857 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
858 calculate_iosize(size, min_size, add_size + size1,
859 resource_size(b_res), min_align);
860 if (!size0 && !size1) {
861 if (b_res->start || b_res->end)
862 dev_info(&bus->self->dev, "disabling bridge window "
863 "%pR to %pR (unused)\n", b_res,
869 b_res->start = min_align;
870 b_res->end = b_res->start + size0 - 1;
871 b_res->flags |= IORESOURCE_STARTALIGN;
872 if (size1 > size0 && realloc_head) {
873 add_to_list(realloc_head, bus->self, b_res, size1-size0,
875 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
876 "%pR to %pR add_size %llx\n", b_res,
878 (unsigned long long)size1-size0);
882 static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
885 resource_size_t align = 0;
886 resource_size_t min_align = 0;
889 for (order = 0; order <= max_order; order++) {
890 resource_size_t align1 = 1;
892 align1 <<= (order + 20);
896 else if (ALIGN(align + min_align, min_align) < align1)
897 min_align = align1 >> 1;
898 align += aligns[order];
905 * pbus_size_mem() - size the memory window of a given bus
908 * @mask: mask the resource flag, then compare it with type
909 * @type: the type of free resource from bridge
910 * @type2: second match type
911 * @type3: third match type
912 * @min_size : the minimum memory window that must to be allocated
913 * @add_size : additional optional memory window
914 * @realloc_head : track the additional memory window on this list
916 * Calculate the size of the bus and minimal alignment which
917 * guarantees that all child resources fit in this size.
919 * Returns -ENOSPC if there's no available bus resource of the desired type.
920 * Otherwise, sets the bus resource start/end to indicate the required
921 * size, adds things to realloc_head (if supplied), and returns 0.
923 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
924 unsigned long type, unsigned long type2,
926 resource_size_t min_size, resource_size_t add_size,
927 struct list_head *realloc_head)
930 resource_size_t min_align, align, size, size0, size1;
931 resource_size_t aligns[14]; /* Alignments from 1Mb to 8Gb */
932 int order, max_order;
933 struct resource *b_res = find_free_bus_resource(bus,
934 mask | IORESOURCE_PREFETCH, type);
935 resource_size_t children_add_size = 0;
940 memset(aligns, 0, sizeof(aligns));
944 list_for_each_entry(dev, &bus->devices, bus_list) {
947 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
948 struct resource *r = &dev->resource[i];
949 resource_size_t r_size;
951 if (r->parent || ((r->flags & mask) != type &&
952 (r->flags & mask) != type2 &&
953 (r->flags & mask) != type3))
955 r_size = resource_size(r);
956 #ifdef CONFIG_PCI_IOV
957 /* put SRIOV requested res to the optional list */
958 if (realloc_head && i >= PCI_IOV_RESOURCES &&
959 i <= PCI_IOV_RESOURCE_END) {
960 r->end = r->start - 1;
961 add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
962 children_add_size += r_size;
967 * aligns[0] is for 1MB (since bridge memory
968 * windows are always at least 1MB aligned), so
969 * keep "order" from being negative for smaller
972 align = pci_resource_alignment(dev, r);
973 order = __ffs(align) - 20;
976 if (order >= ARRAY_SIZE(aligns)) {
977 dev_warn(&dev->dev, "disabling BAR %d: %pR "
978 "(bad alignment %#llx)\n", i, r,
979 (unsigned long long) align);
984 /* Exclude ranges with size > align from
985 calculation of the alignment. */
987 aligns[order] += align;
988 if (order > max_order)
992 children_add_size += get_res_add_size(realloc_head, r);
996 min_align = calculate_mem_align(aligns, max_order);
997 min_align = max(min_align, window_alignment(bus, b_res->flags));
998 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
999 if (children_add_size > add_size)
1000 add_size = children_add_size;
1001 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
1002 calculate_memsize(size, min_size, add_size,
1003 resource_size(b_res), min_align);
1004 if (!size0 && !size1) {
1005 if (b_res->start || b_res->end)
1006 dev_info(&bus->self->dev, "disabling bridge window "
1007 "%pR to %pR (unused)\n", b_res,
1012 b_res->start = min_align;
1013 b_res->end = size0 + min_align - 1;
1014 b_res->flags |= IORESOURCE_STARTALIGN;
1015 if (size1 > size0 && realloc_head) {
1016 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
1017 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
1018 "%pR to %pR add_size %llx\n", b_res,
1019 &bus->busn_res, (unsigned long long)size1-size0);
1024 unsigned long pci_cardbus_resource_alignment(struct resource *res)
1026 if (res->flags & IORESOURCE_IO)
1027 return pci_cardbus_io_size;
1028 if (res->flags & IORESOURCE_MEM)
1029 return pci_cardbus_mem_size;
1033 static void pci_bus_size_cardbus(struct pci_bus *bus,
1034 struct list_head *realloc_head)
1036 struct pci_dev *bridge = bus->self;
1037 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1038 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1041 if (b_res[0].parent)
1042 goto handle_b_res_1;
1044 * Reserve some resources for CardBus. We reserve
1045 * a fixed amount of bus space for CardBus bridges.
1047 b_res[0].start = pci_cardbus_io_size;
1048 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1049 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1051 b_res[0].end -= pci_cardbus_io_size;
1052 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1053 pci_cardbus_io_size);
1057 if (b_res[1].parent)
1058 goto handle_b_res_2;
1059 b_res[1].start = pci_cardbus_io_size;
1060 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1061 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1063 b_res[1].end -= pci_cardbus_io_size;
1064 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1065 pci_cardbus_io_size);
1069 /* MEM1 must not be pref mmio */
1070 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1071 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1072 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1073 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1074 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1078 * Check whether prefetchable memory is supported
1081 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1082 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1083 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1084 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1085 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1088 if (b_res[2].parent)
1089 goto handle_b_res_3;
1091 * If we have prefetchable memory support, allocate
1092 * two regions. Otherwise, allocate one region of
1095 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1096 b_res[2].start = pci_cardbus_mem_size;
1097 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1098 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1099 IORESOURCE_STARTALIGN;
1101 b_res[2].end -= pci_cardbus_mem_size;
1102 add_to_list(realloc_head, bridge, b_res+2,
1103 pci_cardbus_mem_size, pci_cardbus_mem_size);
1106 /* reduce that to half */
1107 b_res_3_size = pci_cardbus_mem_size;
1111 if (b_res[3].parent)
1113 b_res[3].start = pci_cardbus_mem_size;
1114 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1115 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1117 b_res[3].end -= b_res_3_size;
1118 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1119 pci_cardbus_mem_size);
1126 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1128 struct pci_dev *dev;
1129 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1130 resource_size_t additional_mem_size = 0, additional_io_size = 0;
1131 struct resource *b_res;
1134 list_for_each_entry(dev, &bus->devices, bus_list) {
1135 struct pci_bus *b = dev->subordinate;
1139 switch (dev->class >> 8) {
1140 case PCI_CLASS_BRIDGE_CARDBUS:
1141 pci_bus_size_cardbus(b, realloc_head);
1144 case PCI_CLASS_BRIDGE_PCI:
1146 __pci_bus_size_bridges(b, realloc_head);
1152 if (pci_is_root_bus(bus))
1155 switch (bus->self->class >> 8) {
1156 case PCI_CLASS_BRIDGE_CARDBUS:
1157 /* don't size cardbuses yet. */
1160 case PCI_CLASS_BRIDGE_PCI:
1161 pci_bridge_check_ranges(bus);
1162 if (bus->self->is_hotplug_bridge) {
1163 additional_io_size = pci_hotplug_io_size;
1164 additional_mem_size = pci_hotplug_mem_size;
1168 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1169 additional_io_size, realloc_head);
1172 * If there's a 64-bit prefetchable MMIO window, compute
1173 * the size required to put all 64-bit prefetchable
1176 b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1177 mask = IORESOURCE_MEM;
1178 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1179 if (b_res[2].flags & IORESOURCE_MEM_64) {
1180 prefmask |= IORESOURCE_MEM_64;
1181 ret = pbus_size_mem(bus, prefmask, prefmask,
1183 realloc_head ? 0 : additional_mem_size,
1184 additional_mem_size, realloc_head);
1187 * If successful, all non-prefetchable resources
1188 * and any 32-bit prefetchable resources will go in
1189 * the non-prefetchable window.
1193 type2 = prefmask & ~IORESOURCE_MEM_64;
1194 type3 = prefmask & ~IORESOURCE_PREFETCH;
1199 * If there is no 64-bit prefetchable window, compute the
1200 * size required to put all prefetchable resources in the
1201 * 32-bit prefetchable window (if there is one).
1204 prefmask &= ~IORESOURCE_MEM_64;
1205 ret = pbus_size_mem(bus, prefmask, prefmask,
1207 realloc_head ? 0 : additional_mem_size,
1208 additional_mem_size, realloc_head);
1211 * If successful, only non-prefetchable resources
1212 * will go in the non-prefetchable window.
1217 additional_mem_size += additional_mem_size;
1219 type2 = type3 = IORESOURCE_MEM;
1223 * Compute the size required to put everything else in the
1224 * non-prefetchable window. This includes:
1226 * - all non-prefetchable resources
1227 * - 32-bit prefetchable resources if there's a 64-bit
1228 * prefetchable window or no prefetchable window at all
1229 * - 64-bit prefetchable resources if there's no
1230 * prefetchable window at all
1232 * Note that the strategy in __pci_assign_resource() must
1233 * match that used here. Specifically, we cannot put a
1234 * 32-bit prefetchable resource in a 64-bit prefetchable
1237 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1238 realloc_head ? 0 : additional_mem_size,
1239 additional_mem_size, realloc_head);
1244 void pci_bus_size_bridges(struct pci_bus *bus)
1246 __pci_bus_size_bridges(bus, NULL);
1248 EXPORT_SYMBOL(pci_bus_size_bridges);
1250 void __pci_bus_assign_resources(const struct pci_bus *bus,
1251 struct list_head *realloc_head,
1252 struct list_head *fail_head)
1255 struct pci_dev *dev;
1257 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1259 list_for_each_entry(dev, &bus->devices, bus_list) {
1260 b = dev->subordinate;
1264 __pci_bus_assign_resources(b, realloc_head, fail_head);
1266 switch (dev->class >> 8) {
1267 case PCI_CLASS_BRIDGE_PCI:
1268 if (!pci_is_enabled(dev))
1269 pci_setup_bridge(b);
1272 case PCI_CLASS_BRIDGE_CARDBUS:
1273 pci_setup_cardbus(b);
1277 dev_info(&dev->dev, "not setting up bridge for bus "
1278 "%04x:%02x\n", pci_domain_nr(b), b->number);
1284 void pci_bus_assign_resources(const struct pci_bus *bus)
1286 __pci_bus_assign_resources(bus, NULL, NULL);
1288 EXPORT_SYMBOL(pci_bus_assign_resources);
1290 static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1291 struct list_head *add_head,
1292 struct list_head *fail_head)
1296 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1297 add_head, fail_head);
1299 b = bridge->subordinate;
1303 __pci_bus_assign_resources(b, add_head, fail_head);
1305 switch (bridge->class >> 8) {
1306 case PCI_CLASS_BRIDGE_PCI:
1307 pci_setup_bridge(b);
1310 case PCI_CLASS_BRIDGE_CARDBUS:
1311 pci_setup_cardbus(b);
1315 dev_info(&bridge->dev, "not setting up bridge for bus "
1316 "%04x:%02x\n", pci_domain_nr(b), b->number);
1320 static void pci_bridge_release_resources(struct pci_bus *bus,
1323 struct pci_dev *dev = bus->self;
1325 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1326 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1327 unsigned old_flags = 0;
1328 struct resource *b_res;
1331 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1334 * 1. if there is io port assign fail, will release bridge
1336 * 2. if there is non pref mmio assign fail, release bridge
1338 * 3. if there is 64bit pref mmio assign fail, and bridge pref
1339 * is 64bit, release bridge pref mmio.
1340 * 4. if there is pref mmio assign fail, and bridge pref is
1341 * 32bit mmio, release bridge pref mmio
1342 * 5. if there is pref mmio assign fail, and bridge pref is not
1343 * assigned, release bridge nonpref mmio.
1345 if (type & IORESOURCE_IO)
1347 else if (!(type & IORESOURCE_PREFETCH))
1349 else if ((type & IORESOURCE_MEM_64) &&
1350 (b_res[2].flags & IORESOURCE_MEM_64))
1352 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1353 (b_res[2].flags & IORESOURCE_PREFETCH))
1364 * if there are children under that, we should release them
1367 release_child_resources(r);
1368 if (!release_resource(r)) {
1369 type = old_flags = r->flags & type_mask;
1370 dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
1371 PCI_BRIDGE_RESOURCES + idx, r);
1372 /* keep the old size */
1373 r->end = resource_size(r) - 1;
1377 /* avoiding touch the one without PREF */
1378 if (type & IORESOURCE_PREFETCH)
1379 type = IORESOURCE_PREFETCH;
1380 __pci_setup_bridge(bus, type);
1381 /* for next child res under same bridge */
1382 r->flags = old_flags;
1391 * try to release pci bridge resources that is from leaf bridge,
1392 * so we can allocate big new one later
1394 static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1396 enum release_type rel_type)
1398 struct pci_dev *dev;
1399 bool is_leaf_bridge = true;
1401 list_for_each_entry(dev, &bus->devices, bus_list) {
1402 struct pci_bus *b = dev->subordinate;
1406 is_leaf_bridge = false;
1408 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1411 if (rel_type == whole_subtree)
1412 pci_bus_release_bridge_resources(b, type,
1416 if (pci_is_root_bus(bus))
1419 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1422 if ((rel_type == whole_subtree) || is_leaf_bridge)
1423 pci_bridge_release_resources(bus, type);
1426 static void pci_bus_dump_res(struct pci_bus *bus)
1428 struct resource *res;
1431 pci_bus_for_each_resource(bus, res, i) {
1432 if (!res || !res->end || !res->flags)
1435 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1439 static void pci_bus_dump_resources(struct pci_bus *bus)
1442 struct pci_dev *dev;
1445 pci_bus_dump_res(bus);
1447 list_for_each_entry(dev, &bus->devices, bus_list) {
1448 b = dev->subordinate;
1452 pci_bus_dump_resources(b);
1456 static int pci_bus_get_depth(struct pci_bus *bus)
1459 struct pci_bus *child_bus;
1461 list_for_each_entry(child_bus, &bus->children, node){
1464 ret = pci_bus_get_depth(child_bus);
1465 if (ret + 1 > depth)
1473 * -1: undefined, will auto detect later
1474 * 0: disabled by user
1475 * 1: disabled by auto detect
1476 * 2: enabled by user
1477 * 3: enabled by auto detect
1487 static enum enable_type pci_realloc_enable = undefined;
1488 void __init pci_realloc_get_opt(char *str)
1490 if (!strncmp(str, "off", 3))
1491 pci_realloc_enable = user_disabled;
1492 else if (!strncmp(str, "on", 2))
1493 pci_realloc_enable = user_enabled;
1495 static bool pci_realloc_enabled(enum enable_type enable)
1497 return enable >= user_enabled;
1500 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1501 static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1504 bool *unassigned = data;
1506 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1507 struct resource *r = &dev->resource[i];
1508 struct pci_bus_region region;
1510 /* Not assigned or rejected by kernel? */
1514 pcibios_resource_to_bus(dev->bus, ®ion, r);
1515 if (!region.start) {
1517 return 1; /* return early from pci_walk_bus() */
1524 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1525 enum enable_type enable_local)
1527 bool unassigned = false;
1529 if (enable_local != undefined)
1530 return enable_local;
1532 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1534 return auto_enabled;
1536 return enable_local;
1539 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1540 enum enable_type enable_local)
1542 return enable_local;
1547 * first try will not touch pci bridge res
1548 * second and later try will clear small leaf bridge res
1549 * will stop till to the max depth if can not find good one
1551 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1553 LIST_HEAD(realloc_head); /* list of resources that
1554 want additional resources */
1555 struct list_head *add_list = NULL;
1556 int tried_times = 0;
1557 enum release_type rel_type = leaf_only;
1558 LIST_HEAD(fail_head);
1559 struct pci_dev_resource *fail_res;
1560 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1561 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1562 int pci_try_num = 1;
1563 enum enable_type enable_local;
1565 /* don't realloc if asked to do so */
1566 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1567 if (pci_realloc_enabled(enable_local)) {
1568 int max_depth = pci_bus_get_depth(bus);
1570 pci_try_num = max_depth + 1;
1571 dev_printk(KERN_DEBUG, &bus->dev,
1572 "max bus depth: %d pci_try_num: %d\n",
1573 max_depth, pci_try_num);
1578 * last try will use add_list, otherwise will try good to have as
1579 * must have, so can realloc parent bridge resource
1581 if (tried_times + 1 == pci_try_num)
1582 add_list = &realloc_head;
1583 /* Depth first, calculate sizes and alignments of all
1584 subordinate buses. */
1585 __pci_bus_size_bridges(bus, add_list);
1587 /* Depth last, allocate resources and update the hardware. */
1588 __pci_bus_assign_resources(bus, add_list, &fail_head);
1590 BUG_ON(!list_empty(add_list));
1593 /* any device complain? */
1594 if (list_empty(&fail_head))
1597 if (tried_times >= pci_try_num) {
1598 if (enable_local == undefined)
1599 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1600 else if (enable_local == auto_enabled)
1601 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1603 free_list(&fail_head);
1607 dev_printk(KERN_DEBUG, &bus->dev,
1608 "No. %d try to assign unassigned res\n", tried_times + 1);
1610 /* third times and later will not check if it is leaf */
1611 if ((tried_times + 1) > 2)
1612 rel_type = whole_subtree;
1615 * Try to release leaf bridge's resources that doesn't fit resource of
1616 * child device under that bridge
1618 list_for_each_entry(fail_res, &fail_head, list)
1619 pci_bus_release_bridge_resources(fail_res->dev->bus,
1620 fail_res->flags & type_mask,
1623 /* restore size and flags */
1624 list_for_each_entry(fail_res, &fail_head, list) {
1625 struct resource *res = fail_res->res;
1627 res->start = fail_res->start;
1628 res->end = fail_res->end;
1629 res->flags = fail_res->flags;
1630 if (fail_res->dev->subordinate)
1633 free_list(&fail_head);
1638 /* dump the resource on buses */
1639 pci_bus_dump_resources(bus);
1642 void __init pci_assign_unassigned_resources(void)
1644 struct pci_bus *root_bus;
1646 list_for_each_entry(root_bus, &pci_root_buses, node)
1647 pci_assign_unassigned_root_bus_resources(root_bus);
1650 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1652 struct pci_bus *parent = bridge->subordinate;
1653 LIST_HEAD(add_list); /* list of resources that
1654 want additional resources */
1655 int tried_times = 0;
1656 LIST_HEAD(fail_head);
1657 struct pci_dev_resource *fail_res;
1659 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1660 IORESOURCE_PREFETCH;
1663 __pci_bus_size_bridges(parent, &add_list);
1664 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1665 BUG_ON(!list_empty(&add_list));
1668 if (list_empty(&fail_head))
1671 if (tried_times >= 2) {
1672 /* still fail, don't need to try more */
1673 free_list(&fail_head);
1677 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1681 * Try to release leaf bridge's resources that doesn't fit resource of
1682 * child device under that bridge
1684 list_for_each_entry(fail_res, &fail_head, list)
1685 pci_bus_release_bridge_resources(fail_res->dev->bus,
1686 fail_res->flags & type_mask,
1689 /* restore size and flags */
1690 list_for_each_entry(fail_res, &fail_head, list) {
1691 struct resource *res = fail_res->res;
1693 res->start = fail_res->start;
1694 res->end = fail_res->end;
1695 res->flags = fail_res->flags;
1696 if (fail_res->dev->subordinate)
1699 free_list(&fail_head);
1704 retval = pci_reenable_device(bridge);
1706 dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);
1707 pci_set_master(bridge);
1709 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1711 void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
1713 struct pci_dev *dev;
1714 LIST_HEAD(add_list); /* list of resources that
1715 want additional resources */
1717 down_read(&pci_bus_sem);
1718 list_for_each_entry(dev, &bus->devices, bus_list)
1719 if (pci_is_bridge(dev) && pci_has_subordinate(dev))
1720 __pci_bus_size_bridges(dev->subordinate,
1722 up_read(&pci_bus_sem);
1723 __pci_bus_assign_resources(bus, &add_list, NULL);
1724 BUG_ON(!list_empty(&add_list));