2 * drivers/pci/setup-res.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
19 #include <linux/kernel.h>
20 #include <linux/export.h>
21 #include <linux/pci.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/cache.h>
25 #include <linux/slab.h>
29 void pci_update_resource(struct pci_dev *dev, int resno)
31 struct pci_bus_region region;
36 enum pci_bar_type type;
37 struct resource *res = dev->resource + resno;
40 dev_warn(&dev->dev, "can't update VF BAR%d\n", resno);
45 * Ignore resources for unimplemented BARs and unused resource slots
51 if (res->flags & IORESOURCE_UNSET)
55 * Ignore non-moveable resources. This might be legacy resources for
56 * which no functional BAR register exists or another important
57 * system resource we shouldn't move around.
59 if (res->flags & IORESOURCE_PCI_FIXED)
62 pcibios_resource_to_bus(dev->bus, ®ion, res);
64 new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
65 if (res->flags & IORESOURCE_IO)
66 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
68 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
70 reg = pci_resource_bar(dev, resno, &type);
73 if (type != pci_bar_unknown) {
74 if (!(res->flags & IORESOURCE_ROM_ENABLE))
76 new |= PCI_ROM_ADDRESS_ENABLE;
80 * We can't update a 64-bit BAR atomically, so when possible,
81 * disable decoding so that a half-updated BAR won't conflict
82 * with another device.
84 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
86 pci_read_config_word(dev, PCI_COMMAND, &cmd);
87 pci_write_config_word(dev, PCI_COMMAND,
88 cmd & ~PCI_COMMAND_MEMORY);
91 pci_write_config_dword(dev, reg, new);
92 pci_read_config_dword(dev, reg, &check);
94 if ((new ^ check) & mask) {
95 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
99 if (res->flags & IORESOURCE_MEM_64) {
100 new = region.start >> 16 >> 16;
101 pci_write_config_dword(dev, reg + 4, new);
102 pci_read_config_dword(dev, reg + 4, &check);
104 dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
110 pci_write_config_word(dev, PCI_COMMAND, cmd);
113 int pci_claim_resource(struct pci_dev *dev, int resource)
115 struct resource *res = &dev->resource[resource];
116 struct resource *root, *conflict;
118 if (res->flags & IORESOURCE_UNSET) {
119 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
124 root = pci_find_parent_resource(dev, res);
126 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
128 res->flags |= IORESOURCE_UNSET;
132 conflict = request_resource_conflict(root, res);
134 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
135 resource, res, conflict->name, conflict);
136 res->flags |= IORESOURCE_UNSET;
142 EXPORT_SYMBOL(pci_claim_resource);
144 void pci_disable_bridge_window(struct pci_dev *dev)
146 dev_info(&dev->dev, "disabling bridge mem windows\n");
148 /* MMIO Base/Limit */
149 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
151 /* Prefetchable MMIO Base/Limit */
152 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
153 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
154 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
158 * Generic function that returns a value indicating that the device's
159 * original BIOS BAR address was not saved and so is not available for
162 * Can be over-ridden by architecture specific code that implements
163 * reinstatement functionality rather than leaving it disabled when
164 * normal allocation attempts fail.
166 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
171 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
172 int resno, resource_size_t size)
174 struct resource *root, *conflict;
175 resource_size_t fw_addr, start, end;
177 fw_addr = pcibios_retrieve_fw_addr(dev, resno);
183 res->start = fw_addr;
184 res->end = res->start + size - 1;
186 root = pci_find_parent_resource(dev, res);
188 if (res->flags & IORESOURCE_IO)
189 root = &ioport_resource;
191 root = &iomem_resource;
194 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
196 conflict = request_resource_conflict(root, res);
198 dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
199 resno, res, conflict->name, conflict);
207 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
208 int resno, resource_size_t size, resource_size_t align)
210 struct resource *res = dev->resource + resno;
214 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
217 * First, try exact prefetching match. Even if a 64-bit
218 * prefetchable bridge window is below 4GB, we can't put a 32-bit
219 * prefetchable resource in it because pbus_size_mem() assumes a
220 * 64-bit window will contain no 32-bit resources. If we assign
221 * things differently than they were sized, not everything will fit.
223 ret = pci_bus_alloc_resource(bus, res, size, align, min,
224 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
225 pcibios_align_resource, dev);
230 * If the prefetchable window is only 32 bits wide, we can put
231 * 64-bit prefetchable resources in it.
233 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
234 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
235 ret = pci_bus_alloc_resource(bus, res, size, align, min,
237 pcibios_align_resource, dev);
243 * If we didn't find a better match, we can put any memory resource
244 * in a non-prefetchable window. If this resource is 32 bits and
245 * non-prefetchable, the first call already tried the only possibility
246 * so we don't need to try again.
248 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
249 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
250 pcibios_align_resource, dev);
255 static int _pci_assign_resource(struct pci_dev *dev, int resno,
256 resource_size_t size, resource_size_t min_align)
262 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
263 if (!bus->parent || !bus->self->transparent)
271 int pci_assign_resource(struct pci_dev *dev, int resno)
273 struct resource *res = dev->resource + resno;
274 resource_size_t align, size;
277 res->flags |= IORESOURCE_UNSET;
278 align = pci_resource_alignment(dev, res);
280 dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
285 size = resource_size(res);
286 ret = _pci_assign_resource(dev, resno, size, align);
289 * If we failed to assign anything, let's try the address
290 * where firmware left it. That at least has a chance of
291 * working, which is better than just leaving it disabled.
294 dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
295 ret = pci_revert_fw_address(res, dev, resno, size);
299 dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
304 res->flags &= ~IORESOURCE_UNSET;
305 res->flags &= ~IORESOURCE_STARTALIGN;
306 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
307 if (resno < PCI_BRIDGE_RESOURCES)
308 pci_update_resource(dev, resno);
312 EXPORT_SYMBOL(pci_assign_resource);
314 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
315 resource_size_t min_align)
317 struct resource *res = dev->resource + resno;
319 resource_size_t new_size;
323 res->flags |= IORESOURCE_UNSET;
325 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
330 /* already aligned with min_align */
331 new_size = resource_size(res) + addsize;
332 ret = _pci_assign_resource(dev, resno, new_size, min_align);
335 dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
336 resno, res, (unsigned long long) addsize);
340 res->flags &= ~IORESOURCE_UNSET;
341 res->flags &= ~IORESOURCE_STARTALIGN;
342 dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
343 resno, res, (unsigned long long) addsize);
344 if (resno < PCI_BRIDGE_RESOURCES)
345 pci_update_resource(dev, resno);
350 int pci_enable_resources(struct pci_dev *dev, int mask)
356 pci_read_config_word(dev, PCI_COMMAND, &cmd);
359 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
360 if (!(mask & (1 << i)))
363 r = &dev->resource[i];
365 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
367 if ((i == PCI_ROM_RESOURCE) &&
368 (!(r->flags & IORESOURCE_ROM_ENABLE)))
371 if (r->flags & IORESOURCE_UNSET) {
372 dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
378 dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
383 if (r->flags & IORESOURCE_IO)
384 cmd |= PCI_COMMAND_IO;
385 if (r->flags & IORESOURCE_MEM)
386 cmd |= PCI_COMMAND_MEMORY;
389 if (cmd != old_cmd) {
390 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
392 pci_write_config_word(dev, PCI_COMMAND, cmd);