2 * drivers/pci/setup-res.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/cache.h>
25 #include <linux/slab.h>
29 void pci_update_resource(struct pci_dev *dev, int resno)
31 struct pci_bus_region region;
34 enum pci_bar_type type;
35 struct resource *res = dev->resource + resno;
38 * Ignore resources for unimplemented BARs and unused resource slots
45 * Ignore non-moveable resources. This might be legacy resources for
46 * which no functional BAR register exists or another important
47 * system resource we shouldn't move around.
49 if (res->flags & IORESOURCE_PCI_FIXED)
52 pcibios_resource_to_bus(dev, ®ion, res);
54 new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
55 if (res->flags & IORESOURCE_IO)
56 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
58 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
60 reg = pci_resource_bar(dev, resno, &type);
63 if (type != pci_bar_unknown) {
64 if (!(res->flags & IORESOURCE_ROM_ENABLE))
66 new |= PCI_ROM_ADDRESS_ENABLE;
69 pci_write_config_dword(dev, reg, new);
70 pci_read_config_dword(dev, reg, &check);
72 if ((new ^ check) & mask) {
73 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
77 if (res->flags & IORESOURCE_MEM_64) {
78 new = region.start >> 16 >> 16;
79 pci_write_config_dword(dev, reg + 4, new);
80 pci_read_config_dword(dev, reg + 4, &check);
82 dev_err(&dev->dev, "BAR %d: error updating "
83 "(high %#08x != %#08x)\n", resno, new, check);
86 res->flags &= ~IORESOURCE_UNSET;
87 dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
88 resno, res, (unsigned long long)region.start,
89 (unsigned long long)region.end);
92 int pci_claim_resource(struct pci_dev *dev, int resource)
94 struct resource *res = &dev->resource[resource];
95 struct resource *root, *conflict;
97 root = pci_find_parent_resource(dev, res);
99 dev_info(&dev->dev, "no compatible bridge window for %pR\n",
104 conflict = request_resource_conflict(root, res);
107 "address space collision: %pR conflicts with %s %pR\n",
108 res, conflict->name, conflict);
114 EXPORT_SYMBOL(pci_claim_resource);
116 #ifdef CONFIG_PCI_QUIRKS
117 void pci_disable_bridge_window(struct pci_dev *dev)
119 dev_info(&dev->dev, "disabling bridge mem windows\n");
121 /* MMIO Base/Limit */
122 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
124 /* Prefetchable MMIO Base/Limit */
125 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
126 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
127 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
129 #endif /* CONFIG_PCI_QUIRKS */
133 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
134 int resno, resource_size_t size, resource_size_t align)
136 struct resource *res = dev->resource + resno;
140 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
142 /* First, try exact prefetching match.. */
143 ret = pci_bus_alloc_resource(bus, res, size, align, min,
145 pcibios_align_resource, dev);
147 if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
151 * But a prefetching area can handle a non-prefetching
152 * window (it will just not perform as well).
154 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
155 pcibios_align_resource, dev);
160 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
161 int resno, resource_size_t size)
163 struct resource *root, *conflict;
164 resource_size_t start, end;
167 if (res->flags & IORESOURCE_IO)
168 root = &ioport_resource;
170 root = &iomem_resource;
174 res->start = dev->fw_addr[resno];
175 res->end = res->start + size - 1;
176 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
178 conflict = request_resource_conflict(root, res);
181 "BAR %d: %pR conflicts with %s %pR\n", resno,
182 res, conflict->name, conflict);
190 static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
192 struct resource *res = dev->resource + resno;
198 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
199 if (!bus->parent || !bus->self->transparent)
205 if (res->flags & IORESOURCE_MEM)
206 if (res->flags & IORESOURCE_PREFETCH)
210 else if (res->flags & IORESOURCE_IO)
215 "BAR %d: can't assign %s (size %#llx)\n",
216 resno, type, (unsigned long long) resource_size(res));
222 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
223 resource_size_t min_align)
225 struct resource *res = dev->resource + resno;
226 resource_size_t new_size;
230 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resouce %pR "
235 new_size = resource_size(res) + addsize + min_align;
236 ret = _pci_assign_resource(dev, resno, new_size, min_align);
238 res->flags &= ~IORESOURCE_STARTALIGN;
239 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
240 if (resno < PCI_BRIDGE_RESOURCES)
241 pci_update_resource(dev, resno);
246 int pci_assign_resource(struct pci_dev *dev, int resno)
248 struct resource *res = dev->resource + resno;
249 resource_size_t align, size;
253 align = pci_resource_alignment(dev, res);
255 dev_info(&dev->dev, "BAR %d: can't assign %pR "
256 "(bogus alignment)\n", resno, res);
261 size = resource_size(res);
262 ret = _pci_assign_resource(dev, resno, size, align);
265 * If we failed to assign anything, let's try the address
266 * where firmware left it. That at least has a chance of
267 * working, which is better than just leaving it disabled.
269 if (ret < 0 && dev->fw_addr[resno])
270 ret = pci_revert_fw_address(res, dev, resno, size);
273 res->flags &= ~IORESOURCE_STARTALIGN;
274 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
275 if (resno < PCI_BRIDGE_RESOURCES)
276 pci_update_resource(dev, resno);
282 /* Sort resources by alignment */
283 void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
287 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
289 struct resource_list *list, *tmp;
290 resource_size_t r_align;
292 r = &dev->resource[i];
294 if (r->flags & IORESOURCE_PCI_FIXED)
297 if (!(r->flags) || r->parent)
300 r_align = pci_resource_alignment(dev, r);
302 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
306 for (list = head; ; list = list->next) {
307 resource_size_t align = 0;
308 struct resource_list *ln = list->next;
311 align = pci_resource_alignment(ln->dev, ln->res);
313 if (r_align > align) {
314 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
316 panic("pdev_sort_resources(): "
317 "kmalloc() failed!\n");
328 int pci_enable_resources(struct pci_dev *dev, int mask)
334 pci_read_config_word(dev, PCI_COMMAND, &cmd);
337 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
338 if (!(mask & (1 << i)))
341 r = &dev->resource[i];
343 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
345 if ((i == PCI_ROM_RESOURCE) &&
346 (!(r->flags & IORESOURCE_ROM_ENABLE)))
350 dev_err(&dev->dev, "device not available "
351 "(can't reserve %pR)\n", r);
355 if (r->flags & IORESOURCE_IO)
356 cmd |= PCI_COMMAND_IO;
357 if (r->flags & IORESOURCE_MEM)
358 cmd |= PCI_COMMAND_MEMORY;
361 if (cmd != old_cmd) {
362 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
364 pci_write_config_word(dev, PCI_COMMAND, cmd);