drivers/phy/phy-exynos5-usbdrd.c

   1 /*
   2  * Samsung EXYNOS5 SoC series USB DRD PHY driver
   3  *
   4  * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
   5  *
   6  * Copyright (C) 2014 Samsung Electronics Co., Ltd.
   7  * Author: Vivek Gautam <gautam.vivek@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/io.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/phy/phy.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/mutex.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/mfd/syscon/exynos5-pmu.h>
  26 #include <linux/regmap.h>
  27 #include <linux/regulator/consumer.h>
  28
  29 /* Exynos USB PHY registers */
  30 #define EXYNOS5_FSEL_9MHZ6              0x0
  31 #define EXYNOS5_FSEL_10MHZ              0x1
  32 #define EXYNOS5_FSEL_12MHZ              0x2
  33 #define EXYNOS5_FSEL_19MHZ2             0x3
  34 #define EXYNOS5_FSEL_20MHZ              0x4
  35 #define EXYNOS5_FSEL_24MHZ              0x5
  36 #define EXYNOS5_FSEL_50MHZ              0x7
  37
  38 /* EXYNOS5: USB 3.0 DRD PHY registers */
  39 #define EXYNOS5_DRD_LINKSYSTEM                  0x04
  40
  41 #define LINKSYSTEM_FLADJ_MASK                   (0x3f << 1)
  42 #define LINKSYSTEM_FLADJ(_x)                    ((_x) << 1)
  43 #define LINKSYSTEM_XHCI_VERSION_CONTROL         BIT(27)
  44
  45 #define EXYNOS5_DRD_PHYUTMI                     0x08
  46
  47 #define PHYUTMI_OTGDISABLE                      BIT(6)
  48 #define PHYUTMI_FORCESUSPEND                    BIT(1)
  49 #define PHYUTMI_FORCESLEEP                      BIT(0)
  50
  51 #define EXYNOS5_DRD_PHYPIPE                     0x0c
  52
  53 #define EXYNOS5_DRD_PHYCLKRST                   0x10
  54
  55 #define PHYCLKRST_EN_UTMISUSPEND                BIT(31)
  56
  57 #define PHYCLKRST_SSC_REFCLKSEL_MASK            (0xff << 23)
  58 #define PHYCLKRST_SSC_REFCLKSEL(_x)             ((_x) << 23)
  59
  60 #define PHYCLKRST_SSC_RANGE_MASK                (0x03 << 21)
  61 #define PHYCLKRST_SSC_RANGE(_x)                 ((_x) << 21)
  62
  63 #define PHYCLKRST_SSC_EN                        BIT(20)
  64 #define PHYCLKRST_REF_SSP_EN                    BIT(19)
  65 #define PHYCLKRST_REF_CLKDIV2                   BIT(18)
  66
  67 #define PHYCLKRST_MPLL_MULTIPLIER_MASK          (0x7f << 11)
  68 #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF    (0x19 << 11)
  69 #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF       (0x32 << 11)
  70 #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF     (0x68 << 11)
  71 #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF     (0x7d << 11)
  72 #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF  (0x02 << 11)
  73
  74 #define PHYCLKRST_FSEL_UTMI_MASK                (0x7 << 5)
  75 #define PHYCLKRST_FSEL_PIPE_MASK                (0x7 << 8)
  76 #define PHYCLKRST_FSEL(_x)                      ((_x) << 5)
  77 #define PHYCLKRST_FSEL_PAD_100MHZ               (0x27 << 5)
  78 #define PHYCLKRST_FSEL_PAD_24MHZ                (0x2a << 5)
  79 #define PHYCLKRST_FSEL_PAD_20MHZ                (0x31 << 5)
  80 #define PHYCLKRST_FSEL_PAD_19_2MHZ              (0x38 << 5)
  81
  82 #define PHYCLKRST_RETENABLEN                    BIT(4)
  83
  84 #define PHYCLKRST_REFCLKSEL_MASK                (0x03 << 2)
  85 #define PHYCLKRST_REFCLKSEL_PAD_REFCLK          (0x2 << 2)
  86 #define PHYCLKRST_REFCLKSEL_EXT_REFCLK          (0x3 << 2)
  87
  88 #define PHYCLKRST_PORTRESET                     BIT(1)
  89 #define PHYCLKRST_COMMONONN                     BIT(0)
  90
  91 #define EXYNOS5_DRD_PHYREG0                     0x14
  92 #define EXYNOS5_DRD_PHYREG1                     0x18
  93
  94 #define EXYNOS5_DRD_PHYPARAM0                   0x1c
  95
  96 #define PHYPARAM0_REF_USE_PAD                   BIT(31)
  97 #define PHYPARAM0_REF_LOSLEVEL_MASK             (0x1f << 26)
  98 #define PHYPARAM0_REF_LOSLEVEL                  (0x9 << 26)
  99
 100 #define EXYNOS5_DRD_PHYPARAM1                   0x20
 101
 102 #define PHYPARAM1_PCS_TXDEEMPH_MASK             (0x1f << 0)
 103 #define PHYPARAM1_PCS_TXDEEMPH                  (0x1c)
 104
 105 #define EXYNOS5_DRD_PHYTERM                     0x24
 106
 107 #define EXYNOS5_DRD_PHYTEST                     0x28
 108
 109 #define PHYTEST_POWERDOWN_SSP                   BIT(3)
 110 #define PHYTEST_POWERDOWN_HSP                   BIT(2)
 111
 112 #define EXYNOS5_DRD_PHYADP                      0x2c
 113
 114 #define EXYNOS5_DRD_PHYUTMICLKSEL               0x30
 115
 116 #define PHYUTMICLKSEL_UTMI_CLKSEL               BIT(2)
 117
 118 #define EXYNOS5_DRD_PHYRESUME                   0x34
 119 #define EXYNOS5_DRD_LINKPORT                    0x44
 120
 121 #define KHZ     1000
 122 #define MHZ     (KHZ * KHZ)
 123
 124 enum exynos5_usbdrd_phy_id {
 125         EXYNOS5_DRDPHY_UTMI,
 126         EXYNOS5_DRDPHY_PIPE3,
 127         EXYNOS5_DRDPHYS_NUM,
 128 };
 129
 130 struct phy_usb_instance;
 131 struct exynos5_usbdrd_phy;
 132
 133 struct exynos5_usbdrd_phy_config {
 134         u32 id;
 135         void (*phy_isol)(struct phy_usb_instance *inst, u32 on);
 136         void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
 137         unsigned int (*set_refclk)(struct phy_usb_instance *inst);
 138 };
 139
 140 struct exynos5_usbdrd_phy_drvdata {
 141         const struct exynos5_usbdrd_phy_config *phy_cfg;
 142         u32 pmu_offset_usbdrd0_phy;
 143         u32 pmu_offset_usbdrd1_phy;
 144         bool has_common_clk_gate;
 145 };
 146
 147 /**
 148  * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
 149  * @dev: pointer to device instance of this platform device
 150  * @reg_phy: usb phy controller register memory base
 151  * @clk: phy clock for register access
 152  * @pipeclk: clock for pipe3 phy
 153  * @utmiclk: clock for utmi+ phy
 154  * @itpclk: clock for ITP generation
 155  * @drv_data: pointer to SoC level driver data structure
 156  * @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
 157  *          instances each with its 'phy' and 'phy_cfg'.
 158  * @extrefclk: frequency select settings when using 'separate
 159  *             reference clocks' for SS and HS operations
 160  * @ref_clk: reference clock to PHY block from which PHY's
 161  *           operational clocks are derived
 162  */
 163 struct exynos5_usbdrd_phy {
 164         struct device *dev;
 165         void __iomem *reg_phy;
 166         struct clk *clk;
 167         struct clk *pipeclk;
 168         struct clk *utmiclk;
 169         struct clk *itpclk;
 170         const struct exynos5_usbdrd_phy_drvdata *drv_data;
 171         struct phy_usb_instance {
 172                 struct phy *phy;
 173                 u32 index;
 174                 struct regmap *reg_pmu;
 175                 u32 pmu_offset;
 176                 const struct exynos5_usbdrd_phy_config *phy_cfg;
 177         } phys[EXYNOS5_DRDPHYS_NUM];
 178         u32 extrefclk;
 179         struct clk *ref_clk;
 180         struct regulator *vbus;
 181 };
 182
 183 static inline
 184 struct exynos5_usbdrd_phy *to_usbdrd_phy(struct phy_usb_instance *inst)
 185 {
 186         return container_of((inst), struct exynos5_usbdrd_phy,
 187                             phys[(inst)->index]);
 188 }
 189
 190 /*
 191  * exynos5_rate_to_clk() converts the supplied clock rate to the value that
 192  * can be written to the phy register.
 193  */
 194 static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg)
 195 {
 196         /* EXYNOS5_FSEL_MASK */
 197
 198         switch (rate) {
 199         case 9600 * KHZ:
 200                 *reg = EXYNOS5_FSEL_9MHZ6;
 201                 break;
 202         case 10 * MHZ:
 203                 *reg = EXYNOS5_FSEL_10MHZ;
 204                 break;
 205         case 12 * MHZ:
 206                 *reg = EXYNOS5_FSEL_12MHZ;
 207                 break;
 208         case 19200 * KHZ:
 209                 *reg = EXYNOS5_FSEL_19MHZ2;
 210                 break;
 211         case 20 * MHZ:
 212                 *reg = EXYNOS5_FSEL_20MHZ;
 213                 break;
 214         case 24 * MHZ:
 215                 *reg = EXYNOS5_FSEL_24MHZ;
 216                 break;
 217         case 50 * MHZ:
 218                 *reg = EXYNOS5_FSEL_50MHZ;
 219                 break;
 220         default:
 221                 return -EINVAL;
 222         }
 223
 224         return 0;
 225 }
 226
 227 static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst,
 228                                                 unsigned int on)
 229 {
 230         unsigned int val;
 231
 232         if (!inst->reg_pmu)
 233                 return;
 234
 235         val = on ? 0 : EXYNOS5_PHY_ENABLE;
 236
 237         regmap_update_bits(inst->reg_pmu, inst->pmu_offset,
 238                            EXYNOS5_PHY_ENABLE, val);
 239 }
 240
 241 /*
 242  * Sets the pipe3 phy's clk as EXTREFCLK (XXTI) which is internal clock
 243  * from clock core. Further sets multiplier values and spread spectrum
 244  * clock settings for SuperSpeed operations.
 245  */
 246 static unsigned int
 247 exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
 248 {
 249         static u32 reg;
 250         struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
 251
 252         /* restore any previous reference clock settings */
 253         reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
 254
 255         /* Use EXTREFCLK as ref clock */
 256         reg &= ~PHYCLKRST_REFCLKSEL_MASK;
 257         reg |=  PHYCLKRST_REFCLKSEL_EXT_REFCLK;
 258
 259         /* FSEL settings corresponding to reference clock */
 260         reg &= ~PHYCLKRST_FSEL_PIPE_MASK |
 261                 PHYCLKRST_MPLL_MULTIPLIER_MASK |
 262                 PHYCLKRST_SSC_REFCLKSEL_MASK;
 263         switch (phy_drd->extrefclk) {
 264         case EXYNOS5_FSEL_50MHZ:
 265                 reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
 266                         PHYCLKRST_SSC_REFCLKSEL(0x00));
 267                 break;
 268         case EXYNOS5_FSEL_24MHZ:
 269                 reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
 270                         PHYCLKRST_SSC_REFCLKSEL(0x88));
 271                 break;
 272         case EXYNOS5_FSEL_20MHZ:
 273                 reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
 274                         PHYCLKRST_SSC_REFCLKSEL(0x00));
 275                 break;
 276         case EXYNOS5_FSEL_19MHZ2:
 277                 reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
 278                         PHYCLKRST_SSC_REFCLKSEL(0x88));
 279                 break;
 280         default:
 281                 dev_dbg(phy_drd->dev, "unsupported ref clk\n");
 282                 break;
 283         }
 284
 285         return reg;
 286 }
 287
 288 /*
 289  * Sets the utmi phy's clk as EXTREFCLK (XXTI) which is internal clock
 290  * from clock core. Further sets the FSEL values for HighSpeed operations.
 291  */
 292 static unsigned int
 293 exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
 294 {
 295         static u32 reg;
 296         struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
 297
 298         /* restore any previous reference clock settings */
 299         reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
 300
 301         reg &= ~PHYCLKRST_REFCLKSEL_MASK;
 302         reg |=  PHYCLKRST_REFCLKSEL_EXT_REFCLK;
 303
 304         reg &= ~PHYCLKRST_FSEL_UTMI_MASK |
 305                 PHYCLKRST_MPLL_MULTIPLIER_MASK |
 306                 PHYCLKRST_SSC_REFCLKSEL_MASK;
 307         reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
 308
 309         return reg;
 310 }
 311
 312 static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
 313 {
 314         u32 reg;
 315
 316         reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
 317         /* Set Tx De-Emphasis level */
 318         reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
 319         reg |=  PHYPARAM1_PCS_TXDEEMPH;
 320         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
 321
 322         reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
 323         reg &= ~PHYTEST_POWERDOWN_SSP;
 324         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
 325 }
 326
 327 static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
 328 {
 329         u32 reg;
 330
 331         reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
 332         /* Set Loss-of-Signal Detector sensitivity */
 333         reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
 334         reg |=  PHYPARAM0_REF_LOSLEVEL;
 335         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
 336
 337         reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
 338         /* Set Tx De-Emphasis level */
 339         reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
 340         reg |=  PHYPARAM1_PCS_TXDEEMPH;
 341         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
 342
 343         /* UTMI Power Control */
 344         writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
 345
 346         reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
 347         reg &= ~PHYTEST_POWERDOWN_HSP;
 348         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
 349 }
 350
 351 static int exynos5_usbdrd_phy_init(struct phy *phy)
 352 {
 353         int ret;
 354         u32 reg;
 355         struct phy_usb_instance *inst = phy_get_drvdata(phy);
 356         struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
 357
 358         ret = clk_prepare_enable(phy_drd->clk);
 359         if (ret)
 360                 return ret;
 361
 362         /* Reset USB 3.0 PHY */
 363         writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
 364         writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME);
 365
 366         /*
 367          * Setting the Frame length Adj value[6:1] to default 0x20
 368          * See xHCI 1.0 spec, 5.2.4
 369          */
 370         reg =   LINKSYSTEM_XHCI_VERSION_CONTROL |
 371                 LINKSYSTEM_FLADJ(0x20);
 372         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
 373
 374         reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
 375         /* Select PHY CLK source */
 376         reg &= ~PHYPARAM0_REF_USE_PAD;
 377         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
 378
 379         /* This bit must be set for both HS and SS operations */
 380         reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
 381         reg |= PHYUTMICLKSEL_UTMI_CLKSEL;
 382         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
 383
 384         /* UTMI or PIPE3 specific init */
 385         inst->phy_cfg->phy_init(phy_drd);
 386
 387         /* reference clock settings */
 388         reg = inst->phy_cfg->set_refclk(inst);
 389
 390                 /* Digital power supply in normal operating mode */
 391         reg |=  PHYCLKRST_RETENABLEN |
 392                 /* Enable ref clock for SS function */
 393                 PHYCLKRST_REF_SSP_EN |
 394                 /* Enable spread spectrum */
 395                 PHYCLKRST_SSC_EN |
 396                 /* Power down HS Bias and PLL blocks in suspend mode */
 397                 PHYCLKRST_COMMONONN |
 398                 /* Reset the port */
 399                 PHYCLKRST_PORTRESET;
 400
 401         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
 402
 403         udelay(10);
 404
 405         reg &= ~PHYCLKRST_PORTRESET;
 406         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
 407
 408         clk_disable_unprepare(phy_drd->clk);
 409
 410         return 0;
 411 }
 412
 413 static int exynos5_usbdrd_phy_exit(struct phy *phy)
 414 {
 415         int ret;
 416         u32 reg;
 417         struct phy_usb_instance *inst = phy_get_drvdata(phy);
 418         struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
 419
 420         ret = clk_prepare_enable(phy_drd->clk);
 421         if (ret)
 422                 return ret;
 423
 424         reg =   PHYUTMI_OTGDISABLE |
 425                 PHYUTMI_FORCESUSPEND |
 426                 PHYUTMI_FORCESLEEP;
 427         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
 428
 429         /* Resetting the PHYCLKRST enable bits to reduce leakage current */
 430         reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
 431         reg &= ~(PHYCLKRST_REF_SSP_EN |
 432                  PHYCLKRST_SSC_EN |
 433                  PHYCLKRST_COMMONONN);
 434         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
 435
 436         /* Control PHYTEST to remove leakage current */
 437         reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
 438         reg |=  PHYTEST_POWERDOWN_SSP |
 439                 PHYTEST_POWERDOWN_HSP;
 440         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
 441
 442         clk_disable_unprepare(phy_drd->clk);
 443
 444         return 0;
 445 }
 446
 447 static int exynos5_usbdrd_phy_power_on(struct phy *phy)
 448 {
 449         int ret;
 450         struct phy_usb_instance *inst = phy_get_drvdata(phy);
 451         struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
 452
 453         dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
 454
 455         clk_prepare_enable(phy_drd->ref_clk);
 456         if (!phy_drd->drv_data->has_common_clk_gate) {
 457                 clk_prepare_enable(phy_drd->pipeclk);
 458                 clk_prepare_enable(phy_drd->utmiclk);
 459                 clk_prepare_enable(phy_drd->itpclk);
 460         }
 461
 462         /* Enable VBUS supply */
 463         if (phy_drd->vbus) {
 464                 ret = regulator_enable(phy_drd->vbus);
 465                 if (ret) {
 466                         dev_err(phy_drd->dev, "Failed to enable VBUS supply\n");
 467                         goto fail_vbus;
 468                 }
 469         }
 470
 471         /* Power-on PHY*/
 472         inst->phy_cfg->phy_isol(inst, 0);
 473
 474         return 0;
 475
 476 fail_vbus:
 477         clk_disable_unprepare(phy_drd->ref_clk);
 478         if (!phy_drd->drv_data->has_common_clk_gate) {
 479                 clk_disable_unprepare(phy_drd->itpclk);
 480                 clk_disable_unprepare(phy_drd->utmiclk);
 481                 clk_disable_unprepare(phy_drd->pipeclk);
 482         }
 483
 484         return ret;
 485 }
 486
 487 static int exynos5_usbdrd_phy_power_off(struct phy *phy)
 488 {
 489         struct phy_usb_instance *inst = phy_get_drvdata(phy);
 490         struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
 491
 492         dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n");
 493
 494         /* Power-off the PHY */
 495         inst->phy_cfg->phy_isol(inst, 1);
 496
 497         /* Disable VBUS supply */
 498         if (phy_drd->vbus)
 499                 regulator_disable(phy_drd->vbus);
 500
 501         clk_disable_unprepare(phy_drd->ref_clk);
 502         if (!phy_drd->drv_data->has_common_clk_gate) {
 503                 clk_disable_unprepare(phy_drd->itpclk);
 504                 clk_disable_unprepare(phy_drd->pipeclk);
 505                 clk_disable_unprepare(phy_drd->utmiclk);
 506         }
 507
 508         return 0;
 509 }
 510
 511 static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
 512                                         struct of_phandle_args *args)
 513 {
 514         struct exynos5_usbdrd_phy *phy_drd = dev_get_drvdata(dev);
 515
 516         if (WARN_ON(args->args[0] > EXYNOS5_DRDPHYS_NUM))
 517                 return ERR_PTR(-ENODEV);
 518
 519         return phy_drd->phys[args->args[0]].phy;
 520 }
 521
 522 static struct phy_ops exynos5_usbdrd_phy_ops = {
 523         .init           = exynos5_usbdrd_phy_init,
 524         .exit           = exynos5_usbdrd_phy_exit,
 525         .power_on       = exynos5_usbdrd_phy_power_on,
 526         .power_off      = exynos5_usbdrd_phy_power_off,
 527         .owner          = THIS_MODULE,
 528 };
 529
 530 static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
 531 {
 532         unsigned long ref_rate;
 533         int ret;
 534
 535         phy_drd->clk = devm_clk_get(phy_drd->dev, "phy");
 536         if (IS_ERR(phy_drd->clk)) {
 537                 dev_err(phy_drd->dev, "Failed to get phy clock\n");
 538                 return PTR_ERR(phy_drd->clk);
 539         }
 540
 541         phy_drd->ref_clk = devm_clk_get(phy_drd->dev, "ref");
 542         if (IS_ERR(phy_drd->ref_clk)) {
 543                 dev_err(phy_drd->dev, "Failed to get phy reference clock\n");
 544                 return PTR_ERR(phy_drd->ref_clk);
 545         }
 546         ref_rate = clk_get_rate(phy_drd->ref_clk);
 547
 548         ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
 549         if (ret) {
 550                 dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
 551                         ref_rate);
 552                 return ret;
 553         }
 554
 555         if (!phy_drd->drv_data->has_common_clk_gate) {
 556                 phy_drd->pipeclk = devm_clk_get(phy_drd->dev, "phy_pipe");
 557                 if (IS_ERR(phy_drd->pipeclk)) {
 558                         dev_info(phy_drd->dev,
 559                                  "PIPE3 phy operational clock not specified\n");
 560                         phy_drd->pipeclk = NULL;
 561                 }
 562
 563                 phy_drd->utmiclk = devm_clk_get(phy_drd->dev, "phy_utmi");
 564                 if (IS_ERR(phy_drd->utmiclk)) {
 565                         dev_info(phy_drd->dev,
 566                                  "UTMI phy operational clock not specified\n");
 567                         phy_drd->utmiclk = NULL;
 568                 }
 569
 570                 phy_drd->itpclk = devm_clk_get(phy_drd->dev, "itp");
 571                 if (IS_ERR(phy_drd->itpclk)) {
 572                         dev_info(phy_drd->dev,
 573                                  "ITP clock from main OSC not specified\n");
 574                         phy_drd->itpclk = NULL;
 575                 }
 576         }
 577
 578         return 0;
 579 }
 580
 581 static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = {
 582         {
 583                 .id             = EXYNOS5_DRDPHY_UTMI,
 584                 .phy_isol       = exynos5_usbdrd_phy_isol,
 585                 .phy_init       = exynos5_usbdrd_utmi_init,
 586                 .set_refclk     = exynos5_usbdrd_utmi_set_refclk,
 587         },
 588         {
 589                 .id             = EXYNOS5_DRDPHY_PIPE3,
 590                 .phy_isol       = exynos5_usbdrd_phy_isol,
 591                 .phy_init       = exynos5_usbdrd_pipe3_init,
 592                 .set_refclk     = exynos5_usbdrd_pipe3_set_refclk,
 593         },
 594 };
 595
 596 static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
 597         .phy_cfg                = phy_cfg_exynos5,
 598         .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
 599         .pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL,
 600         .has_common_clk_gate    = true,
 601 };
 602
 603 static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
 604         .phy_cfg                = phy_cfg_exynos5,
 605         .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
 606         .has_common_clk_gate    = true,
 607 };
 608
 609 static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = {
 610         .phy_cfg                = phy_cfg_exynos5,
 611         .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
 612         .has_common_clk_gate    = false,
 613 };
 614
 615 static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
 616         {
 617                 .compatible = "samsung,exynos5250-usbdrd-phy",
 618                 .data = &exynos5250_usbdrd_phy
 619         }, {
 620                 .compatible = "samsung,exynos5420-usbdrd-phy",
 621                 .data = &exynos5420_usbdrd_phy
 622         }, {
 623                 .compatible = "samsung,exynos7-usbdrd-phy",
 624                 .data = &exynos7_usbdrd_phy
 625         },
 626         { },
 627 };
 628 MODULE_DEVICE_TABLE(of, exynos5_usbdrd_phy_of_match);
 629
 630 static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
 631 {
 632         struct device *dev = &pdev->dev;
 633         struct device_node *node = dev->of_node;
 634         struct exynos5_usbdrd_phy *phy_drd;
 635         struct phy_provider *phy_provider;
 636         struct resource *res;
 637         const struct of_device_id *match;
 638         const struct exynos5_usbdrd_phy_drvdata *drv_data;
 639         struct regmap *reg_pmu;
 640         u32 pmu_offset;
 641         int i, ret;
 642         int channel;
 643
 644         phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL);
 645         if (!phy_drd)
 646                 return -ENOMEM;
 647
 648         dev_set_drvdata(dev, phy_drd);
 649         phy_drd->dev = dev;
 650
 651         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 652         phy_drd->reg_phy = devm_ioremap_resource(dev, res);
 653         if (IS_ERR(phy_drd->reg_phy))
 654                 return PTR_ERR(phy_drd->reg_phy);
 655
 656         match = of_match_node(exynos5_usbdrd_phy_of_match, pdev->dev.of_node);
 657
 658         drv_data = match->data;
 659         phy_drd->drv_data = drv_data;
 660
 661         ret = exynos5_usbdrd_phy_clk_handle(phy_drd);
 662         if (ret) {
 663                 dev_err(dev, "Failed to initialize clocks\n");
 664                 return ret;
 665         }
 666
 667         reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
 668                                                    "samsung,pmu-syscon");
 669         if (IS_ERR(reg_pmu)) {
 670                 dev_err(dev, "Failed to lookup PMU regmap\n");
 671                 return PTR_ERR(reg_pmu);
 672         }
 673
 674         /*
 675          * Exynos5420 SoC has multiple channels for USB 3.0 PHY, with
 676          * each having separate power control registers.
 677          * 'channel' facilitates to set such registers.
 678          */
 679         channel = of_alias_get_id(node, "usbdrdphy");
 680         if (channel < 0)
 681                 dev_dbg(dev, "Not a multi-controller usbdrd phy\n");
 682
 683         switch (channel) {
 684         case 1:
 685                 pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd1_phy;
 686                 break;
 687         case 0:
 688         default:
 689                 pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd0_phy;
 690                 break;
 691         }
 692
 693         /* Get Vbus regulator */
 694         phy_drd->vbus = devm_regulator_get(dev, "vbus");
 695         if (IS_ERR(phy_drd->vbus)) {
 696                 ret = PTR_ERR(phy_drd->vbus);
 697                 if (ret == -EPROBE_DEFER)
 698                         return ret;
 699
 700                 dev_warn(dev, "Failed to get VBUS supply regulator\n");
 701                 phy_drd->vbus = NULL;
 702         }
 703
 704         dev_vdbg(dev, "Creating usbdrd_phy phy\n");
 705
 706         for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {
 707                 struct phy *phy = devm_phy_create(dev, NULL,
 708                                                   &exynos5_usbdrd_phy_ops);
 709                 if (IS_ERR(phy)) {
 710                         dev_err(dev, "Failed to create usbdrd_phy phy\n");
 711                         return PTR_ERR(phy);
 712                 }
 713
 714                 phy_drd->phys[i].phy = phy;
 715                 phy_drd->phys[i].index = i;
 716                 phy_drd->phys[i].reg_pmu = reg_pmu;
 717                 phy_drd->phys[i].pmu_offset = pmu_offset;
 718                 phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i];
 719                 phy_set_drvdata(phy, &phy_drd->phys[i]);
 720         }
 721
 722         phy_provider = devm_of_phy_provider_register(dev,
 723                                                      exynos5_usbdrd_phy_xlate);
 724         if (IS_ERR(phy_provider)) {
 725                 dev_err(phy_drd->dev, "Failed to register phy provider\n");
 726                 return PTR_ERR(phy_provider);
 727         }
 728
 729         return 0;
 730 }
 731
 732 static struct platform_driver exynos5_usb3drd_phy = {
 733         .probe  = exynos5_usbdrd_phy_probe,
 734         .driver = {
 735                 .of_match_table = exynos5_usbdrd_phy_of_match,
 736                 .name           = "exynos5_usb3drd_phy",
 737         }
 738 };
 739
 740 module_platform_driver(exynos5_usb3drd_phy);
 741 MODULE_DESCRIPTION("Samsung EXYNOS5 SoCs USB 3.0 DRD controller PHY driver");
 742 MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>");
 743 MODULE_LICENSE("GPL v2");
 744 MODULE_ALIAS("platform:exynos5_usb3drd_phy");