2 * Copyright (C) 2014 STMicroelectronics
4 * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407).
6 * Author: Alexandre Torgue <alexandre.torgue@st.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2, as
10 * published by the Free Software Foundation.
14 #include <linux/platform_device.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_address.h>
21 #include <linux/clk.h>
22 #include <linux/phy/phy.h>
23 #include <linux/delay.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/regmap.h>
26 #include <linux/reset.h>
28 #include <dt-bindings/phy/phy.h>
31 #define MIPHY_CONF_RESET 0x00
32 #define RST_APPLI_SW BIT(0)
33 #define RST_CONF_SW BIT(1)
34 #define RST_MACRO_SW BIT(2)
36 #define MIPHY_RESET 0x01
37 #define RST_PLL_SW BIT(0)
38 #define RST_COMP_SW BIT(2)
40 #define MIPHY_STATUS_1 0x02
41 #define PHY_RDY BIT(0)
42 #define HFC_RDY BIT(1)
43 #define HFC_PLL BIT(2)
45 #define MIPHY_CONTROL 0x04
46 #define TERM_EN_SW BIT(2)
47 #define DIS_LINK_RST BIT(3)
48 #define AUTO_RST_RX BIT(4)
49 #define PX_RX_POL BIT(5)
51 #define MIPHY_BOUNDARY_SEL 0x0a
53 #define SSC_SEL BIT(4)
54 #define GENSEL_SEL BIT(0)
56 #define MIPHY_BOUNDARY_1 0x0b
57 #define MIPHY_BOUNDARY_2 0x0c
58 #define SSC_EN_SW BIT(2)
60 #define MIPHY_PLL_CLKREF_FREQ 0x0d
61 #define MIPHY_SPEED 0x0e
62 #define TX_SPDSEL_80DEC 0
63 #define TX_SPDSEL_40DEC 1
64 #define TX_SPDSEL_20DEC 2
65 #define RX_SPDSEL_80DEC 0
66 #define RX_SPDSEL_40DEC (1 << 2)
67 #define RX_SPDSEL_20DEC (2 << 2)
69 #define MIPHY_CONF 0x0f
70 #define MIPHY_CTRL_TEST_SEL 0x20
71 #define MIPHY_CTRL_TEST_1 0x21
72 #define MIPHY_CTRL_TEST_2 0x22
73 #define MIPHY_CTRL_TEST_3 0x23
74 #define MIPHY_CTRL_TEST_4 0x24
75 #define MIPHY_FEEDBACK_TEST 0x25
76 #define MIPHY_DEBUG_BUS 0x26
77 #define MIPHY_DEBUG_STATUS_MSB 0x27
78 #define MIPHY_DEBUG_STATUS_LSB 0x28
79 #define MIPHY_PWR_RAIL_1 0x29
80 #define MIPHY_PWR_RAIL_2 0x2a
81 #define MIPHY_SYNCHAR_CONTROL 0x30
83 #define MIPHY_COMP_FSM_1 0x3a
84 #define COMP_START BIT(6)
86 #define MIPHY_COMP_FSM_6 0x3f
87 #define COMP_DONE BIT(7)
89 #define MIPHY_COMP_POSTP 0x42
90 #define MIPHY_TX_CTRL_1 0x49
91 #define TX_REG_STEP_0V 0
92 #define TX_REG_STEP_P_25MV 1
93 #define TX_REG_STEP_P_50MV 2
94 #define TX_REG_STEP_N_25MV 7
95 #define TX_REG_STEP_N_50MV 6
96 #define TX_REG_STEP_N_75MV 5
98 #define MIPHY_TX_CTRL_2 0x4a
99 #define TX_SLEW_SW_40_PS 0
100 #define TX_SLEW_SW_80_PS 1
101 #define TX_SLEW_SW_120_PS 2
103 #define MIPHY_TX_CTRL_3 0x4b
104 #define MIPHY_TX_CAL_MAN 0x4e
105 #define TX_SLEW_CAL_MAN_EN BIT(0)
107 #define MIPHY_TST_BIAS_BOOST_2 0x62
108 #define MIPHY_BIAS_BOOST_1 0x63
109 #define MIPHY_BIAS_BOOST_2 0x64
110 #define MIPHY_RX_DESBUFF_FDB_2 0x67
111 #define MIPHY_RX_DESBUFF_FDB_3 0x68
112 #define MIPHY_SIGDET_COMPENS1 0x69
113 #define MIPHY_SIGDET_COMPENS2 0x6a
114 #define MIPHY_JITTER_PERIOD 0x6b
115 #define MIPHY_JITTER_AMPLITUDE_1 0x6c
116 #define MIPHY_JITTER_AMPLITUDE_2 0x6d
117 #define MIPHY_JITTER_AMPLITUDE_3 0x6e
118 #define MIPHY_RX_K_GAIN 0x78
119 #define MIPHY_RX_BUFFER_CTRL 0x7a
120 #define VGA_GAIN BIT(0)
121 #define EQ_DC_GAIN BIT(2)
122 #define EQ_BOOST_GAIN BIT(3)
124 #define MIPHY_RX_VGA_GAIN 0x7b
125 #define MIPHY_RX_EQU_GAIN_1 0x7f
126 #define MIPHY_RX_EQU_GAIN_2 0x80
127 #define MIPHY_RX_EQU_GAIN_3 0x81
128 #define MIPHY_RX_CAL_CTRL_1 0x97
129 #define MIPHY_RX_CAL_CTRL_2 0x98
131 #define MIPHY_RX_CAL_OFFSET_CTRL 0x99
132 #define CAL_OFFSET_VGA_64 (0x03 << 0)
133 #define CAL_OFFSET_THRESHOLD_64 (0x03 << 2)
134 #define VGA_OFFSET_POLARITY BIT(4)
135 #define OFFSET_COMPENSATION_EN BIT(6)
137 #define MIPHY_RX_CAL_VGA_STEP 0x9a
138 #define MIPHY_RX_CAL_EYE_MIN 0x9d
139 #define MIPHY_RX_CAL_OPT_LENGTH 0x9f
140 #define MIPHY_RX_LOCK_CTRL_1 0xc1
141 #define MIPHY_RX_LOCK_SETTINGS_OPT 0xc2
142 #define MIPHY_RX_LOCK_STEP 0xc4
144 #define MIPHY_RX_SIGDET_SLEEP_OA 0xc9
145 #define MIPHY_RX_SIGDET_SLEEP_SEL 0xca
146 #define MIPHY_RX_SIGDET_WAIT_SEL 0xcb
147 #define MIPHY_RX_SIGDET_DATA_SEL 0xcc
148 #define EN_ULTRA_LOW_POWER BIT(0)
149 #define EN_FIRST_HALF BIT(1)
150 #define EN_SECOND_HALF BIT(2)
151 #define EN_DIGIT_SIGNAL_CHECK BIT(3)
153 #define MIPHY_RX_POWER_CTRL_1 0xcd
154 #define MIPHY_RX_POWER_CTRL_2 0xce
155 #define MIPHY_PLL_CALSET_CTRL 0xd3
156 #define MIPHY_PLL_CALSET_1 0xd4
157 #define MIPHY_PLL_CALSET_2 0xd5
158 #define MIPHY_PLL_CALSET_3 0xd6
159 #define MIPHY_PLL_CALSET_4 0xd7
160 #define MIPHY_PLL_SBR_1 0xe3
161 #define SET_NEW_CHANGE BIT(1)
163 #define MIPHY_PLL_SBR_2 0xe4
164 #define MIPHY_PLL_SBR_3 0xe5
165 #define MIPHY_PLL_SBR_4 0xe6
166 #define MIPHY_PLL_COMMON_MISC_2 0xe9
167 #define START_ACT_FILT BIT(6)
169 #define MIPHY_PLL_SPAREIN 0xeb
172 * On STiH407 the glue logic can be different among MiPHY devices; for example:
173 * MiPHY0: OSC_FORCE_EXT means:
174 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
175 * MiPHY1: OSC_FORCE_EXT means:
176 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
177 * Some devices have not the possibility to check if the osc is ready.
179 #define MIPHY_OSC_FORCE_EXT BIT(3)
180 #define MIPHY_OSC_RDY BIT(5)
182 #define MIPHY_CTRL_MASK 0x0f
183 #define MIPHY_CTRL_DEFAULT 0
184 #define MIPHY_CTRL_SYNC_D_EN BIT(2)
186 /* SATA / PCIe defines */
187 #define SATA_CTRL_MASK 0x07
188 #define PCIE_CTRL_MASK 0xff
189 #define SATA_CTRL_SELECT_SATA 1
190 #define SATA_CTRL_SELECT_PCIE 0
191 #define SYSCFG_PCIE_PCIE_VAL 0x80
192 #define SATA_SPDMODE 1
194 #define MIPHY_SATA_BANK_NB 3
195 #define MIPHY_PCIE_BANK_NB 2
197 struct miphy28lp_phy {
199 struct miphy28lp_dev *phydev;
201 void __iomem *pipebase;
209 struct reset_control *miphy_rst;
213 /* Sysconfig registers offsets needed to configure the device */
214 u32 syscfg_miphy_ctrl;
215 u32 syscfg_miphy_status;
221 struct miphy28lp_dev {
223 struct regmap *regmap;
224 struct mutex miphy_mutex;
225 struct miphy28lp_phy **phys;
228 struct miphy_initval {
233 enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 };
235 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
246 static struct pll_ratio sata_pll_ratio = {
255 static struct pll_ratio pcie_pll_ratio = {
264 static struct pll_ratio usb3_pll_ratio = {
273 struct miphy28lp_pll_gen {
289 static struct miphy28lp_pll_gen sata_pll_gen[] = {
292 .speed = TX_SPDSEL_80DEC | RX_SPDSEL_80DEC,
293 .bias_boost_1 = 0x00,
294 .bias_boost_2 = 0xae,
297 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
299 .rx_equ_gain_1 = 0x7d,
300 .rx_equ_gain_2 = 0x56,
301 .rx_equ_gain_3 = 0x00,
305 .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC,
306 .bias_boost_1 = 0x00,
307 .bias_boost_2 = 0xae,
310 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
312 .rx_equ_gain_1 = 0x7d,
313 .rx_equ_gain_2 = 0x56,
314 .rx_equ_gain_3 = 0x00,
318 .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC,
319 .bias_boost_1 = 0x00,
320 .bias_boost_2 = 0xae,
323 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
325 .rx_equ_gain_1 = 0x7d,
326 .rx_equ_gain_2 = 0x56,
327 .rx_equ_gain_3 = 0x00,
331 static struct miphy28lp_pll_gen pcie_pll_gen[] = {
334 .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC,
335 .bias_boost_1 = 0x00,
336 .bias_boost_2 = 0xa5,
337 .tx_ctrl_1 = TX_REG_STEP_N_25MV,
341 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
343 .rx_equ_gain_1 = 0x79,
344 .rx_equ_gain_2 = 0x56,
348 .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC,
349 .bias_boost_1 = 0x00,
350 .bias_boost_2 = 0xa5,
351 .tx_ctrl_1 = TX_REG_STEP_N_25MV,
355 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
357 .rx_equ_gain_1 = 0x78,
358 .rx_equ_gain_2 = 0x07,
362 static inline void miphy28lp_set_reset(struct miphy28lp_phy *miphy_phy)
364 void *base = miphy_phy->base;
367 /* Putting Macro in reset */
368 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
370 val = RST_APPLI_SW | RST_CONF_SW;
371 writeb_relaxed(val, base + MIPHY_CONF_RESET);
373 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
375 /* Bringing the MIPHY-CPU registers out of reset */
376 if (miphy_phy->type == PHY_TYPE_PCIE) {
377 val = AUTO_RST_RX | TERM_EN_SW;
378 writeb_relaxed(val, base + MIPHY_CONTROL);
380 val = AUTO_RST_RX | TERM_EN_SW | DIS_LINK_RST;
381 writeb_relaxed(val, base + MIPHY_CONTROL);
385 static inline void miphy28lp_pll_calibration(struct miphy28lp_phy *miphy_phy,
386 struct pll_ratio *pll_ratio)
388 void *base = miphy_phy->base;
391 /* Applying PLL Settings */
392 writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
393 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
396 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1);
397 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2);
398 writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3);
399 writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4);
400 writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL);
402 writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL);
404 val = (0x68 << 1) | TX_SLEW_CAL_MAN_EN;
405 writeb_relaxed(val, base + MIPHY_TX_CAL_MAN);
407 val = VGA_OFFSET_POLARITY | CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64;
409 if (miphy_phy->type != PHY_TYPE_SATA)
410 val |= OFFSET_COMPENSATION_EN;
412 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
414 if (miphy_phy->type == PHY_TYPE_USB3) {
415 writeb_relaxed(0x00, base + MIPHY_CONF);
416 writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP);
417 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA);
418 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL);
419 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL);
421 val = EN_DIGIT_SIGNAL_CHECK | EN_FIRST_HALF;
422 writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL);
427 static inline void miphy28lp_sata_config_gen(struct miphy28lp_phy *miphy_phy)
429 void __iomem *base = miphy_phy->base;
432 for (i = 0; i < ARRAY_SIZE(sata_pll_gen); i++) {
433 struct miphy28lp_pll_gen *gen = &sata_pll_gen[i];
435 /* Banked settings */
436 writeb_relaxed(gen->bank, base + MIPHY_CONF);
437 writeb_relaxed(gen->speed, base + MIPHY_SPEED);
438 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
439 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
441 /* TX buffer Settings */
442 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
443 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
445 /* RX Buffer Settings */
446 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
447 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
448 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
449 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
450 writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3);
454 static inline void miphy28lp_pcie_config_gen(struct miphy28lp_phy *miphy_phy)
456 void __iomem *base = miphy_phy->base;
459 for (i = 0; i < ARRAY_SIZE(pcie_pll_gen); i++) {
460 struct miphy28lp_pll_gen *gen = &pcie_pll_gen[i];
462 /* Banked settings */
463 writeb_relaxed(gen->bank, base + MIPHY_CONF);
464 writeb_relaxed(gen->speed, base + MIPHY_SPEED);
465 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
466 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
468 /* TX buffer Settings */
469 writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1);
470 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
471 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
473 writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN);
475 /* RX Buffer Settings */
476 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
477 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
478 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
479 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
483 static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy)
485 unsigned long finish = jiffies + 5 * HZ;
488 /* Waiting for Compensation to complete */
490 val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6);
492 if (time_after_eq(jiffies, finish))
495 } while (!(val & COMP_DONE));
501 static inline int miphy28lp_compensation(struct miphy28lp_phy *miphy_phy,
502 struct pll_ratio *pll_ratio)
504 void __iomem *base = miphy_phy->base;
506 /* Poll for HFC ready after reset release */
507 /* Compensation measurement */
508 writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET);
510 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
511 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
512 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
514 if (miphy_phy->type == PHY_TYPE_PCIE)
515 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
517 writeb_relaxed(0x00, base + MIPHY_RESET);
518 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
519 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
521 /* TX compensation offset to re-center TX impedance */
522 writeb_relaxed(0x00, base + MIPHY_COMP_POSTP);
524 if (miphy_phy->type == PHY_TYPE_PCIE)
525 return miphy28lp_wait_compensation(miphy_phy);
530 static inline void miphy28_usb3_miphy_reset(struct miphy28lp_phy *miphy_phy)
532 void __iomem *base = miphy_phy->base;
536 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
537 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
538 writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET);
540 val = RST_COMP_SW | RST_PLL_SW;
541 writeb_relaxed(val, base + MIPHY_RESET);
543 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
544 writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
545 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
546 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
547 writeb_relaxed(0x00, base + MIPHY_RESET);
548 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
549 writeb_relaxed(0x00, base + MIPHY_CONF);
550 writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1);
551 writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2);
552 writeb_relaxed(0x00, base + MIPHY_CONF);
553 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
554 writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS);
555 writeb_relaxed(0x00, base + MIPHY_CONF);
558 static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy)
560 void __iomem *base = miphy_phy->base;
563 /* Compensate Tx impedance to avoid out of range values */
565 * Enable the SSC on PLL for all banks
566 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
568 val = readb_relaxed(base + MIPHY_BOUNDARY_2);
570 writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
572 val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
574 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
576 for (val = 0; val < MIPHY_SATA_BANK_NB; val++) {
577 writeb_relaxed(val, base + MIPHY_CONF);
579 /* Add value to each reference clock cycle */
580 /* and define the period length of the SSC */
581 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
582 writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3);
583 writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4);
585 /* Clear any previous request */
586 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
588 /* requests the PLL to take in account new parameters */
589 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
591 /* To be sure there is no other pending requests */
592 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
596 static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
598 void __iomem *base = miphy_phy->base;
601 /* Compensate Tx impedance to avoid out of range values */
603 * Enable the SSC on PLL for all banks
604 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
606 val = readb_relaxed(base + MIPHY_BOUNDARY_2);
608 writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
610 val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
612 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
614 for (val = 0; val < MIPHY_PCIE_BANK_NB; val++) {
615 writeb_relaxed(val, base + MIPHY_CONF);
617 /* Validate Step component */
618 writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3);
619 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
621 /* Validate Period component */
622 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
623 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
625 /* Clear any previous request */
626 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
628 /* requests the PLL to take in account new parameters */
629 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
631 /* To be sure there is no other pending requests */
632 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
636 static inline void miphy_tune_tx_impedance(struct miphy28lp_phy *miphy_phy)
638 /* Compensate Tx impedance to avoid out of range values */
639 writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);
642 static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
644 void __iomem *base = miphy_phy->base;
648 /* Putting Macro in reset */
649 miphy28lp_set_reset(miphy_phy);
651 /* PLL calibration */
652 miphy28lp_pll_calibration(miphy_phy, &sata_pll_ratio);
654 /* Banked settings Gen1/Gen2/Gen3 */
655 miphy28lp_sata_config_gen(miphy_phy);
658 /* Input bridge enable, manual input bridge control */
659 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
661 /* Macro out of reset */
662 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
664 /* Poll for HFC ready after reset release */
665 /* Compensation measurement */
666 err = miphy28lp_compensation(miphy_phy, &sata_pll_ratio);
670 if (miphy_phy->px_rx_pol_inv) {
671 /* Invert Rx polarity */
672 val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL);
674 writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);
678 miphy_sata_tune_ssc(miphy_phy);
680 if (miphy_phy->tx_impedance)
681 miphy_tune_tx_impedance(miphy_phy);
686 static inline int miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
688 void __iomem *base = miphy_phy->base;
691 /* Putting Macro in reset */
692 miphy28lp_set_reset(miphy_phy);
694 /* PLL calibration */
695 miphy28lp_pll_calibration(miphy_phy, &pcie_pll_ratio);
697 /* Banked settings Gen1/Gen2 */
698 miphy28lp_pcie_config_gen(miphy_phy);
701 /* Input bridge enable, manual input bridge control */
702 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
704 /* Macro out of reset */
705 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
707 /* Poll for HFC ready after reset release */
708 /* Compensation measurement */
709 err = miphy28lp_compensation(miphy_phy, &pcie_pll_ratio);
714 miphy_pcie_tune_ssc(miphy_phy);
716 if (miphy_phy->tx_impedance)
717 miphy_tune_tx_impedance(miphy_phy);
723 static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy)
725 void __iomem *base = miphy_phy->base;
728 /* Putting Macro in reset */
729 miphy28lp_set_reset(miphy_phy);
731 /* PLL calibration */
732 miphy28lp_pll_calibration(miphy_phy, &usb3_pll_ratio);
734 /* Writing The Speed Rate */
735 writeb_relaxed(0x00, base + MIPHY_CONF);
737 val = RX_SPDSEL_20DEC | TX_SPDSEL_20DEC;
738 writeb_relaxed(val, base + MIPHY_SPEED);
740 /* RX Channel compensation and calibration */
741 writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT);
742 writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1);
743 writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2);
745 val = OFFSET_COMPENSATION_EN | VGA_OFFSET_POLARITY |
746 CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64;
747 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
748 writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP);
749 writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH);
751 val = EQ_DC_GAIN | VGA_GAIN;
752 writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL);
753 writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1);
754 writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL);
756 /* TX compensation offset to re-center TX impedance */
757 writeb_relaxed(0x02, base + MIPHY_COMP_POSTP);
759 /* Enable GENSEL_SEL and SSC */
760 /* TX_SEL=0 swing preemp forced by pipe registres */
761 val = SSC_SEL | GENSEL_SEL;
762 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
764 /* MIPHY Bias boost */
765 writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
766 writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2);
769 writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2);
771 /* MIPHY TX control */
772 writeb_relaxed(0x00, base + MIPHY_CONF);
774 /* Validate Step component */
775 writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3);
776 writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4);
778 /* Validate Period component */
779 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
780 writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4);
782 /* Clear any previous request */
783 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
785 /* requests the PLL to take in account new parameters */
786 writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
788 /* To be sure there is no other pending requests */
789 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
791 /* Rx PI controller settings */
792 writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN);
794 /* MIPHY RX input bridge control */
795 /* INPUT_BRIDGE_EN_SW=1, manual input bridge control[0]=1 */
796 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
797 writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1);
798 writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2);
800 /* MIPHY Reset for usb3 */
801 miphy28_usb3_miphy_reset(miphy_phy);
804 static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy)
806 unsigned long finish = jiffies + 5 * HZ;
807 u8 mask = HFC_PLL | HFC_RDY;
811 * For PCIe and USB3 check only that PLL and HFC are ready
812 * For SATA check also that phy is ready!
814 if (miphy_phy->type == PHY_TYPE_SATA)
818 val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1);
819 if ((val & mask) != mask)
823 } while (!time_after_eq(jiffies, finish));
828 static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy)
830 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
831 unsigned long finish = jiffies + 5 * HZ;
834 if (!miphy_phy->osc_rdy)
837 if (!miphy_phy->syscfg_miphy_status)
841 regmap_read(miphy_dev->regmap, miphy_phy->syscfg_miphy_status,
844 if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY)
848 } while (!time_after_eq(jiffies, finish));
853 static int miphy28lp_get_resource_byname(struct device_node *child,
854 char *rname, struct resource *res)
858 index = of_property_match_string(child, "reg-names", rname);
862 return of_address_to_resource(child, index, res);
865 static int miphy28lp_get_one_addr(struct device *dev,
866 struct device_node *child, char *rname,
872 ret = miphy28lp_get_resource_byname(child, rname, &res);
874 *base = devm_ioremap(dev, res.start, resource_size(&res));
876 dev_err(dev, "failed to ioremap %s address region\n"
885 /* MiPHY reset and sysconf setup */
886 static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val)
889 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
891 if (!miphy_phy->syscfg_miphy_ctrl)
894 err = reset_control_assert(miphy_phy->miphy_rst);
896 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
900 if (miphy_phy->osc_force_ext)
901 miphy_val |= MIPHY_OSC_FORCE_EXT;
903 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_miphy_ctrl,
904 MIPHY_CTRL_MASK, miphy_val);
906 err = reset_control_deassert(miphy_phy->miphy_rst);
908 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
912 return miphy_osc_is_ready(miphy_phy);
915 static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
917 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
918 int err, sata_conf = SATA_CTRL_SELECT_SATA;
920 if ((!miphy_phy->syscfg_sata) || (!miphy_phy->syscfg_pci)
921 || (!miphy_phy->base))
924 dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base);
926 /* Configure the glue-logic */
927 sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE);
929 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_sata,
930 SATA_CTRL_MASK, sata_conf);
932 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_pci,
933 PCIE_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
935 /* MiPHY path and clocking init */
936 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
939 dev_err(miphy_dev->dev, "SATA phy setup failed\n");
943 /* initialize miphy */
944 miphy28lp_configure_sata(miphy_phy);
946 return miphy_is_ready(miphy_phy);
949 static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy)
951 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
954 if ((!miphy_phy->syscfg_sata) || (!miphy_phy->syscfg_pci)
955 || (!miphy_phy->base) || (!miphy_phy->pipebase))
958 dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base);
960 /* Configure the glue-logic */
961 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_sata,
962 SATA_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
964 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_pci,
965 PCIE_CTRL_MASK, SYSCFG_PCIE_PCIE_VAL);
967 /* MiPHY path and clocking init */
968 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
971 dev_err(miphy_dev->dev, "PCIe phy setup failed\n");
975 /* initialize miphy */
976 err = miphy28lp_configure_pcie(miphy_phy);
980 /* PIPE Wrapper Configuration */
981 writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */
982 writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */
983 writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */
984 writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */
985 writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */
986 writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */
988 /* Wait for phy_ready */
989 return miphy_is_ready(miphy_phy);
992 static int miphy28lp_init_usb3(struct miphy28lp_phy *miphy_phy)
994 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
997 if ((!miphy_phy->base) || (!miphy_phy->pipebase))
1000 dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base);
1002 /* MiPHY path and clocking init */
1003 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_SYNC_D_EN);
1005 dev_err(miphy_dev->dev, "USB3 phy setup failed\n");
1009 /* initialize miphy */
1010 miphy28lp_configure_usb3(miphy_phy);
1012 /* PIPE Wrapper Configuration */
1013 writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);
1014 writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);
1015 writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);
1016 writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);
1017 writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);
1018 writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);
1020 /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */
1021 writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);
1022 writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);
1023 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);
1024 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);
1025 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);
1026 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);
1027 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);
1028 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);
1030 return miphy_is_ready(miphy_phy);
1033 static int miphy28lp_init(struct phy *phy)
1035 struct miphy28lp_phy *miphy_phy = phy_get_drvdata(phy);
1036 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1039 mutex_lock(&miphy_dev->miphy_mutex);
1041 switch (miphy_phy->type) {
1044 ret = miphy28lp_init_sata(miphy_phy);
1047 ret = miphy28lp_init_pcie(miphy_phy);
1050 ret = miphy28lp_init_usb3(miphy_phy);
1056 mutex_unlock(&miphy_dev->miphy_mutex);
1061 static int miphy28lp_get_addr(struct miphy28lp_phy *miphy_phy)
1063 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1064 struct device_node *phynode = miphy_phy->phy->dev.of_node;
1067 if ((miphy_phy->type != PHY_TYPE_SATA) &&
1068 (miphy_phy->type != PHY_TYPE_PCIE) &&
1069 (miphy_phy->type != PHY_TYPE_USB3)) {
1073 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode,
1074 PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA],
1079 if ((miphy_phy->type == PHY_TYPE_PCIE) ||
1080 (miphy_phy->type == PHY_TYPE_USB3)) {
1081 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew",
1082 &miphy_phy->pipebase);
1090 static struct phy *miphy28lp_xlate(struct device *dev,
1091 struct of_phandle_args *args)
1093 struct miphy28lp_dev *miphy_dev = dev_get_drvdata(dev);
1094 struct miphy28lp_phy *miphy_phy = NULL;
1095 struct device_node *phynode = args->np;
1098 if (!of_device_is_available(phynode)) {
1099 dev_warn(dev, "Requested PHY is disabled\n");
1100 return ERR_PTR(-ENODEV);
1103 if (args->args_count != 1) {
1104 dev_err(dev, "Invalid number of cells in 'phy' property\n");
1105 return ERR_PTR(-EINVAL);
1108 for (index = 0; index < of_get_child_count(dev->of_node); index++)
1109 if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {
1110 miphy_phy = miphy_dev->phys[index];
1115 dev_err(dev, "Failed to find appropriate phy\n");
1116 return ERR_PTR(-EINVAL);
1119 miphy_phy->type = args->args[0];
1121 ret = miphy28lp_get_addr(miphy_phy);
1123 return ERR_PTR(ret);
1125 return miphy_phy->phy;
1128 static struct phy_ops miphy28lp_ops = {
1129 .init = miphy28lp_init,
1132 static int miphy28lp_probe_resets(struct device_node *node,
1133 struct miphy28lp_phy *miphy_phy)
1135 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1138 miphy_phy->miphy_rst = of_reset_control_get(node, "miphy-sw-rst");
1140 if (IS_ERR(miphy_phy->miphy_rst)) {
1141 dev_err(miphy_dev->dev,
1142 "miphy soft reset control not defined\n");
1143 return PTR_ERR(miphy_phy->miphy_rst);
1146 err = reset_control_deassert(miphy_phy->miphy_rst);
1148 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
1155 static int miphy28lp_of_probe(struct device_node *np,
1156 struct miphy28lp_phy *miphy_phy)
1158 struct resource res;
1160 miphy_phy->osc_force_ext =
1161 of_property_read_bool(np, "st,osc-force-ext");
1163 miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy");
1165 miphy_phy->px_rx_pol_inv =
1166 of_property_read_bool(np, "st,px_rx_pol_inv");
1168 miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
1170 miphy_phy->tx_impedance =
1171 of_property_read_bool(np, "st,tx-impedance-comp");
1173 of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
1174 if (!miphy_phy->sata_gen)
1175 miphy_phy->sata_gen = SATA_GEN1;
1177 if (!miphy28lp_get_resource_byname(np, "miphy-ctrl-glue", &res))
1178 miphy_phy->syscfg_miphy_ctrl = res.start;
1180 if (!miphy28lp_get_resource_byname(np, "miphy-status-glue", &res))
1181 miphy_phy->syscfg_miphy_status = res.start;
1183 if (!miphy28lp_get_resource_byname(np, "pcie-glue", &res))
1184 miphy_phy->syscfg_pci = res.start;
1186 if (!miphy28lp_get_resource_byname(np, "sata-glue", &res))
1187 miphy_phy->syscfg_sata = res.start;
1193 static int miphy28lp_probe(struct platform_device *pdev)
1195 struct device_node *child, *np = pdev->dev.of_node;
1196 struct miphy28lp_dev *miphy_dev;
1197 struct phy_provider *provider;
1199 int chancount, port = 0;
1202 miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
1206 chancount = of_get_child_count(np);
1207 miphy_dev->phys = devm_kzalloc(&pdev->dev, sizeof(phy) * chancount,
1209 if (!miphy_dev->phys)
1212 miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1213 if (IS_ERR(miphy_dev->regmap)) {
1214 dev_err(miphy_dev->dev, "No syscfg phandle specified\n");
1215 return PTR_ERR(miphy_dev->regmap);
1218 miphy_dev->dev = &pdev->dev;
1220 dev_set_drvdata(&pdev->dev, miphy_dev);
1222 mutex_init(&miphy_dev->miphy_mutex);
1224 for_each_child_of_node(np, child) {
1225 struct miphy28lp_phy *miphy_phy;
1227 miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
1232 miphy_dev->phys[port] = miphy_phy;
1234 phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops);
1236 dev_err(&pdev->dev, "failed to create PHY\n");
1237 return PTR_ERR(phy);
1240 miphy_dev->phys[port]->phy = phy;
1241 miphy_dev->phys[port]->phydev = miphy_dev;
1243 ret = miphy28lp_of_probe(child, miphy_phy);
1247 ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]);
1251 phy_set_drvdata(phy, miphy_dev->phys[port]);
1256 provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate);
1257 if (IS_ERR(provider))
1258 return PTR_ERR(provider);
1263 static const struct of_device_id miphy28lp_of_match[] = {
1264 {.compatible = "st,miphy28lp-phy", },
1268 MODULE_DEVICE_TABLE(of, miphy28lp_of_match);
1270 static struct platform_driver miphy28lp_driver = {
1271 .probe = miphy28lp_probe,
1273 .name = "miphy28lp-phy",
1274 .owner = THIS_MODULE,
1275 .of_match_table = miphy28lp_of_match,
1279 module_platform_driver(miphy28lp_driver);
1281 MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
1282 MODULE_DESCRIPTION("STMicroelectronics miphy28lp driver");
1283 MODULE_LICENSE("GPL v2");