2 * Rockchip emmc PHY driver
4 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
5 * Copyright (C) 2016 ROCKCHIP, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
28 * The higher 16-bit of this register is used for write protection
29 * only if BIT(x + 16) set to 1 the BIT(x) can be written.
31 #define HIWORD_UPDATE(val, mask, shift) \
32 ((val) << (shift) | (mask) << ((shift) + 16))
34 /* Register definition */
35 #define GRF_EMMCPHY_CON0 0x0
36 #define GRF_EMMCPHY_CON1 0x4
37 #define GRF_EMMCPHY_CON2 0x8
38 #define GRF_EMMCPHY_CON3 0xc
39 #define GRF_EMMCPHY_CON4 0x10
40 #define GRF_EMMCPHY_CON5 0x14
41 #define GRF_EMMCPHY_CON6 0x18
42 #define GRF_EMMCPHY_STATUS 0x20
44 #define PHYCTRL_PDB_MASK 0x1
45 #define PHYCTRL_PDB_SHIFT 0x0
46 #define PHYCTRL_PDB_PWR_ON 0x1
47 #define PHYCTRL_PDB_PWR_OFF 0x0
48 #define PHYCTRL_ENDLL_MASK 0x1
49 #define PHYCTRL_ENDLL_SHIFT 0x1
50 #define PHYCTRL_ENDLL_ENABLE 0x1
51 #define PHYCTRL_ENDLL_DISABLE 0x0
52 #define PHYCTRL_CALDONE_MASK 0x1
53 #define PHYCTRL_CALDONE_SHIFT 0x6
54 #define PHYCTRL_CALDONE_DONE 0x1
55 #define PHYCTRL_CALDONE_GOING 0x0
56 #define PHYCTRL_DLLRDY_MASK 0x1
57 #define PHYCTRL_DLLRDY_SHIFT 0x5
58 #define PHYCTRL_DLLRDY_DONE 0x1
59 #define PHYCTRL_DLLRDY_GOING 0x0
60 #define PHYCTRL_FREQSEL_200M 0x0
61 #define PHYCTRL_FREQSEL_50M 0x1
62 #define PHYCTRL_FREQSEL_100M 0x2
63 #define PHYCTRL_FREQSEL_150M 0x3
64 #define PHYCTRL_FREQSEL_MASK 0x3
65 #define PHYCTRL_FREQSEL_SHIFT 0xc
66 #define PHYCTRL_DR_MASK 0x7
67 #define PHYCTRL_DR_SHIFT 0x4
68 #define PHYCTRL_DR_50OHM 0x0
69 #define PHYCTRL_DR_33OHM 0x1
70 #define PHYCTRL_DR_66OHM 0x2
71 #define PHYCTRL_DR_100OHM 0x3
72 #define PHYCTRL_DR_40OHM 0x4
73 #define PHYCTRL_OTAPDLYENA 0x1
74 #define PHYCTRL_OTAPDLYENA_MASK 0x1
75 #define PHYCTRL_OTAPDLYENA_SHIFT 0xb
76 #define PHYCTRL_OTAPDLYSEL_MASK 0xf
77 #define PHYCTRL_OTAPDLYSEL_SHIFT 0x7
78 #define PHYCTRL_REN_STRB_ENABLE 0x1
79 #define PHYCTRL_REN_STRB_MASK 0x1
80 #define PHYCTRL_REN_STRB_SHIFT 0x9
82 struct rockchip_emmc_phy {
83 unsigned int reg_offset;
84 struct regmap *reg_base;
88 static int rockchip_emmc_phy_power(struct phy *phy, bool on_off)
90 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
93 unsigned int freqsel = PHYCTRL_FREQSEL_200M;
95 unsigned long timeout;
98 * Keep phyctrl_pdb and phyctrl_endll low to allow
99 * initialization of CALIO state M/C DFFs
101 regmap_write(rk_phy->reg_base,
102 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
103 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
106 regmap_write(rk_phy->reg_base,
107 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
108 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
110 PHYCTRL_ENDLL_SHIFT));
112 /* Already finish power_off above */
113 if (on_off == PHYCTRL_PDB_PWR_OFF)
116 rate = clk_get_rate(rk_phy->emmcclk);
119 unsigned long ideal_rate;
124 ideal_rate = 50000000;
125 freqsel = PHYCTRL_FREQSEL_50M;
127 case 75000000 ... 124999999:
128 ideal_rate = 100000000;
129 freqsel = PHYCTRL_FREQSEL_100M;
131 case 125000000 ... 174999999:
132 ideal_rate = 150000000;
133 freqsel = PHYCTRL_FREQSEL_150M;
136 ideal_rate = 200000000;
140 diff = (rate > ideal_rate) ?
141 rate - ideal_rate : ideal_rate - rate;
144 * In order for tuning delays to be accurate we need to be
145 * pretty spot on for the DLL range, so warn if we're too
146 * far off. Also warn if we're above the 200 MHz max. Don't
147 * warn for really slow rates since we won't be tuning then.
149 if ((rate > 50000000 && diff > 15000000) || (rate > 200000000))
150 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
154 * According to the user manual, calpad calibration
155 * cycle takes more than 2us without the minimal recommended
156 * value, so we may need a little margin here
159 regmap_write(rk_phy->reg_base,
160 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
161 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
166 * According to the user manual, it asks driver to
167 * wait 5us for calpad busy trimming
170 regmap_read(rk_phy->reg_base,
171 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
173 caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
174 if (caldone != PHYCTRL_CALDONE_DONE) {
175 pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
179 /* Set the frequency of the DLL operation */
180 regmap_write(rk_phy->reg_base,
181 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
182 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
183 PHYCTRL_FREQSEL_SHIFT));
185 /* Turn on the DLL */
186 regmap_write(rk_phy->reg_base,
187 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
188 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
190 PHYCTRL_ENDLL_SHIFT));
193 * We turned on the DLL even though the rate was 0 because we the
194 * clock might be turned on later. ...but we can't wait for the DLL
195 * to lock when the rate is 0 because it will never lock with no
198 * Technically we should be checking the lock later when the clock
199 * is turned on, but for now we won't.
205 * After enabling analog DLL circuits docs say that we need 10.2 us if
206 * our source clock is at 50 MHz and that lock time scales linearly
207 * with clock speed. If we are powering on the PHY and the card clock
208 * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
209 * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
210 * Hopefully we won't be running at 100 kHz, but we should still make
211 * sure we wait long enough.
213 * NOTE: There appear to be corner cases where the DLL seems to take
214 * extra long to lock for reasons that aren't understood. In some
215 * extreme cases we've seen it take up to over 10ms (!). We'll be
216 * generous and give it 50ms. We still busy wait here because:
217 * - In most cases it should be super fast.
218 * - This is not called lots during normal operation so it shouldn't
219 * be a power or performance problem to busy wait. We expect it
220 * only at boot / resume. In both cases, eMMC is probably on the
221 * critical path so busy waiting a little extra time should be OK.
223 timeout = jiffies + msecs_to_jiffies(50);
227 regmap_read(rk_phy->reg_base,
228 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
230 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
231 if (dllrdy == PHYCTRL_DLLRDY_DONE)
233 } while (!time_after(jiffies, timeout));
235 if (dllrdy != PHYCTRL_DLLRDY_DONE) {
236 pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
243 static int rockchip_emmc_phy_init(struct phy *phy)
245 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
249 * We purposely get the clock here and not in probe to avoid the
250 * circular dependency problem. We expect:
251 * - PHY driver to probe
252 * - SDHCI driver to start probe
253 * - SDHCI driver to register it's clock
254 * - SDHCI driver to get the PHY
255 * - SDHCI driver to init the PHY
257 * The clock is optional, so upon any error we just set to NULL.
259 * NOTE: we don't do anything special for EPROBE_DEFER here. Given the
260 * above expected use case, EPROBE_DEFER isn't sensible to expect, so
261 * it's just like any other error.
263 rk_phy->emmcclk = clk_get(&phy->dev, "emmcclk");
264 if (IS_ERR(rk_phy->emmcclk)) {
265 dev_dbg(&phy->dev, "Error getting emmcclk: %d\n", ret);
266 rk_phy->emmcclk = NULL;
272 static int rockchip_emmc_phy_exit(struct phy *phy)
274 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
276 clk_put(rk_phy->emmcclk);
281 static int rockchip_emmc_phy_power_off(struct phy *phy)
283 /* Power down emmc phy analog blocks */
284 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF);
287 static int rockchip_emmc_phy_power_on(struct phy *phy)
289 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
291 /* Drive impedance: 50 Ohm */
292 regmap_write(rk_phy->reg_base,
293 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
294 HIWORD_UPDATE(PHYCTRL_DR_50OHM,
298 /* Output tap delay: enable */
299 regmap_write(rk_phy->reg_base,
300 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
301 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
302 PHYCTRL_OTAPDLYENA_MASK,
303 PHYCTRL_OTAPDLYENA_SHIFT));
305 /* Output tap delay */
306 regmap_write(rk_phy->reg_base,
307 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
309 PHYCTRL_OTAPDLYSEL_MASK,
310 PHYCTRL_OTAPDLYSEL_SHIFT));
312 /* Internal pull-down for strobe line: enable */
313 regmap_write(rk_phy->reg_base,
314 rk_phy->reg_offset + GRF_EMMCPHY_CON2,
315 HIWORD_UPDATE(PHYCTRL_REN_STRB_ENABLE,
316 PHYCTRL_REN_STRB_MASK,
317 PHYCTRL_REN_STRB_SHIFT));
319 /* Power up emmc phy analog blocks */
320 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON);
323 static const struct phy_ops ops = {
324 .init = rockchip_emmc_phy_init,
325 .exit = rockchip_emmc_phy_exit,
326 .power_on = rockchip_emmc_phy_power_on,
327 .power_off = rockchip_emmc_phy_power_off,
328 .owner = THIS_MODULE,
331 static int rockchip_emmc_phy_probe(struct platform_device *pdev)
333 struct device *dev = &pdev->dev;
334 struct rockchip_emmc_phy *rk_phy;
335 struct phy *generic_phy;
336 struct phy_provider *phy_provider;
338 unsigned int reg_offset;
340 if (!dev->parent || !dev->parent->of_node)
343 grf = syscon_node_to_regmap(dev->parent->of_node);
345 dev_err(dev, "Missing rockchip,grf property\n");
349 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
353 if (of_property_read_u32(dev->of_node, "reg", ®_offset)) {
354 dev_err(dev, "missing reg property in node %s\n",
359 rk_phy->reg_offset = reg_offset;
360 rk_phy->reg_base = grf;
362 generic_phy = devm_phy_create(dev, dev->of_node, &ops);
363 if (IS_ERR(generic_phy)) {
364 dev_err(dev, "failed to create PHY\n");
365 return PTR_ERR(generic_phy);
368 phy_set_drvdata(generic_phy, rk_phy);
369 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
371 return PTR_ERR_OR_ZERO(phy_provider);
374 static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
375 { .compatible = "rockchip,rk3399-emmc-phy" },
379 MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
381 static struct platform_driver rockchip_emmc_driver = {
382 .probe = rockchip_emmc_phy_probe,
384 .name = "rockchip-emmc-phy",
385 .of_match_table = rockchip_emmc_phy_dt_ids,
389 module_platform_driver(rockchip_emmc_driver);
391 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
392 MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
393 MODULE_LICENSE("GPL v2");