2 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/extcon.h>
21 #include <linux/interrupt.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/jiffies.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/mutex.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/phy/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/power_supply.h>
35 #include <linux/regmap.h>
36 #include <linux/mfd/syscon.h>
37 #include <linux/usb/otg.h>
38 #include <linux/wakelock.h>
40 #define BIT_WRITEABLE_SHIFT 16
41 #define SCHEDULE_DELAY (60 * HZ)
42 #define OTG_SCHEDULE_DELAY (2 * HZ)
44 struct rockchip_usb2phy;
46 enum rockchip_usb2phy_port_id {
52 enum rockchip_usb2phy_host_state {
53 PHY_STATE_HS_ONLINE = 0,
54 PHY_STATE_DISCONNECT = 1,
55 PHY_STATE_CONNECT = 2,
56 PHY_STATE_FS_LS_ONLINE = 4,
60 * Different states involved in USB charger detection.
61 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
62 * process is not yet started.
63 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
64 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
65 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
66 * between SDP and DCP/CDP).
67 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
68 * between DCP and CDP).
69 * USB_CHG_STATE_DETECTED USB charger type is determined.
72 USB_CHG_STATE_UNDEFINED = 0,
73 USB_CHG_STATE_WAIT_FOR_DCD,
74 USB_CHG_STATE_DCD_DONE,
75 USB_CHG_STATE_PRIMARY_DONE,
76 USB_CHG_STATE_SECONDARY_DONE,
77 USB_CHG_STATE_DETECTED,
80 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
93 unsigned int bitstart;
99 * struct rockchip_chg_det_reg: usb charger detect registers
100 * @cp_det: charging port detected successfully.
101 * @dcp_det: dedicated charging port detected successfully.
102 * @dp_det: assert data pin connect successfully.
103 * @idm_sink_en: open dm sink curren.
104 * @idp_sink_en: open dp sink current.
105 * @idp_src_en: open dm source current.
106 * @rdm_pdwn_en: open dm pull down resistor.
107 * @vdm_src_en: open dm voltage source.
108 * @vdp_src_en: open dp voltage source.
109 * @opmode: utmi operational mode.
111 struct rockchip_chg_det_reg {
112 struct usb2phy_reg cp_det;
113 struct usb2phy_reg dcp_det;
114 struct usb2phy_reg dp_det;
115 struct usb2phy_reg idm_sink_en;
116 struct usb2phy_reg idp_sink_en;
117 struct usb2phy_reg idp_src_en;
118 struct usb2phy_reg rdm_pdwn_en;
119 struct usb2phy_reg vdm_src_en;
120 struct usb2phy_reg vdp_src_en;
121 struct usb2phy_reg opmode;
125 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
126 * @phy_sus: phy suspend register.
127 * @bvalid_det_en: vbus valid rise detection enable register.
128 * @bvalid_det_st: vbus valid rise detection status register.
129 * @bvalid_det_clr: vbus valid rise detection clear register.
130 * @ls_det_en: linestate detection enable register.
131 * @ls_det_st: linestate detection state register.
132 * @ls_det_clr: linestate detection clear register.
133 * @utmi_bvalid: utmi vbus valid status register.
134 * @utmi_ls: utmi linestate state register.
135 * @utmi_hstdet: utmi host disconnect register.
137 struct rockchip_usb2phy_port_cfg {
138 struct usb2phy_reg phy_sus;
139 struct usb2phy_reg bvalid_det_en;
140 struct usb2phy_reg bvalid_det_st;
141 struct usb2phy_reg bvalid_det_clr;
142 struct usb2phy_reg ls_det_en;
143 struct usb2phy_reg ls_det_st;
144 struct usb2phy_reg ls_det_clr;
145 struct usb2phy_reg utmi_bvalid;
146 struct usb2phy_reg utmi_ls;
147 struct usb2phy_reg utmi_hstdet;
151 * struct rockchip_usb2phy_cfg: usb-phy configuration.
152 * @reg: the address offset of grf for usb-phy config.
153 * @num_ports: specify how many ports that the phy has.
154 * @phy_tuning: phy default parameters tunning.
155 * @clkout_ctl: keep on/turn off output clk of phy.
156 * @chg_det: charger detection registers.
158 struct rockchip_usb2phy_cfg {
160 unsigned int num_ports;
161 int (*phy_tuning)(struct rockchip_usb2phy *);
162 struct usb2phy_reg clkout_ctl;
163 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
164 const struct rockchip_chg_det_reg chg_det;
168 * struct rockchip_usb2phy_port: usb-phy port data.
169 * @port_id: flag for otg port or host port.
170 * @suspended: phy suspended flag.
171 * @vbus_attached: otg device vbus status.
172 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
173 * @ls_irq: IRQ number assigned for linestate detection.
174 * @mutex: for register updating in sm_work.
175 * @chg_work: charge detect work.
176 * @otg_sm_work: OTG state machine work.
177 * @sm_work: HOST state machine work.
178 * @phy_cfg: port register configuration, assigned by driver data.
179 * @event_nb: hold event notification callback.
180 * @wakelock: wake lock struct to prevent system suspend
181 * when USB is active.
182 * @state: define OTG enumeration states before device reset.
184 struct rockchip_usb2phy_port {
186 unsigned int port_id;
192 struct delayed_work chg_work;
193 struct delayed_work otg_sm_work;
194 struct delayed_work sm_work;
195 const struct rockchip_usb2phy_port_cfg *port_cfg;
196 struct notifier_block event_nb;
197 struct wake_lock wakelock;
198 enum usb_otg_state state;
202 * struct rockchip_usb2phy: usb2.0 phy driver data.
203 * @grf: General Register Files regmap.
204 * @clk: clock struct of phy input clk.
205 * @clk480m: clock struct of phy output clk.
206 * @clk_hw: clock struct of phy output clk management.
207 * @chg_state: states involved in USB charger detection.
208 * @chg_type: USB charger types.
209 * @dcd_retries: The retry count used to track Data contact
211 * @edev: extcon device for notification registration
212 * @phy_cfg: phy register configuration, assigned by driver data.
213 * @ports: phy port instance.
215 struct rockchip_usb2phy {
220 struct clk_hw clk480m_hw;
221 enum usb_chg_state chg_state;
222 enum power_supply_type chg_type;
224 struct extcon_dev *edev;
225 const struct rockchip_usb2phy_cfg *phy_cfg;
226 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
229 static inline int property_enable(struct rockchip_usb2phy *rphy,
230 const struct usb2phy_reg *reg, bool en)
232 unsigned int val, mask, tmp;
234 tmp = en ? reg->enable : reg->disable;
235 mask = GENMASK(reg->bitend, reg->bitstart);
236 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
238 return regmap_write(rphy->grf, reg->offset, val);
241 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
242 const struct usb2phy_reg *reg)
245 unsigned int tmp, orig;
246 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
248 ret = regmap_read(rphy->grf, reg->offset, &orig);
252 tmp = (orig & mask) >> reg->bitstart;
253 return tmp == reg->enable;
256 static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
258 struct rockchip_usb2phy *rphy =
259 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
262 /* turn on 480m clk output if it is off */
263 if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
264 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
268 /* waitting for the clk become stable */
275 static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
277 struct rockchip_usb2phy *rphy =
278 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
280 /* turn off 480m clk output */
281 property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
284 static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
286 struct rockchip_usb2phy *rphy =
287 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
289 return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
293 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
294 unsigned long parent_rate)
299 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
300 .enable = rockchip_usb2phy_clk480m_enable,
301 .disable = rockchip_usb2phy_clk480m_disable,
302 .is_enabled = rockchip_usb2phy_clk480m_enabled,
303 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
306 static void rockchip_usb2phy_clk480m_unregister(void *data)
308 struct rockchip_usb2phy *rphy = data;
310 of_clk_del_provider(rphy->dev->of_node);
311 clk_unregister(rphy->clk480m);
315 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
317 struct device_node *node = rphy->dev->of_node;
318 struct clk_init_data init;
319 const char *clk_name;
323 init.name = "clk_usbphy_480m";
324 init.ops = &rockchip_usb2phy_clkout_ops;
326 /* optional override of the clockname */
327 of_property_read_string(node, "clock-output-names", &init.name);
330 clk_name = __clk_get_name(rphy->clk);
331 init.parent_names = &clk_name;
332 init.num_parents = 1;
334 init.parent_names = NULL;
335 init.num_parents = 0;
338 rphy->clk480m_hw.init = &init;
340 /* register the clock */
341 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
342 if (IS_ERR(rphy->clk480m)) {
343 ret = PTR_ERR(rphy->clk480m);
347 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
349 goto err_clk_provider;
351 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
354 goto err_unreg_action;
359 of_clk_del_provider(node);
361 clk_unregister(rphy->clk480m);
366 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
369 struct device_node *node = rphy->dev->of_node;
370 struct extcon_dev *edev;
372 if (of_property_read_bool(node, "extcon")) {
373 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
375 if (PTR_ERR(edev) != -EPROBE_DEFER)
376 dev_err(rphy->dev, "Invalid or missing extcon\n");
377 return PTR_ERR(edev);
380 /* Initialize extcon device */
381 edev = devm_extcon_dev_allocate(rphy->dev,
382 rockchip_usb2phy_extcon_cable);
387 ret = devm_extcon_dev_register(rphy->dev, edev);
389 dev_err(rphy->dev, "failed to register extcon device\n");
399 static int rockchip_usb2phy_init(struct phy *phy)
401 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
402 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
405 mutex_lock(&rport->mutex);
407 if (rport->port_id == USB2PHY_PORT_OTG) {
408 /* clear bvalid status and enable bvalid detect irq */
409 ret = property_enable(rphy,
410 &rport->port_cfg->bvalid_det_clr, true);
412 mutex_unlock(&rport->mutex);
416 ret = property_enable(rphy,
417 &rport->port_cfg->bvalid_det_en, true);
419 mutex_unlock(&rport->mutex);
423 mutex_unlock(&rport->mutex);
424 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
426 } else if (rport->port_id == USB2PHY_PORT_HOST) {
427 /* clear linestate and enable linestate detect irq */
428 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
430 mutex_unlock(&rport->mutex);
434 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
436 mutex_unlock(&rport->mutex);
440 mutex_unlock(&rport->mutex);
441 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
447 static int rockchip_usb2phy_power_on(struct phy *phy)
449 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
450 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
453 dev_dbg(&rport->phy->dev, "port power on\n");
455 if (!rport->suspended)
458 ret = clk_prepare_enable(rphy->clk480m);
462 ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
466 rport->suspended = false;
470 static int rockchip_usb2phy_power_off(struct phy *phy)
472 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
473 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
476 dev_dbg(&rport->phy->dev, "port power off\n");
478 if (rport->suspended)
481 ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
485 rport->suspended = true;
486 clk_disable_unprepare(rphy->clk480m);
491 static int rockchip_usb2phy_exit(struct phy *phy)
493 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
495 if (rport->port_id == USB2PHY_PORT_OTG) {
496 cancel_delayed_work_sync(&rport->chg_work);
497 cancel_delayed_work_sync(&rport->otg_sm_work);
498 } else if (rport->port_id == USB2PHY_PORT_HOST)
499 cancel_delayed_work_sync(&rport->sm_work);
504 static const struct phy_ops rockchip_usb2phy_ops = {
505 .init = rockchip_usb2phy_init,
506 .exit = rockchip_usb2phy_exit,
507 .power_on = rockchip_usb2phy_power_on,
508 .power_off = rockchip_usb2phy_power_off,
509 .owner = THIS_MODULE,
512 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
514 struct rockchip_usb2phy_port *rport =
515 container_of(work, struct rockchip_usb2phy_port,
517 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
518 static unsigned int cable;
520 bool vbus_attach, sch_work, notify_charger;
522 vbus_attach = property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
524 notify_charger = false;
525 delay = OTG_SCHEDULE_DELAY;
526 dev_dbg(&rport->phy->dev, "%s otg sm work\n",
527 usb_otg_state_string(rport->state));
529 switch (rport->state) {
530 case OTG_STATE_UNDEFINED:
531 rport->state = OTG_STATE_B_IDLE;
533 rockchip_usb2phy_power_off(rport->phy);
535 case OTG_STATE_B_IDLE:
536 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0) {
537 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
538 rport->state = OTG_STATE_A_HOST;
539 rockchip_usb2phy_power_on(rport->phy);
541 } else if (vbus_attach) {
542 dev_dbg(&rport->phy->dev, "vbus_attach\n");
543 switch (rphy->chg_state) {
544 case USB_CHG_STATE_UNDEFINED:
545 schedule_delayed_work(&rport->chg_work, 0);
547 case USB_CHG_STATE_DETECTED:
548 switch (rphy->chg_type) {
549 case POWER_SUPPLY_TYPE_USB:
550 dev_dbg(&rport->phy->dev,
551 "sdp cable is connecetd\n");
552 wake_lock(&rport->wakelock);
553 rockchip_usb2phy_power_on(rport->phy);
554 rport->state = OTG_STATE_B_PERIPHERAL;
555 notify_charger = true;
557 cable = EXTCON_CHG_USB_SDP;
559 case POWER_SUPPLY_TYPE_USB_DCP:
560 dev_dbg(&rport->phy->dev,
561 "dcp cable is connecetd\n");
562 rockchip_usb2phy_power_off(rport->phy);
563 notify_charger = true;
565 cable = EXTCON_CHG_USB_DCP;
567 case POWER_SUPPLY_TYPE_USB_CDP:
568 dev_dbg(&rport->phy->dev,
569 "cdp cable is connecetd\n");
570 wake_lock(&rport->wakelock);
571 rockchip_usb2phy_power_on(rport->phy);
572 rport->state = OTG_STATE_B_PERIPHERAL;
573 notify_charger = true;
575 cable = EXTCON_CHG_USB_CDP;
577 case POWER_SUPPLY_TYPE_USB_FLOATING:
578 dev_dbg(&rport->phy->dev,
579 "floating cable is connecetd\n");
580 rockchip_usb2phy_power_off(rport->phy);
581 notify_charger = true;
583 cable = EXTCON_CHG_USB_SLOW;
593 notify_charger = true;
594 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
595 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
598 if (rport->vbus_attached != vbus_attach) {
599 rport->vbus_attached = vbus_attach;
601 if (notify_charger && rphy->edev)
602 extcon_set_cable_state_(rphy->edev,
606 case OTG_STATE_B_PERIPHERAL:
608 dev_dbg(&rport->phy->dev, "usb disconnect\n");
609 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
610 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
611 rport->state = OTG_STATE_B_IDLE;
613 rockchip_usb2phy_power_off(rport->phy);
614 wake_unlock(&rport->wakelock);
618 case OTG_STATE_A_HOST:
619 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
620 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
621 rport->state = OTG_STATE_B_IDLE;
622 rockchip_usb2phy_power_off(rport->phy);
630 schedule_delayed_work(&rport->otg_sm_work, delay);
633 static const char *chg_to_string(enum power_supply_type chg_type)
636 case POWER_SUPPLY_TYPE_USB:
637 return "USB_SDP_CHARGER";
638 case POWER_SUPPLY_TYPE_USB_DCP:
639 return "USB_DCP_CHARGER";
640 case POWER_SUPPLY_TYPE_USB_CDP:
641 return "USB_CDP_CHARGER";
642 case POWER_SUPPLY_TYPE_USB_FLOATING:
643 return "USB_FLOATING_CHARGER";
645 return "INVALID_CHARGER";
649 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
652 property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
653 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
656 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
659 property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
660 property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
663 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
666 property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
667 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
670 #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
671 #define CHG_DCD_MAX_RETRIES 6
672 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
673 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
674 static void rockchip_chg_detect_work(struct work_struct *work)
676 struct rockchip_usb2phy_port *rport =
677 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
678 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
679 bool is_dcd, tmout, vout;
682 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
684 switch (rphy->chg_state) {
685 case USB_CHG_STATE_UNDEFINED:
686 if (!rport->suspended)
687 rockchip_usb2phy_power_off(rport->phy);
688 /* put the controller in non-driving mode */
689 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
690 /* Start DCD processing stage 1 */
691 rockchip_chg_enable_dcd(rphy, true);
692 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
693 rphy->dcd_retries = 0;
694 delay = CHG_DCD_POLL_TIME;
696 case USB_CHG_STATE_WAIT_FOR_DCD:
697 /* get data contact detection status */
698 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
699 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
701 if (is_dcd || tmout) {
703 /* Turn off DCD circuitry */
704 rockchip_chg_enable_dcd(rphy, false);
705 /* Voltage Source on DP, Probe on DM */
706 rockchip_chg_enable_primary_det(rphy, true);
707 delay = CHG_PRIMARY_DET_TIME;
708 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
711 delay = CHG_DCD_POLL_TIME;
714 case USB_CHG_STATE_DCD_DONE:
715 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
716 rockchip_chg_enable_primary_det(rphy, false);
718 /* Voltage Source on DM, Probe on DP */
719 rockchip_chg_enable_secondary_det(rphy, true);
720 delay = CHG_SECONDARY_DET_TIME;
721 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
724 /* floating charger found */
725 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
726 rphy->chg_state = USB_CHG_STATE_DETECTED;
729 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
730 rphy->chg_state = USB_CHG_STATE_DETECTED;
735 case USB_CHG_STATE_PRIMARY_DONE:
736 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
737 /* Turn off voltage source */
738 rockchip_chg_enable_secondary_det(rphy, false);
740 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
742 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
744 case USB_CHG_STATE_SECONDARY_DONE:
745 rphy->chg_state = USB_CHG_STATE_DETECTED;
748 case USB_CHG_STATE_DETECTED:
749 /* put the controller in normal mode */
750 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
751 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
752 dev_info(&rport->phy->dev, "charger = %s\n",
753 chg_to_string(rphy->chg_type));
759 schedule_delayed_work(&rport->chg_work, delay);
763 * The function manage host-phy port state and suspend/resume phy port
766 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
767 * devices is disconnect or not. Besides, we do not need care it is FS/LS
768 * disconnected or HS disconnected, actually, we just only need get the
769 * device is disconnected at last through rearm the delayed work,
770 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
772 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
773 * some clk related APIs, so do not invoke it from interrupt context directly.
775 static void rockchip_usb2phy_sm_work(struct work_struct *work)
777 struct rockchip_usb2phy_port *rport =
778 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
779 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
780 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
781 rport->port_cfg->utmi_hstdet.bitstart + 1;
782 unsigned int ul, uhd, state;
783 unsigned int ul_mask, uhd_mask;
786 mutex_lock(&rport->mutex);
788 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
792 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
797 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
798 rport->port_cfg->utmi_hstdet.bitstart);
799 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
800 rport->port_cfg->utmi_ls.bitstart);
802 /* stitch on utmi_ls and utmi_hstdet as phy state */
803 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
804 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
807 case PHY_STATE_HS_ONLINE:
808 dev_dbg(&rport->phy->dev, "HS online\n");
810 case PHY_STATE_FS_LS_ONLINE:
812 * For FS/LS device, the online state share with connect state
813 * from utmi_ls and utmi_hstdet register, so we distinguish
814 * them via suspended flag.
816 * Plus, there are two cases, one is D- Line pull-up, and D+
817 * line pull-down, the state is 4; another is D+ line pull-up,
818 * and D- line pull-down, the state is 2.
820 if (!rport->suspended) {
821 /* D- line pull-up, D+ line pull-down */
822 dev_dbg(&rport->phy->dev, "FS/LS online\n");
826 case PHY_STATE_CONNECT:
827 if (rport->suspended) {
828 dev_dbg(&rport->phy->dev, "Connected\n");
829 rockchip_usb2phy_power_on(rport->phy);
830 rport->suspended = false;
832 /* D+ line pull-up, D- line pull-down */
833 dev_dbg(&rport->phy->dev, "FS/LS online\n");
836 case PHY_STATE_DISCONNECT:
837 if (!rport->suspended) {
838 dev_dbg(&rport->phy->dev, "Disconnected\n");
839 rockchip_usb2phy_power_off(rport->phy);
840 rport->suspended = true;
844 * activate the linestate detection to get the next device
847 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
848 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
851 * we don't need to rearm the delayed work when the phy port
854 mutex_unlock(&rport->mutex);
857 dev_dbg(&rport->phy->dev, "unknown phy state\n");
862 mutex_unlock(&rport->mutex);
863 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
866 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
868 struct rockchip_usb2phy_port *rport = data;
869 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
871 if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
874 mutex_lock(&rport->mutex);
876 /* disable linestate detect irq and clear its status */
877 property_enable(rphy, &rport->port_cfg->ls_det_en, false);
878 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
880 mutex_unlock(&rport->mutex);
883 * In this case for host phy port, a new device is plugged in,
884 * meanwhile, if the phy port is suspended, we need rearm the work to
885 * resume it and mange its states; otherwise, we do nothing about that.
887 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
888 rockchip_usb2phy_sm_work(&rport->sm_work.work);
893 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
895 struct rockchip_usb2phy_port *rport = data;
896 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
898 if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
901 mutex_lock(&rport->mutex);
903 /* clear bvalid detect irq pending status */
904 property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
906 mutex_unlock(&rport->mutex);
908 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
913 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
914 struct rockchip_usb2phy_port *rport,
915 struct device_node *child_np)
919 rport->port_id = USB2PHY_PORT_HOST;
920 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
921 rport->suspended = true;
923 mutex_init(&rport->mutex);
924 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
926 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
927 if (rport->ls_irq < 0) {
928 dev_err(rphy->dev, "no linestate irq provided\n");
929 return rport->ls_irq;
932 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
933 rockchip_usb2phy_linestate_irq,
935 "rockchip_usb2phy", rport);
937 dev_err(rphy->dev, "failed to request linestate irq handle\n");
944 static int rockchip_otg_event(struct notifier_block *nb,
945 unsigned long event, void *ptr)
947 struct rockchip_usb2phy_port *rport =
948 container_of(nb, struct rockchip_usb2phy_port, event_nb);
950 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
955 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
956 struct rockchip_usb2phy_port *rport,
957 struct device_node *child_np)
961 rport->port_id = USB2PHY_PORT_OTG;
962 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
963 rport->state = OTG_STATE_UNDEFINED;
965 * set suspended flag to true, but actually don't
966 * put phy in suspend mode, it aims to enable usb
967 * phy and clock in power_on() called by usb controller
968 * driver during probe.
970 rport->suspended = true;
971 rport->vbus_attached = false;
973 mutex_init(&rport->mutex);
974 wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
975 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
976 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
978 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
979 if (rport->bvalid_irq < 0) {
980 dev_err(rphy->dev, "no vbus valid irq provided\n");
981 return rport->bvalid_irq;
984 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
985 rockchip_usb2phy_bvalid_irq,
987 "rockchip_usb2phy_bvalid", rport);
989 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
993 if (!IS_ERR(rphy->edev)) {
994 rport->event_nb.notifier_call = rockchip_otg_event;
996 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
999 dev_err(rphy->dev, "register USB HOST notifier failed\n");
1007 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1009 struct device *dev = &pdev->dev;
1010 struct device_node *np = dev->of_node;
1011 struct device_node *child_np;
1012 struct phy_provider *provider;
1013 struct rockchip_usb2phy *rphy;
1014 const struct rockchip_usb2phy_cfg *phy_cfgs;
1015 const struct of_device_id *match;
1019 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1023 match = of_match_device(dev->driver->of_match_table, dev);
1024 if (!match || !match->data) {
1025 dev_err(dev, "phy configs are not assigned!\n");
1029 if (!dev->parent || !dev->parent->of_node)
1032 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1033 if (IS_ERR(rphy->grf))
1034 return PTR_ERR(rphy->grf);
1036 if (of_property_read_u32(np, "reg", ®)) {
1037 dev_err(dev, "the reg property is not assigned in %s node\n",
1043 phy_cfgs = match->data;
1044 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1045 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1046 platform_set_drvdata(pdev, rphy);
1048 ret = rockchip_usb2phy_extcon_register(rphy);
1052 /* find out a proper config which can be matched with dt. */
1054 while (phy_cfgs[index].reg) {
1055 if (phy_cfgs[index].reg == reg) {
1056 rphy->phy_cfg = &phy_cfgs[index];
1063 if (!rphy->phy_cfg) {
1064 dev_err(dev, "no phy-config can be matched with %s node\n",
1069 rphy->clk = of_clk_get_by_name(np, "phyclk");
1070 if (!IS_ERR(rphy->clk)) {
1071 clk_prepare_enable(rphy->clk);
1073 dev_info(&pdev->dev, "no phyclk specified\n");
1077 ret = rockchip_usb2phy_clk480m_register(rphy);
1079 dev_err(dev, "failed to register 480m output clock\n");
1083 if (rphy->phy_cfg->phy_tuning) {
1084 ret = rphy->phy_cfg->phy_tuning(rphy);
1090 for_each_available_child_of_node(np, child_np) {
1091 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1094 /* This driver aims to support both otg-port and host-port */
1095 if (of_node_cmp(child_np->name, "host-port") &&
1096 of_node_cmp(child_np->name, "otg-port"))
1099 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1101 dev_err(dev, "failed to create phy\n");
1107 phy_set_drvdata(rport->phy, rport);
1109 /* initialize otg/host port separately */
1110 if (!of_node_cmp(child_np->name, "host-port")) {
1111 ret = rockchip_usb2phy_host_port_init(rphy, rport,
1116 ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1123 /* to prevent out of boundary */
1124 if (++index >= rphy->phy_cfg->num_ports)
1128 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1129 return PTR_ERR_OR_ZERO(provider);
1132 of_node_put(child_np);
1135 clk_disable_unprepare(rphy->clk);
1141 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1143 unsigned int open_pre_emphasize = 0xffff851f;
1144 unsigned int eye_height_tuning = 0xffff68c8;
1145 unsigned int compensation_tuning = 0xffff026e;
1148 /* open HS pre-emphasize to expand HS slew rate for each port. */
1149 ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1150 ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1151 ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1152 ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1154 /* compensate default tuning reference relate to ODT and etc. */
1155 ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1160 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1164 .phy_tuning = rk3366_usb2phy_tuning,
1165 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1167 [USB2PHY_PORT_HOST] = {
1168 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
1169 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1170 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1171 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1172 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
1173 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
1180 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1184 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1186 [USB2PHY_PORT_OTG] = {
1187 .phy_sus = { 0xe454, 1, 0, 2, 1 },
1188 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1189 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1190 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1191 .utmi_bvalid = { 0xe2ac, 7, 7, 0, 1 },
1193 [USB2PHY_PORT_HOST] = {
1194 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1195 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1196 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1197 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1198 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1199 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1203 .opmode = { 0xe454, 3, 0, 5, 1 },
1204 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1205 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1206 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1207 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1208 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1209 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1210 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1211 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1212 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1218 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1220 [USB2PHY_PORT_HOST] = {
1221 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1222 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1223 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1224 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1225 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1226 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1233 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1234 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1235 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1238 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1240 static struct platform_driver rockchip_usb2phy_driver = {
1241 .probe = rockchip_usb2phy_probe,
1243 .name = "rockchip-usb2phy",
1244 .of_match_table = rockchip_usb2phy_dt_match,
1247 module_platform_driver(rockchip_usb2phy_driver);
1249 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1250 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1251 MODULE_LICENSE("GPL v2");