2 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/extcon.h>
21 #include <linux/interrupt.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/jiffies.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/mutex.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/phy/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/power_supply.h>
35 #include <linux/regmap.h>
36 #include <linux/mfd/syscon.h>
37 #include <linux/usb/of.h>
38 #include <linux/usb/otg.h>
39 #include <linux/wakelock.h>
41 #define BIT_WRITEABLE_SHIFT 16
42 #define SCHEDULE_DELAY (60 * HZ)
43 #define OTG_SCHEDULE_DELAY (2 * HZ)
45 struct rockchip_usb2phy;
47 enum rockchip_usb2phy_port_id {
53 enum rockchip_usb2phy_host_state {
54 PHY_STATE_HS_ONLINE = 0,
55 PHY_STATE_DISCONNECT = 1,
56 PHY_STATE_CONNECT = 2,
57 PHY_STATE_FS_LS_ONLINE = 4,
61 * Different states involved in USB charger detection.
62 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
63 * process is not yet started.
64 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
65 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
66 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
67 * between SDP and DCP/CDP).
68 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
69 * between DCP and CDP).
70 * USB_CHG_STATE_DETECTED USB charger type is determined.
73 USB_CHG_STATE_UNDEFINED = 0,
74 USB_CHG_STATE_WAIT_FOR_DCD,
75 USB_CHG_STATE_DCD_DONE,
76 USB_CHG_STATE_PRIMARY_DONE,
77 USB_CHG_STATE_SECONDARY_DONE,
78 USB_CHG_STATE_DETECTED,
81 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
95 unsigned int bitstart;
101 * struct rockchip_chg_det_reg: usb charger detect registers
102 * @cp_det: charging port detected successfully.
103 * @dcp_det: dedicated charging port detected successfully.
104 * @dp_det: assert data pin connect successfully.
105 * @idm_sink_en: open dm sink curren.
106 * @idp_sink_en: open dp sink current.
107 * @idp_src_en: open dm source current.
108 * @rdm_pdwn_en: open dm pull down resistor.
109 * @vdm_src_en: open dm voltage source.
110 * @vdp_src_en: open dp voltage source.
111 * @opmode: utmi operational mode.
113 struct rockchip_chg_det_reg {
114 struct usb2phy_reg cp_det;
115 struct usb2phy_reg dcp_det;
116 struct usb2phy_reg dp_det;
117 struct usb2phy_reg idm_sink_en;
118 struct usb2phy_reg idp_sink_en;
119 struct usb2phy_reg idp_src_en;
120 struct usb2phy_reg rdm_pdwn_en;
121 struct usb2phy_reg vdm_src_en;
122 struct usb2phy_reg vdp_src_en;
123 struct usb2phy_reg opmode;
127 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
128 * @phy_sus: phy suspend register.
129 * @bvalid_det_en: vbus valid rise detection enable register.
130 * @bvalid_det_st: vbus valid rise detection status register.
131 * @bvalid_det_clr: vbus valid rise detection clear register.
132 * @ls_det_en: linestate detection enable register.
133 * @ls_det_st: linestate detection state register.
134 * @ls_det_clr: linestate detection clear register.
135 * @idfall_det_en: id fall detection enable register.
136 * @idfall_det_st: id fall detection state register.
137 * @idfall_det_clr: id fall detection clear register.
138 * @idrise_det_en: id rise detection enable register.
139 * @idrise_det_st: id rise detection state register.
140 * @idrise_det_clr: id rise detection clear register.
141 * @utmi_avalid: utmi vbus avalid status register.
142 * @utmi_bvalid: utmi vbus bvalid status register.
143 * @utmi_iddig: otg port id pin status register.
144 * @utmi_ls: utmi linestate state register.
145 * @utmi_hstdet: utmi host disconnect register.
146 * @vbus_det_en: vbus detect function power down register.
148 struct rockchip_usb2phy_port_cfg {
149 struct usb2phy_reg phy_sus;
150 struct usb2phy_reg bvalid_det_en;
151 struct usb2phy_reg bvalid_det_st;
152 struct usb2phy_reg bvalid_det_clr;
153 struct usb2phy_reg ls_det_en;
154 struct usb2phy_reg ls_det_st;
155 struct usb2phy_reg ls_det_clr;
156 struct usb2phy_reg idfall_det_en;
157 struct usb2phy_reg idfall_det_st;
158 struct usb2phy_reg idfall_det_clr;
159 struct usb2phy_reg idrise_det_en;
160 struct usb2phy_reg idrise_det_st;
161 struct usb2phy_reg idrise_det_clr;
162 struct usb2phy_reg utmi_avalid;
163 struct usb2phy_reg utmi_bvalid;
164 struct usb2phy_reg utmi_iddig;
165 struct usb2phy_reg utmi_ls;
166 struct usb2phy_reg utmi_hstdet;
167 struct usb2phy_reg vbus_det_en;
171 * struct rockchip_usb2phy_cfg: usb-phy configuration.
172 * @reg: the address offset of grf for usb-phy config.
173 * @num_ports: specify how many ports that the phy has.
174 * @phy_tuning: phy default parameters tunning.
175 * @clkout_ctl: keep on/turn off output clk of phy.
176 * @chg_det: charger detection registers.
178 struct rockchip_usb2phy_cfg {
180 unsigned int num_ports;
181 int (*phy_tuning)(struct rockchip_usb2phy *);
182 struct usb2phy_reg clkout_ctl;
183 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
184 const struct rockchip_chg_det_reg chg_det;
188 * struct rockchip_usb2phy_port: usb-phy port data.
189 * @port_id: flag for otg port or host port.
190 * @perip_connected: flag for periphyeral connect status.
191 * @suspended: phy suspended flag.
192 * @utmi_avalid: utmi avalid status usage flag.
193 * true - use avalid to get vbus status
194 * flase - use bvalid to get vbus status
195 * @vbus_attached: otg device vbus status.
196 * @vbus_always_on: otg vbus is always powered on.
197 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
198 * @vbus_drv_gpio: gpio description for vbus control.
199 * @ls_irq: IRQ number assigned for linestate detection.
200 * @id_irq: IRQ number assigned for id fall or rise detection.
201 * @mutex: for register updating in sm_work.
202 * @chg_work: charge detect work.
203 * @otg_sm_work: OTG state machine work.
204 * @sm_work: HOST state machine work.
205 * @phy_cfg: port register configuration, assigned by driver data.
206 * @event_nb: hold event notification callback.
207 * @wakelock: wake lock struct to prevent system suspend
208 * when USB is active.
209 * @state: define OTG enumeration states before device reset.
210 * @mode: the dr_mode of the controller.
212 struct rockchip_usb2phy_port {
214 unsigned int port_id;
215 bool perip_connected;
224 struct delayed_work chg_work;
225 struct delayed_work otg_sm_work;
226 struct delayed_work sm_work;
227 struct gpio_desc *vbus_drv_gpio;
228 const struct rockchip_usb2phy_port_cfg *port_cfg;
229 struct notifier_block event_nb;
230 struct wake_lock wakelock;
231 enum usb_otg_state state;
232 enum usb_dr_mode mode;
236 * struct rockchip_usb2phy: usb2.0 phy driver data.
237 * @grf: General Register Files regmap.
238 * @clk: clock struct of phy input clk.
239 * @clk480m: clock struct of phy output clk.
240 * @clk_hw: clock struct of phy output clk management.
241 * @chg_state: states involved in USB charger detection.
242 * @chg_type: USB charger types.
243 * @dcd_retries: The retry count used to track Data contact
245 * @edev_self: represent the source of extcon.
246 * @edev: extcon device for notification registration
247 * @phy_cfg: phy register configuration, assigned by driver data.
248 * @ports: phy port instance.
250 struct rockchip_usb2phy {
255 struct clk_hw clk480m_hw;
256 enum usb_chg_state chg_state;
257 enum power_supply_type chg_type;
261 struct extcon_dev *edev;
262 const struct rockchip_usb2phy_cfg *phy_cfg;
263 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
266 static inline int property_enable(struct rockchip_usb2phy *rphy,
267 const struct usb2phy_reg *reg, bool en)
269 unsigned int val, mask, tmp;
271 tmp = en ? reg->enable : reg->disable;
272 mask = GENMASK(reg->bitend, reg->bitstart);
273 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
275 return regmap_write(rphy->grf, reg->offset, val);
278 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
279 const struct usb2phy_reg *reg)
282 unsigned int tmp, orig;
283 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
285 ret = regmap_read(rphy->grf, reg->offset, &orig);
289 tmp = (orig & mask) >> reg->bitstart;
290 return tmp == reg->enable;
293 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
295 struct rockchip_usb2phy *rphy =
296 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
299 /* turn on 480m clk output if it is off */
300 if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
301 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
305 /* waiting for the clk become stable */
306 usleep_range(1200, 1300);
312 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
314 struct rockchip_usb2phy *rphy =
315 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
317 /* turn off 480m clk output */
318 property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
321 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
323 struct rockchip_usb2phy *rphy =
324 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
326 return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
330 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
331 unsigned long parent_rate)
336 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
337 .prepare = rockchip_usb2phy_clk480m_prepare,
338 .unprepare = rockchip_usb2phy_clk480m_unprepare,
339 .is_prepared = rockchip_usb2phy_clk480m_prepared,
340 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
343 static void rockchip_usb2phy_clk480m_unregister(void *data)
345 struct rockchip_usb2phy *rphy = data;
347 of_clk_del_provider(rphy->dev->of_node);
348 clk_unregister(rphy->clk480m);
352 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
354 struct device_node *node = rphy->dev->of_node;
355 struct clk_init_data init;
356 const char *clk_name;
360 init.name = "clk_usbphy_480m";
361 init.ops = &rockchip_usb2phy_clkout_ops;
363 /* optional override of the clockname */
364 of_property_read_string(node, "clock-output-names", &init.name);
367 clk_name = __clk_get_name(rphy->clk);
368 init.parent_names = &clk_name;
369 init.num_parents = 1;
371 init.parent_names = NULL;
372 init.num_parents = 0;
375 rphy->clk480m_hw.init = &init;
377 /* register the clock */
378 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
379 if (IS_ERR(rphy->clk480m)) {
380 ret = PTR_ERR(rphy->clk480m);
384 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
386 goto err_clk_provider;
388 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
391 goto err_unreg_action;
396 of_clk_del_provider(node);
398 clk_unregister(rphy->clk480m);
403 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
406 struct device_node *node = rphy->dev->of_node;
407 struct extcon_dev *edev;
409 if (of_property_read_bool(node, "extcon")) {
410 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
412 if (PTR_ERR(edev) != -EPROBE_DEFER)
413 dev_err(rphy->dev, "Invalid or missing extcon\n");
414 return PTR_ERR(edev);
417 /* Initialize extcon device */
418 edev = devm_extcon_dev_allocate(rphy->dev,
419 rockchip_usb2phy_extcon_cable);
424 ret = devm_extcon_dev_register(rphy->dev, edev);
426 dev_err(rphy->dev, "failed to register extcon device\n");
430 rphy->edev_self = true;
438 static int rockchip_usb2phy_init(struct phy *phy)
440 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
441 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
444 mutex_lock(&rport->mutex);
446 if (rport->port_id == USB2PHY_PORT_OTG) {
447 if (rport->mode != USB_DR_MODE_HOST &&
448 !rport->vbus_always_on) {
449 /* clear bvalid status and enable bvalid detect irq */
450 ret = property_enable(rphy,
457 ret = property_enable(rphy,
464 if (rphy->edev_self) {
465 ret = property_enable(rphy,
472 ret = property_enable(rphy,
479 ret = property_enable(rphy,
486 ret = property_enable(rphy,
494 schedule_delayed_work(&rport->otg_sm_work,
497 /* If OTG works in host only mode, do nothing. */
498 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
500 } else if (rport->port_id == USB2PHY_PORT_HOST) {
501 /* clear linestate and enable linestate detect irq */
502 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
506 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
510 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
514 mutex_unlock(&rport->mutex);
518 static int rockchip_usb2phy_power_on(struct phy *phy)
520 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
521 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
524 dev_dbg(&rport->phy->dev, "port power on\n");
526 if (!rport->suspended)
529 ret = clk_prepare_enable(rphy->clk480m);
533 ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
537 rport->suspended = false;
541 static int rockchip_usb2phy_power_off(struct phy *phy)
543 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
544 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
547 dev_dbg(&rport->phy->dev, "port power off\n");
549 if (rport->suspended)
552 ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
556 rport->suspended = true;
557 clk_disable_unprepare(rphy->clk480m);
562 static int rockchip_usb2phy_exit(struct phy *phy)
564 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
566 if (rport->port_id == USB2PHY_PORT_OTG &&
567 rport->mode != USB_DR_MODE_HOST &&
568 !rport->vbus_always_on)
569 cancel_delayed_work_sync(&rport->chg_work);
570 else if (rport->port_id == USB2PHY_PORT_HOST)
571 cancel_delayed_work_sync(&rport->sm_work);
576 static int rockchip_usb2phy_set_mode(struct phy *phy, enum phy_mode mode)
578 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
579 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
583 if (rport->port_id != USB2PHY_PORT_OTG ||
584 !rport->vbus_always_on)
588 case PHY_MODE_USB_OTG:
590 * In case of using vbus to detect connect state by u2phy,
591 * enable vbus detect on otg mode.
595 case PHY_MODE_USB_DEVICE:
598 case PHY_MODE_USB_HOST:
600 case PHY_MODE_INVALID:
604 dev_info(&rport->phy->dev, "illegal mode\n");
608 ret = property_enable(rphy, &rport->port_cfg->vbus_det_en, vbus_det_en);
612 static const struct phy_ops rockchip_usb2phy_ops = {
613 .init = rockchip_usb2phy_init,
614 .exit = rockchip_usb2phy_exit,
615 .power_on = rockchip_usb2phy_power_on,
616 .power_off = rockchip_usb2phy_power_off,
617 .set_mode = rockchip_usb2phy_set_mode,
618 .owner = THIS_MODULE,
621 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
623 struct rockchip_usb2phy_port *rport =
624 container_of(work, struct rockchip_usb2phy_port,
626 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
627 static unsigned int cable;
631 if (rport->utmi_avalid)
632 rport->vbus_attached =
633 property_enabled(rphy, &rport->port_cfg->utmi_avalid);
635 rport->vbus_attached =
636 property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
639 delay = OTG_SCHEDULE_DELAY;
641 dev_dbg(&rport->phy->dev, "%s otg sm work\n",
642 usb_otg_state_string(rport->state));
644 switch (rport->state) {
645 case OTG_STATE_UNDEFINED:
646 rport->state = OTG_STATE_B_IDLE;
647 if (!rport->vbus_attached)
648 rockchip_usb2phy_power_off(rport->phy);
650 case OTG_STATE_B_IDLE:
651 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0 ||
652 extcon_get_cable_state_(rphy->edev,
653 EXTCON_USB_VBUS_EN) > 0) {
654 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
655 rport->state = OTG_STATE_A_HOST;
656 rockchip_usb2phy_power_on(rport->phy);
658 } else if (rport->vbus_attached) {
659 dev_dbg(&rport->phy->dev, "vbus_attach\n");
660 switch (rphy->chg_state) {
661 case USB_CHG_STATE_UNDEFINED:
662 schedule_delayed_work(&rport->chg_work, 0);
664 case USB_CHG_STATE_DETECTED:
665 switch (rphy->chg_type) {
666 case POWER_SUPPLY_TYPE_USB:
667 dev_dbg(&rport->phy->dev,
668 "sdp cable is connecetd\n");
669 wake_lock(&rport->wakelock);
670 cable = EXTCON_CHG_USB_SDP;
671 rockchip_usb2phy_power_on(rport->phy);
672 rport->state = OTG_STATE_B_PERIPHERAL;
673 rport->perip_connected = true;
676 case POWER_SUPPLY_TYPE_USB_DCP:
677 dev_dbg(&rport->phy->dev,
678 "dcp cable is connecetd\n");
679 cable = EXTCON_CHG_USB_DCP;
680 rockchip_usb2phy_power_off(rport->phy);
683 case POWER_SUPPLY_TYPE_USB_CDP:
684 dev_dbg(&rport->phy->dev,
685 "cdp cable is connecetd\n");
686 wake_lock(&rport->wakelock);
687 cable = EXTCON_CHG_USB_CDP;
688 rockchip_usb2phy_power_on(rport->phy);
689 rport->state = OTG_STATE_B_PERIPHERAL;
690 rport->perip_connected = true;
693 case POWER_SUPPLY_TYPE_USB_FLOATING:
694 dev_dbg(&rport->phy->dev,
695 "floating cable is connecetd\n");
696 cable = EXTCON_CHG_USB_DCP;
697 rockchip_usb2phy_power_off(rport->phy);
708 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
709 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
712 case OTG_STATE_B_PERIPHERAL:
713 if (!rport->vbus_attached) {
714 dev_dbg(&rport->phy->dev, "usb disconnect\n");
715 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
716 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
717 rport->state = OTG_STATE_B_IDLE;
718 rport->perip_connected = false;
720 rockchip_usb2phy_power_off(rport->phy);
721 wake_unlock(&rport->wakelock);
726 case OTG_STATE_A_HOST:
727 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
728 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
729 rport->state = OTG_STATE_B_IDLE;
730 rockchip_usb2phy_power_off(rport->phy);
737 if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached)
738 extcon_set_cable_state_(rphy->edev,
739 cable, rport->vbus_attached);
741 if (rphy->edev_self &&
742 (extcon_get_state(rphy->edev, EXTCON_USB) !=
743 rport->perip_connected))
744 extcon_set_cable_state_(rphy->edev,
746 rport->perip_connected);
749 schedule_delayed_work(&rport->otg_sm_work, delay);
752 static const char *chg_to_string(enum power_supply_type chg_type)
755 case POWER_SUPPLY_TYPE_USB:
756 return "USB_SDP_CHARGER";
757 case POWER_SUPPLY_TYPE_USB_DCP:
758 return "USB_DCP_CHARGER";
759 case POWER_SUPPLY_TYPE_USB_CDP:
760 return "USB_CDP_CHARGER";
761 case POWER_SUPPLY_TYPE_USB_FLOATING:
762 return "USB_FLOATING_CHARGER";
764 return "INVALID_CHARGER";
768 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
771 property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
772 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
775 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
778 property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
779 property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
782 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
785 property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
786 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
789 #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
790 #define CHG_DCD_MAX_RETRIES 6
791 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
792 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
793 static void rockchip_chg_detect_work(struct work_struct *work)
795 struct rockchip_usb2phy_port *rport =
796 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
797 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
798 bool is_dcd, tmout, vout;
801 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
803 switch (rphy->chg_state) {
804 case USB_CHG_STATE_UNDEFINED:
805 if (!rport->suspended)
806 rockchip_usb2phy_power_off(rport->phy);
807 /* put the controller in non-driving mode */
808 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
809 /* Start DCD processing stage 1 */
810 rockchip_chg_enable_dcd(rphy, true);
811 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
812 rphy->dcd_retries = 0;
813 rphy->primary_retries = 0;
814 delay = CHG_DCD_POLL_TIME;
816 case USB_CHG_STATE_WAIT_FOR_DCD:
817 /* get data contact detection status */
818 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
819 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
821 if (is_dcd || tmout) {
823 /* Turn off DCD circuitry */
824 rockchip_chg_enable_dcd(rphy, false);
825 /* Voltage Source on DP, Probe on DM */
826 rockchip_chg_enable_primary_det(rphy, true);
827 delay = CHG_PRIMARY_DET_TIME;
828 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
831 delay = CHG_DCD_POLL_TIME;
834 case USB_CHG_STATE_DCD_DONE:
835 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
836 rockchip_chg_enable_primary_det(rphy, false);
838 /* Voltage Source on DM, Probe on DP */
839 rockchip_chg_enable_secondary_det(rphy, true);
840 delay = CHG_SECONDARY_DET_TIME;
841 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
843 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
844 /* floating charger found */
845 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
846 rphy->chg_state = USB_CHG_STATE_DETECTED;
849 if (rphy->primary_retries < 2) {
850 /* Turn off DCD circuitry */
851 rockchip_chg_enable_dcd(rphy, false);
852 /* Voltage Source on DP, Probe on DM */
853 rockchip_chg_enable_primary_det(rphy,
855 delay = CHG_PRIMARY_DET_TIME;
857 USB_CHG_STATE_DCD_DONE;
858 rphy->primary_retries++;
859 /* break USB_CHG_STATE_DCD_DONE */
862 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
863 rphy->chg_state = USB_CHG_STATE_DETECTED;
868 case USB_CHG_STATE_PRIMARY_DONE:
869 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
870 /* Turn off voltage source */
871 rockchip_chg_enable_secondary_det(rphy, false);
873 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
875 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
877 case USB_CHG_STATE_SECONDARY_DONE:
878 rphy->chg_state = USB_CHG_STATE_DETECTED;
881 case USB_CHG_STATE_DETECTED:
882 /* put the controller in normal mode */
883 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
884 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
885 dev_info(&rport->phy->dev, "charger = %s\n",
886 chg_to_string(rphy->chg_type));
892 schedule_delayed_work(&rport->chg_work, delay);
896 * The function manage host-phy port state and suspend/resume phy port
899 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
900 * devices is disconnect or not. Besides, we do not need care it is FS/LS
901 * disconnected or HS disconnected, actually, we just only need get the
902 * device is disconnected at last through rearm the delayed work,
903 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
905 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
906 * some clk related APIs, so do not invoke it from interrupt context directly.
908 static void rockchip_usb2phy_sm_work(struct work_struct *work)
910 struct rockchip_usb2phy_port *rport =
911 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
912 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
913 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
914 rport->port_cfg->utmi_hstdet.bitstart + 1;
915 unsigned int ul, uhd, state;
916 unsigned int ul_mask, uhd_mask;
919 if (!rport->port_cfg->utmi_ls.offset ||
920 !rport->port_cfg->utmi_hstdet.offset) {
921 dev_dbg(&rport->phy->dev, "some property may not be specified\n");
925 mutex_lock(&rport->mutex);
927 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
931 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
936 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
937 rport->port_cfg->utmi_hstdet.bitstart);
938 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
939 rport->port_cfg->utmi_ls.bitstart);
941 /* stitch on utmi_ls and utmi_hstdet as phy state */
942 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
943 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
946 case PHY_STATE_HS_ONLINE:
947 dev_dbg(&rport->phy->dev, "HS online\n");
949 case PHY_STATE_FS_LS_ONLINE:
951 * For FS/LS device, the online state share with connect state
952 * from utmi_ls and utmi_hstdet register, so we distinguish
953 * them via suspended flag.
955 * Plus, there are two cases, one is D- Line pull-up, and D+
956 * line pull-down, the state is 4; another is D+ line pull-up,
957 * and D- line pull-down, the state is 2.
959 if (!rport->suspended) {
960 /* D- line pull-up, D+ line pull-down */
961 dev_dbg(&rport->phy->dev, "FS/LS online\n");
965 case PHY_STATE_CONNECT:
966 if (rport->suspended) {
967 dev_dbg(&rport->phy->dev, "Connected\n");
968 rockchip_usb2phy_power_on(rport->phy);
969 rport->suspended = false;
971 /* D+ line pull-up, D- line pull-down */
972 dev_dbg(&rport->phy->dev, "FS/LS online\n");
975 case PHY_STATE_DISCONNECT:
976 if (!rport->suspended) {
977 dev_dbg(&rport->phy->dev, "Disconnected\n");
978 rockchip_usb2phy_power_off(rport->phy);
979 rport->suspended = true;
983 * activate the linestate detection to get the next device
986 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
987 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
990 * we don't need to rearm the delayed work when the phy port
993 mutex_unlock(&rport->mutex);
996 dev_dbg(&rport->phy->dev, "unknown phy state\n");
1001 mutex_unlock(&rport->mutex);
1002 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
1005 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
1007 struct rockchip_usb2phy_port *rport = data;
1008 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1010 if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
1013 dev_dbg(&rport->phy->dev, "linestate interrupt\n");
1015 mutex_lock(&rport->mutex);
1017 /* disable linestate detect irq and clear its status */
1018 property_enable(rphy, &rport->port_cfg->ls_det_en, false);
1019 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
1021 mutex_unlock(&rport->mutex);
1024 * In this case for host phy port, a new device is plugged in,
1025 * meanwhile, if the phy port is suspended, we need rearm the work to
1026 * resume it and mange its states; otherwise, we do nothing about that.
1028 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
1029 rockchip_usb2phy_sm_work(&rport->sm_work.work);
1034 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
1036 struct rockchip_usb2phy_port *rport = data;
1037 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1039 if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
1042 mutex_lock(&rport->mutex);
1044 /* clear bvalid detect irq pending status */
1045 property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
1047 mutex_unlock(&rport->mutex);
1049 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1054 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1056 struct rockchip_usb2phy_port *rport = data;
1057 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1058 bool cable_vbus_state;
1060 if (!property_enabled(rphy, &rport->port_cfg->idfall_det_st) &&
1061 !property_enabled(rphy, &rport->port_cfg->idrise_det_st))
1064 mutex_lock(&rport->mutex);
1066 /* clear id fall or rise detect irq pending status */
1067 if (property_enabled(rphy, &rport->port_cfg->idfall_det_st)) {
1068 property_enable(rphy, &rport->port_cfg->idfall_det_clr,
1070 cable_vbus_state = true;
1071 } else if (property_enabled(rphy, &rport->port_cfg->idrise_det_st)) {
1072 property_enable(rphy, &rport->port_cfg->idrise_det_clr,
1074 cable_vbus_state = false;
1077 extcon_set_state(rphy->edev, EXTCON_USB_HOST, cable_vbus_state);
1078 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, cable_vbus_state);
1080 extcon_sync(rphy->edev, EXTCON_USB_HOST);
1081 extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
1082 gpiod_set_value_cansleep(rport->vbus_drv_gpio,
1083 cable_vbus_state ? 1 : 0);
1085 mutex_unlock(&rport->mutex);
1090 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1091 struct rockchip_usb2phy_port *rport,
1092 struct device_node *child_np)
1096 rport->port_id = USB2PHY_PORT_HOST;
1097 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1098 rport->suspended = true;
1100 mutex_init(&rport->mutex);
1101 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1103 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1104 if (rport->ls_irq < 0) {
1105 dev_err(rphy->dev, "no linestate irq provided\n");
1106 return rport->ls_irq;
1109 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1110 rockchip_usb2phy_linestate_irq,
1112 "rockchip_usb2phy", rport);
1114 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1121 static int rockchip_otg_event(struct notifier_block *nb,
1122 unsigned long event, void *ptr)
1124 struct rockchip_usb2phy_port *rport =
1125 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1127 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1132 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1133 struct rockchip_usb2phy_port *rport,
1134 struct device_node *child_np)
1139 rport->port_id = USB2PHY_PORT_OTG;
1140 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1141 rport->state = OTG_STATE_UNDEFINED;
1144 * set suspended flag to true, but actually don't
1145 * put phy in suspend mode, it aims to enable usb
1146 * phy and clock in power_on() called by usb controller
1147 * driver during probe.
1149 rport->suspended = true;
1150 rport->vbus_attached = false;
1151 rport->perip_connected = false;
1153 mutex_init(&rport->mutex);
1155 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1156 if (rport->ls_irq < 0) {
1157 dev_err(rphy->dev, "no linestate irq provided\n");
1158 return rport->ls_irq;
1161 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1162 rockchip_usb2phy_linestate_irq,
1164 "rockchip_usb2phy", rport);
1166 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1170 rport->vbus_drv_gpio = devm_gpiod_get_optional(rphy->dev, "otg-vbus",
1172 if (!rport->vbus_drv_gpio) {
1173 dev_warn(rphy->dev, "vbus_drv is not assigned\n");
1174 } else if (IS_ERR(rport->vbus_drv_gpio)) {
1175 dev_err(rphy->dev, "failed to get vbus_drv\n");
1176 return PTR_ERR(rport->vbus_drv_gpio);
1179 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1180 if (rport->mode == USB_DR_MODE_HOST) {
1181 if (rphy->edev_self) {
1182 extcon_set_state(rphy->edev, EXTCON_USB, false);
1183 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1184 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1185 gpiod_set_value_cansleep(rport->vbus_drv_gpio, 1);
1190 rport->vbus_always_on =
1191 of_property_read_bool(child_np, "rockchip,vbus-always-on");
1192 if (rport->vbus_always_on)
1195 wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
1196 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1197 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1199 rport->utmi_avalid =
1200 of_property_read_bool(child_np, "rockchip,utmi-avalid");
1202 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1203 if (rport->bvalid_irq < 0) {
1204 dev_err(rphy->dev, "no vbus valid irq provided\n");
1205 return rport->bvalid_irq;
1208 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
1209 rockchip_usb2phy_bvalid_irq,
1211 "rockchip_usb2phy_bvalid", rport);
1213 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1217 if (rphy->edev_self) {
1218 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1219 if (rport->id_irq < 0) {
1220 dev_err(rphy->dev, "no otg id irq provided\n");
1221 return rport->id_irq;
1224 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, NULL,
1225 rockchip_usb2phy_id_irq,
1227 "rockchip_usb2phy_id", rport);
1229 dev_err(rphy->dev, "failed to request otg-id irq handle\n");
1233 iddig = property_enabled(rphy, &rport->port_cfg->utmi_iddig);
1235 extcon_set_state(rphy->edev, EXTCON_USB, false);
1236 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1237 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1238 gpiod_set_value_cansleep(rport->vbus_drv_gpio, 1);
1240 extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1241 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1242 gpiod_set_value_cansleep(rport->vbus_drv_gpio, 0);
1246 if (!IS_ERR(rphy->edev)) {
1247 rport->event_nb.notifier_call = rockchip_otg_event;
1249 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1252 dev_err(rphy->dev, "register USB HOST notifier failed\n");
1260 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1262 struct device *dev = &pdev->dev;
1263 struct device_node *np = dev->of_node;
1264 struct device_node *child_np;
1265 struct phy_provider *provider;
1266 struct rockchip_usb2phy *rphy;
1267 const struct rockchip_usb2phy_cfg *phy_cfgs;
1268 const struct of_device_id *match;
1272 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1276 match = of_match_device(dev->driver->of_match_table, dev);
1277 if (!match || !match->data) {
1278 dev_err(dev, "phy configs are not assigned!\n");
1282 if (!dev->parent || !dev->parent->of_node)
1285 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1286 if (IS_ERR(rphy->grf))
1287 return PTR_ERR(rphy->grf);
1289 if (of_property_read_u32(np, "reg", ®)) {
1290 dev_err(dev, "the reg property is not assigned in %s node\n",
1296 phy_cfgs = match->data;
1297 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1298 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1299 rphy->edev_self = false;
1300 platform_set_drvdata(pdev, rphy);
1302 ret = rockchip_usb2phy_extcon_register(rphy);
1306 /* find out a proper config which can be matched with dt. */
1308 while (phy_cfgs[index].reg) {
1309 if (phy_cfgs[index].reg == reg) {
1310 rphy->phy_cfg = &phy_cfgs[index];
1317 if (!rphy->phy_cfg) {
1318 dev_err(dev, "no phy-config can be matched with %s node\n",
1323 rphy->clk = of_clk_get_by_name(np, "phyclk");
1324 if (!IS_ERR(rphy->clk)) {
1325 clk_prepare_enable(rphy->clk);
1327 dev_info(&pdev->dev, "no phyclk specified\n");
1331 ret = rockchip_usb2phy_clk480m_register(rphy);
1333 dev_err(dev, "failed to register 480m output clock\n");
1337 if (rphy->phy_cfg->phy_tuning) {
1338 ret = rphy->phy_cfg->phy_tuning(rphy);
1344 for_each_available_child_of_node(np, child_np) {
1345 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1348 /* This driver aims to support both otg-port and host-port */
1349 if (of_node_cmp(child_np->name, "host-port") &&
1350 of_node_cmp(child_np->name, "otg-port"))
1353 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1355 dev_err(dev, "failed to create phy\n");
1361 phy_set_drvdata(rport->phy, rport);
1363 /* initialize otg/host port separately */
1364 if (!of_node_cmp(child_np->name, "host-port")) {
1365 ret = rockchip_usb2phy_host_port_init(rphy, rport,
1370 ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1377 /* to prevent out of boundary */
1378 if (++index >= rphy->phy_cfg->num_ports)
1382 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1383 return PTR_ERR_OR_ZERO(provider);
1386 of_node_put(child_np);
1389 clk_disable_unprepare(rphy->clk);
1395 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1399 /* Open debug mode for tuning */
1400 ret = regmap_write(rphy->grf, 0x2c, 0xffff0400);
1405 * Open HS pre-emphasize function to increase
1406 * HS slew rate for host port
1408 ret = regmap_write(rphy->grf, 0x30, 0xffff851d);
1415 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1417 unsigned int open_pre_emphasize = 0xffff851f;
1418 unsigned int eye_height_tuning = 0xffff68c8;
1419 unsigned int compensation_tuning = 0xffff026e;
1422 /* open HS pre-emphasize to expand HS slew rate for each port. */
1423 ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1424 ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1425 ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1426 ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1428 /* compensate default tuning reference relate to ODT and etc. */
1429 ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1434 static int rk3399_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1436 struct device_node *node = rphy->dev->of_node;
1439 if (!of_property_read_bool(node, "rockchip,u2phy-tuning"))
1442 if (rphy->phy_cfg->reg == 0xe450) {
1444 * Set max ODT compensation voltage and
1445 * current tuning reference for PHY0.
1447 ret |= regmap_write(rphy->grf, 0x448c,
1448 GENMASK(23, 16) | 0xe3);
1450 /* Set max pre-emphasis level for PHY0 */
1451 ret |= regmap_write(rphy->grf, 0x44b0,
1452 GENMASK(18, 16) | 0x07);
1455 * Disable the pre-emphasize in eop state
1456 * and chirp state to avoid mis-trigger the
1457 * disconnect detection and also avoid hs
1458 * handshake fail for PHY0.
1460 ret |= regmap_write(rphy->grf, 0x4480,
1461 GENMASK(17, 16) | 0x0);
1462 ret |= regmap_write(rphy->grf, 0x44b4,
1463 GENMASK(17, 16) | 0x0);
1466 * Set max ODT compensation voltage and
1467 * current tuning reference for PHY1.
1469 ret |= regmap_write(rphy->grf, 0x450c,
1470 GENMASK(23, 16) | 0xe3);
1472 /* Set max pre-emphasis level for PHY1 */
1473 ret |= regmap_write(rphy->grf, 0x4530,
1474 GENMASK(18, 16) | 0x07);
1477 * Disable the pre-emphasize in eop state
1478 * and chirp state to avoid mis-trigger the
1479 * disconnect detection and also avoid hs
1480 * handshake fail for PHY1.
1482 ret |= regmap_write(rphy->grf, 0x4500,
1483 GENMASK(17, 16) | 0x0);
1484 ret |= regmap_write(rphy->grf, 0x4534,
1485 GENMASK(17, 16) | 0x0);
1491 #ifdef CONFIG_PM_SLEEP
1492 static int rockchip_usb2phy_pm_suspend(struct device *dev)
1494 struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
1495 struct rockchip_usb2phy_port *rport;
1498 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1499 rport = &rphy->ports[index];
1503 /* activate the linestate to detect the next interrupt. */
1504 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
1505 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
1511 static int rockchip_usb2phy_pm_resume(struct device *dev)
1516 static const struct dev_pm_ops rockchip_usb2phy_dev_pm_ops = {
1517 SET_SYSTEM_SLEEP_PM_OPS(rockchip_usb2phy_pm_suspend,
1518 rockchip_usb2phy_pm_resume)
1521 #define ROCKCHIP_USB2PHY_DEV_PM (&rockchip_usb2phy_dev_pm_ops)
1523 #define ROCKCHIP_USB2PHY_DEV_PM NULL
1524 #endif /* CONFIG_PM_SLEEP */
1526 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1530 .phy_tuning = rk3328_usb2phy_tuning,
1531 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1533 [USB2PHY_PORT_OTG] = {
1534 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
1535 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1536 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1537 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1538 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
1539 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
1540 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1541 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
1542 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
1543 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1544 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1545 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1546 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1547 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1548 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1549 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1550 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1552 [USB2PHY_PORT_HOST] = {
1553 .phy_sus = { 0x104, 15, 0, 0, 0x1d1 },
1554 .ls_det_en = { 0x110, 1, 1, 0, 1 },
1555 .ls_det_st = { 0x114, 1, 1, 0, 1 },
1556 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
1557 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1558 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1562 .opmode = { 0x0100, 3, 0, 5, 1 },
1563 .cp_det = { 0x0120, 24, 24, 0, 1 },
1564 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1565 .dp_det = { 0x0120, 25, 25, 0, 1 },
1566 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1567 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1568 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1569 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1570 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1571 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1577 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1581 .phy_tuning = rk3366_usb2phy_tuning,
1582 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1584 [USB2PHY_PORT_HOST] = {
1585 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
1586 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1587 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1588 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1589 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
1590 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
1597 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = {
1601 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1603 [USB2PHY_PORT_HOST] = {
1604 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
1605 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1606 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1607 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1614 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1618 .phy_tuning = rk3399_usb2phy_tuning,
1619 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1621 [USB2PHY_PORT_OTG] = {
1622 .phy_sus = { 0xe454, 15, 0, 0x1452, 0x15d1 },
1623 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1624 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1625 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1626 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 },
1627 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 },
1628 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1629 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 },
1630 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 },
1631 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1632 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 },
1633 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 },
1634 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 },
1635 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1636 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1637 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 },
1638 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 },
1639 .vbus_det_en = { 0x449c, 15, 15, 1, 0 },
1641 [USB2PHY_PORT_HOST] = {
1642 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1643 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1644 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1645 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1646 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1647 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1651 .opmode = { 0xe454, 3, 0, 5, 1 },
1652 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1653 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1654 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1655 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1656 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1657 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1658 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1659 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1660 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1666 .phy_tuning = rk3399_usb2phy_tuning,
1667 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1669 [USB2PHY_PORT_OTG] = {
1670 .phy_sus = { 0xe464, 15, 0, 0x1452, 0x15d1 },
1671 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1672 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1673 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1674 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 },
1675 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 },
1676 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1677 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 },
1678 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 },
1679 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1680 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 },
1681 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 },
1682 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 },
1683 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1684 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1685 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 },
1686 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 },
1687 .vbus_det_en = { 0x451c, 15, 15, 1, 0 },
1689 [USB2PHY_PORT_HOST] = {
1690 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1691 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1692 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1693 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1694 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1695 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1702 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1703 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1704 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1705 { .compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs },
1706 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1709 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1711 static struct platform_driver rockchip_usb2phy_driver = {
1712 .probe = rockchip_usb2phy_probe,
1714 .name = "rockchip-usb2phy",
1715 .pm = ROCKCHIP_USB2PHY_DEV_PM,
1716 .of_match_table = rockchip_usb2phy_dt_match,
1719 module_platform_driver(rockchip_usb2phy_driver);
1721 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1722 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1723 MODULE_LICENSE("GPL v2");