2 * Rockchip usb PHY driver
4 * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
5 * Copyright (C) 2014 ROCKCHIP, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/mutex.h>
25 #include <linux/of_address.h>
26 #include <linux/of_platform.h>
27 #include <linux/phy/phy.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/reset.h>
31 #include <linux/regmap.h>
32 #include <linux/mfd/syscon.h>
35 * The higher 16-bit of this register is used for write protection
36 * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
38 #define SIDDQ_WRITE_ENA BIT(29)
39 #define SIDDQ_ON BIT(13)
40 #define SIDDQ_OFF (0 << 13)
42 #define USB2_PHY_WRITE_ENA (0xffff << 16)
43 #define USB2_PHY_SUSPEND (0x5 << 0 | 0xd << 4 | 0x1 << 8)
44 #define USB2_PHY_RESUME (0)
46 #define UTMI_SEL_GRF_WR_ENA (0x3 << 16)
47 #define UTMI_SEL_GRF_SUSPEND (0x1 << 0)
48 #define UTMI_SEL_GRF_RESUME (0x2 << 0)
50 struct rockchip_usb_phys {
55 struct rockchip_usb_phy_pdata {
56 struct rockchip_usb_phys *phys;
57 unsigned int phy_pw_on;
58 unsigned int phy_pw_off;
62 struct rockchip_usb_phy_base {
64 struct regmap *reg_base;
65 struct gpio_desc *vbus_drv_gpio;
66 const struct rockchip_usb_phy_pdata *pdata;
69 struct rockchip_usb_phy {
70 struct rockchip_usb_phy_base *base;
71 struct device_node *np;
72 unsigned int reg_offset;
75 struct clk_hw clk480m_hw;
79 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
84 val = !off ? phy->base->pdata->phy_pw_on : phy->base->pdata->phy_pw_off;
85 return regmap_write(phy->base->reg_base, phy->reg_offset, val);
88 static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
89 unsigned long parent_rate)
94 static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
96 struct rockchip_usb_phy *phy = container_of(hw,
97 struct rockchip_usb_phy,
100 /* Power down usb phy analog blocks by set siddq 1 */
101 if (phy->base->pdata->siddq_ctl)
102 rockchip_usb_phy_power(phy, 1);
105 static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
108 struct rockchip_usb_phy *phy = container_of(hw,
109 struct rockchip_usb_phy,
112 /* Power up usb phy analog blocks by set siddq 0 */
113 if (phy->base->pdata->siddq_ctl)
114 ret = rockchip_usb_phy_power(phy, 0);
119 static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
121 struct rockchip_usb_phy *phy = container_of(hw,
122 struct rockchip_usb_phy,
127 if (phy->base->pdata->siddq_ctl) {
128 ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
132 ret = (val & SIDDQ_ON) ? 0 : 1;
138 static const struct clk_ops rockchip_usb_phy480m_ops = {
139 .enable = rockchip_usb_phy480m_enable,
140 .disable = rockchip_usb_phy480m_disable,
141 .is_enabled = rockchip_usb_phy480m_is_enabled,
142 .recalc_rate = rockchip_usb_phy480m_recalc_rate,
145 static int rockchip_usb_phy_power_off(struct phy *_phy)
148 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
150 if (!phy->base->pdata->siddq_ctl) {
151 ret = rockchip_usb_phy_power(phy, 1);
156 clk_disable_unprepare(phy->clk480m);
160 static int rockchip_usb_phy_power_on(struct phy *_phy)
163 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
165 ret = clk_prepare_enable(phy->clk480m);
169 if (!phy->base->pdata->siddq_ctl)
170 ret = rockchip_usb_phy_power(phy, 0);
175 static const struct phy_ops ops = {
176 .power_on = rockchip_usb_phy_power_on,
177 .power_off = rockchip_usb_phy_power_off,
178 .owner = THIS_MODULE,
181 static void rockchip_usb_phy_action(void *data)
183 struct rockchip_usb_phy *rk_phy = data;
185 of_clk_del_provider(rk_phy->np);
186 clk_unregister(rk_phy->clk480m);
189 clk_put(rk_phy->clk);
192 static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
193 struct device_node *child)
195 struct rockchip_usb_phy *rk_phy;
196 unsigned int reg_offset;
197 const char *clk_name;
198 struct clk_init_data init;
201 rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
208 if (of_property_read_u32(child, "reg", ®_offset)) {
209 dev_err(base->dev, "missing reg property in node %s\n",
214 rk_phy->reg_offset = reg_offset;
216 rk_phy->clk = of_clk_get_by_name(child, "phyclk");
217 if (IS_ERR(rk_phy->clk))
222 while (base->pdata->phys[i].reg) {
223 if (base->pdata->phys[i].reg == reg_offset) {
224 init.name = base->pdata->phys[i].pll_name;
231 dev_err(base->dev, "phy data not found\n");
236 clk_name = __clk_get_name(rk_phy->clk);
238 init.parent_names = &clk_name;
239 init.num_parents = 1;
241 init.flags = CLK_IS_ROOT;
242 init.parent_names = NULL;
243 init.num_parents = 0;
246 init.ops = &rockchip_usb_phy480m_ops;
247 rk_phy->clk480m_hw.init = &init;
249 rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
250 if (IS_ERR(rk_phy->clk480m)) {
251 err = PTR_ERR(rk_phy->clk480m);
255 err = of_clk_add_provider(child, of_clk_src_simple_get,
260 err = devm_add_action(base->dev, rockchip_usb_phy_action, rk_phy);
262 goto err_devm_action;
264 rk_phy->phy = devm_phy_create(base->dev, child, &ops);
265 if (IS_ERR(rk_phy->phy)) {
266 dev_err(base->dev, "failed to create PHY\n");
267 return PTR_ERR(rk_phy->phy);
269 phy_set_drvdata(rk_phy->phy, rk_phy);
271 /* only power up usb phy when it use, so disable it when init*/
272 return rockchip_usb_phy_power(rk_phy, 1);
275 of_clk_del_provider(child);
277 clk_unregister(rk_phy->clk480m);
280 clk_put(rk_phy->clk);
284 static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
285 .phys = (struct rockchip_usb_phys[]){
286 { .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
287 { .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
290 .phy_pw_on = SIDDQ_WRITE_ENA | SIDDQ_OFF,
291 .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
295 static const struct rockchip_usb_phy_pdata rk3188_pdata = {
296 .phys = (struct rockchip_usb_phys[]){
297 { .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
298 { .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
301 .phy_pw_on = SIDDQ_WRITE_ENA | SIDDQ_OFF,
302 .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
306 static const struct rockchip_usb_phy_pdata rk3288_pdata = {
307 .phys = (struct rockchip_usb_phys[]){
308 { .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
309 { .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
310 { .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
313 .phy_pw_on = SIDDQ_WRITE_ENA | SIDDQ_OFF,
314 .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
318 static const struct rockchip_usb_phy_pdata rk336x_pdata = {
319 .phys = (struct rockchip_usb_phys[]){
320 { .reg = 0x700, .pll_name = "sclk_otgphy0_480m" },
321 { .reg = 0x728, .pll_name = "sclk_otgphy1_480m" },
324 .phy_pw_on = USB2_PHY_WRITE_ENA | USB2_PHY_RESUME,
325 .phy_pw_off = USB2_PHY_WRITE_ENA | USB2_PHY_SUSPEND,
329 static const struct rockchip_usb_phy_pdata rk3399_pdata = {
330 .phys = (struct rockchip_usb_phys[]){
331 { .reg = 0xe458, .pll_name = "sclk_otgphy0_480m" },
332 { .reg = 0xe468, .pll_name = "sclk_otgphy1_480m" },
335 .phy_pw_on = UTMI_SEL_GRF_WR_ENA | UTMI_SEL_GRF_RESUME,
336 .phy_pw_off = UTMI_SEL_GRF_WR_ENA | UTMI_SEL_GRF_SUSPEND,
340 static int rockchip_usb_phy_probe(struct platform_device *pdev)
342 struct device *dev = &pdev->dev;
343 struct rockchip_usb_phy_base *phy_base;
344 struct phy_provider *phy_provider;
345 const struct of_device_id *match;
346 struct device_node *child;
349 phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
353 match = of_match_device(dev->driver->of_match_table, dev);
354 if (!match || !match->data) {
355 dev_err(dev, "missing phy data\n");
359 phy_base->pdata = match->data;
362 phy_base->reg_base = syscon_regmap_lookup_by_phandle(dev->of_node,
364 if (IS_ERR(phy_base->reg_base)) {
365 dev_err(&pdev->dev, "Missing rockchip,grf property\n");
366 return PTR_ERR(phy_base->reg_base);
369 /* Request the vbus_drv GPIO asserted */
370 phy_base->vbus_drv_gpio =
371 devm_gpiod_get_optional(dev, "vbus_drv", GPIOD_OUT_HIGH);
372 if (!phy_base->vbus_drv_gpio)
373 dev_info(&pdev->dev, "vbus_drv is not assigned!\n");
374 else if (IS_ERR(phy_base->vbus_drv_gpio))
375 return PTR_ERR(phy_base->vbus_drv_gpio);
377 for_each_available_child_of_node(dev->of_node, child) {
378 err = rockchip_usb_phy_init(phy_base, child);
385 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
386 return PTR_ERR_OR_ZERO(phy_provider);
389 static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
390 { .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
391 { .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
392 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
393 { .compatible = "rockchip,rk336x-usb-phy", .data = &rk336x_pdata },
394 { .compatible = "rockchip,rk3399-usb-phy", .data = &rk3399_pdata },
398 MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
400 static struct platform_driver rockchip_usb_driver = {
401 .probe = rockchip_usb_phy_probe,
403 .name = "rockchip-usb-phy",
404 .of_match_table = rockchip_usb_phy_dt_ids,
408 module_platform_driver(rockchip_usb_driver);
410 MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
411 MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
412 MODULE_LICENSE("GPL v2");