2 * phy-ti-pipe3 - PIPE3 PHY driver.
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * Author: Kishon Vijay Abraham I <kishon@ti.com>
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/phy/phy.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/delay.h>
29 #include <linux/phy/omap_control_phy.h>
30 #include <linux/of_platform.h>
32 #define PLL_STATUS 0x00000004
33 #define PLL_GO 0x00000008
34 #define PLL_CONFIGURATION1 0x0000000C
35 #define PLL_CONFIGURATION2 0x00000010
36 #define PLL_CONFIGURATION3 0x00000014
37 #define PLL_CONFIGURATION4 0x00000020
39 #define PLL_REGM_MASK 0x001FFE00
40 #define PLL_REGM_SHIFT 0x9
41 #define PLL_REGM_F_MASK 0x0003FFFF
42 #define PLL_REGM_F_SHIFT 0x0
43 #define PLL_REGN_MASK 0x000001FE
44 #define PLL_REGN_SHIFT 0x1
45 #define PLL_SELFREQDCO_MASK 0x0000000E
46 #define PLL_SELFREQDCO_SHIFT 0x1
47 #define PLL_SD_MASK 0x0003FC00
48 #define PLL_SD_SHIFT 10
49 #define SET_PLL_GO 0x1
50 #define PLL_LDOPWDN BIT(15)
51 #define PLL_TICOPWDN BIT(16)
56 * This is an Empirical value that works, need to confirm the actual
57 * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
58 * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
60 #define PLL_IDLE_TIME 100 /* in milliseconds */
61 #define PLL_LOCK_TIME 100 /* in milliseconds */
63 struct pipe3_dpll_params {
71 struct pipe3_dpll_map {
73 struct pipe3_dpll_params params;
77 void __iomem *pll_ctrl_base;
79 struct device *control_dev;
84 struct pipe3_dpll_map *dpll_map;
87 static struct pipe3_dpll_map dpll_map_usb[] = {
88 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
89 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
90 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
91 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
92 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
93 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
97 static struct pipe3_dpll_map dpll_map_sata[] = {
98 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
99 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
100 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
101 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
102 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
103 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
104 { }, /* Terminator */
107 static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
109 return __raw_readl(addr + offset);
112 static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
115 __raw_writel(data, addr + offset);
118 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
121 struct pipe3_dpll_map *dpll_map = phy->dpll_map;
123 rate = clk_get_rate(phy->sys_clk);
125 for (; dpll_map->rate; dpll_map++) {
126 if (rate == dpll_map->rate)
127 return &dpll_map->params;
130 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
135 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
136 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
138 static int ti_pipe3_power_off(struct phy *x)
140 struct ti_pipe3 *phy = phy_get_drvdata(x);
142 omap_control_phy_power(phy->control_dev, 0);
147 static int ti_pipe3_power_on(struct phy *x)
149 struct ti_pipe3 *phy = phy_get_drvdata(x);
151 omap_control_phy_power(phy->control_dev, 1);
156 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
159 unsigned long timeout;
161 timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
164 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
167 } while (!time_after(jiffies, timeout));
169 dev_err(phy->dev, "DPLL failed to lock\n");
173 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
176 struct pipe3_dpll_params *dpll_params;
178 dpll_params = ti_pipe3_get_dpll_params(phy);
182 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
183 val &= ~PLL_REGN_MASK;
184 val |= dpll_params->n << PLL_REGN_SHIFT;
185 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
187 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
188 val &= ~PLL_SELFREQDCO_MASK;
189 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
190 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
192 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
193 val &= ~PLL_REGM_MASK;
194 val |= dpll_params->m << PLL_REGM_SHIFT;
195 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
197 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
198 val &= ~PLL_REGM_F_MASK;
199 val |= dpll_params->mf << PLL_REGM_F_SHIFT;
200 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
202 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
204 val |= dpll_params->sd << PLL_SD_SHIFT;
205 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
207 ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
209 return ti_pipe3_dpll_wait_lock(phy);
212 static int ti_pipe3_init(struct phy *x)
214 struct ti_pipe3 *phy = phy_get_drvdata(x);
218 ti_pipe3_enable_clocks(phy);
220 * Set pcie_pcs register to 0x96 for proper functioning of phy
221 * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
224 if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
225 omap_control_pcie_pcs(phy->control_dev, 0x96);
229 /* Bring it out of IDLE if it is IDLE */
230 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
231 if (val & PLL_IDLE) {
233 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
234 ret = ti_pipe3_dpll_wait_lock(phy);
237 /* Program the DPLL only if not locked */
238 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
239 if (!(val & PLL_LOCK))
240 if (ti_pipe3_dpll_program(phy))
246 static int ti_pipe3_exit(struct phy *x)
248 struct ti_pipe3 *phy = phy_get_drvdata(x);
250 unsigned long timeout;
252 /* SATA DPLL can't be powered down due to Errata i783 */
253 if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata"))
256 /* PCIe doesn't have internal DPLL */
257 if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
258 /* Put DPLL in IDLE mode */
259 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
261 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
263 /* wait for LDO and Oscillator to power down */
264 timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
267 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
268 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
270 } while (!time_after(jiffies, timeout));
272 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
273 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
279 ti_pipe3_disable_clocks(phy);
283 static struct phy_ops ops = {
284 .init = ti_pipe3_init,
285 .exit = ti_pipe3_exit,
286 .power_on = ti_pipe3_power_on,
287 .power_off = ti_pipe3_power_off,
288 .owner = THIS_MODULE,
291 static const struct of_device_id ti_pipe3_id_table[];
293 static int ti_pipe3_probe(struct platform_device *pdev)
295 struct ti_pipe3 *phy;
296 struct phy *generic_phy;
297 struct phy_provider *phy_provider;
298 struct resource *res;
299 struct device_node *node = pdev->dev.of_node;
300 struct device_node *control_node;
301 struct platform_device *control_pdev;
302 const struct of_device_id *match;
305 phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
309 phy->dev = &pdev->dev;
311 if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
312 match = of_match_device(ti_pipe3_id_table, &pdev->dev);
316 phy->dpll_map = (struct pipe3_dpll_map *)match->data;
317 if (!phy->dpll_map) {
318 dev_err(&pdev->dev, "no DPLL data\n");
322 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
324 phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
325 if (IS_ERR(phy->pll_ctrl_base))
326 return PTR_ERR(phy->pll_ctrl_base);
328 phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
329 if (IS_ERR(phy->sys_clk)) {
330 dev_err(&pdev->dev, "unable to get sysclk\n");
335 phy->refclk = devm_clk_get(phy->dev, "refclk");
336 if (IS_ERR(phy->refclk)) {
337 dev_err(&pdev->dev, "unable to get refclk\n");
338 /* older DTBs have missing refclk in SATA PHY
339 * so don't bail out in case of SATA PHY.
341 if (!of_device_is_compatible(node, "ti,phy-pipe3-sata"))
342 return PTR_ERR(phy->refclk);
345 if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
346 phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
347 if (IS_ERR(phy->wkupclk)) {
348 dev_err(&pdev->dev, "unable to get wkupclk\n");
349 return PTR_ERR(phy->wkupclk);
352 phy->wkupclk = ERR_PTR(-ENODEV);
355 if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
357 clk = devm_clk_get(phy->dev, "dpll_ref");
359 dev_err(&pdev->dev, "unable to get dpll ref clk\n");
362 clk_set_rate(clk, 1500000000);
364 clk = devm_clk_get(phy->dev, "dpll_ref_m2");
366 dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
369 clk_set_rate(clk, 100000000);
371 clk = devm_clk_get(phy->dev, "phy-div");
373 dev_err(&pdev->dev, "unable to get phy-div clk\n");
376 clk_set_rate(clk, 100000000);
378 phy->div_clk = devm_clk_get(phy->dev, "div-clk");
379 if (IS_ERR(phy->div_clk)) {
380 dev_err(&pdev->dev, "unable to get div-clk\n");
381 return PTR_ERR(phy->div_clk);
384 phy->div_clk = ERR_PTR(-ENODEV);
387 control_node = of_parse_phandle(node, "ctrl-module", 0);
389 dev_err(&pdev->dev, "Failed to get control device phandle\n");
393 control_pdev = of_find_device_by_node(control_node);
395 dev_err(&pdev->dev, "Failed to get control device\n");
399 phy->control_dev = &control_pdev->dev;
401 omap_control_phy_power(phy->control_dev, 0);
403 platform_set_drvdata(pdev, phy);
404 pm_runtime_enable(phy->dev);
405 /* Prevent auto-disable of refclk for SATA PHY due to Errata i783 */
406 if (of_device_is_compatible(node, "ti,phy-pipe3-sata"))
407 if (!IS_ERR(phy->refclk))
408 clk_prepare_enable(phy->refclk);
410 generic_phy = devm_phy_create(phy->dev, NULL, &ops);
411 if (IS_ERR(generic_phy))
412 return PTR_ERR(generic_phy);
414 phy_set_drvdata(generic_phy, phy);
415 phy_provider = devm_of_phy_provider_register(phy->dev,
416 of_phy_simple_xlate);
417 if (IS_ERR(phy_provider))
418 return PTR_ERR(phy_provider);
423 static int ti_pipe3_remove(struct platform_device *pdev)
425 pm_runtime_disable(&pdev->dev);
430 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
434 if (!IS_ERR(phy->refclk)) {
435 ret = clk_prepare_enable(phy->refclk);
437 dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
442 if (!IS_ERR(phy->wkupclk)) {
443 ret = clk_prepare_enable(phy->wkupclk);
445 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
450 if (!IS_ERR(phy->div_clk)) {
451 ret = clk_prepare_enable(phy->div_clk);
453 dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
454 goto disable_wkupclk;
461 if (!IS_ERR(phy->wkupclk))
462 clk_disable_unprepare(phy->wkupclk);
465 if (!IS_ERR(phy->refclk))
466 clk_disable_unprepare(phy->refclk);
471 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
473 if (!IS_ERR(phy->wkupclk))
474 clk_disable_unprepare(phy->wkupclk);
475 if (!IS_ERR(phy->refclk))
476 clk_disable_unprepare(phy->refclk);
477 if (!IS_ERR(phy->div_clk))
478 clk_disable_unprepare(phy->div_clk);
481 static const struct of_device_id ti_pipe3_id_table[] = {
483 .compatible = "ti,phy-usb3",
484 .data = dpll_map_usb,
487 .compatible = "ti,omap-usb3",
488 .data = dpll_map_usb,
491 .compatible = "ti,phy-pipe3-sata",
492 .data = dpll_map_sata,
495 .compatible = "ti,phy-pipe3-pcie",
499 MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
501 static struct platform_driver ti_pipe3_driver = {
502 .probe = ti_pipe3_probe,
503 .remove = ti_pipe3_remove,
506 .of_match_table = ti_pipe3_id_table,
510 module_platform_driver(ti_pipe3_driver);
512 MODULE_ALIAS("platform:ti_pipe3");
513 MODULE_AUTHOR("Texas Instruments Inc.");
514 MODULE_DESCRIPTION("TI PIPE3 phy driver");
515 MODULE_LICENSE("GPL v2");