2 * phy-ti-pipe3 - PIPE3 PHY driver.
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * Author: Kishon Vijay Abraham I <kishon@ti.com>
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/phy/phy.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/delay.h>
29 #include <linux/phy/omap_control_phy.h>
30 #include <linux/of_platform.h>
31 #include <linux/spinlock.h>
33 #define PLL_STATUS 0x00000004
34 #define PLL_GO 0x00000008
35 #define PLL_CONFIGURATION1 0x0000000C
36 #define PLL_CONFIGURATION2 0x00000010
37 #define PLL_CONFIGURATION3 0x00000014
38 #define PLL_CONFIGURATION4 0x00000020
40 #define PLL_REGM_MASK 0x001FFE00
41 #define PLL_REGM_SHIFT 0x9
42 #define PLL_REGM_F_MASK 0x0003FFFF
43 #define PLL_REGM_F_SHIFT 0x0
44 #define PLL_REGN_MASK 0x000001FE
45 #define PLL_REGN_SHIFT 0x1
46 #define PLL_SELFREQDCO_MASK 0x0000000E
47 #define PLL_SELFREQDCO_SHIFT 0x1
48 #define PLL_SD_MASK 0x0003FC00
49 #define PLL_SD_SHIFT 10
50 #define SET_PLL_GO 0x1
51 #define PLL_LDOPWDN BIT(15)
52 #define PLL_TICOPWDN BIT(16)
57 * This is an Empirical value that works, need to confirm the actual
58 * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
59 * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
61 #define PLL_IDLE_TIME 100 /* in milliseconds */
62 #define PLL_LOCK_TIME 100 /* in milliseconds */
64 struct pipe3_dpll_params {
72 struct pipe3_dpll_map {
74 struct pipe3_dpll_params params;
78 void __iomem *pll_ctrl_base;
80 struct device *control_dev;
85 struct pipe3_dpll_map *dpll_map;
87 spinlock_t lock; /* serialize clock enable/disable */
88 /* the below flag is needed specifically for SATA */
92 static struct pipe3_dpll_map dpll_map_usb[] = {
93 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
94 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
95 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
96 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
97 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
98 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
102 static struct pipe3_dpll_map dpll_map_sata[] = {
103 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
104 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
105 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
106 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
107 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
108 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
109 { }, /* Terminator */
112 static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
114 return __raw_readl(addr + offset);
117 static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
120 __raw_writel(data, addr + offset);
123 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
126 struct pipe3_dpll_map *dpll_map = phy->dpll_map;
128 rate = clk_get_rate(phy->sys_clk);
130 for (; dpll_map->rate; dpll_map++) {
131 if (rate == dpll_map->rate)
132 return &dpll_map->params;
135 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
140 static int ti_pipe3_power_off(struct phy *x)
142 struct ti_pipe3 *phy = phy_get_drvdata(x);
144 omap_control_phy_power(phy->control_dev, 0);
149 static int ti_pipe3_power_on(struct phy *x)
151 struct ti_pipe3 *phy = phy_get_drvdata(x);
153 omap_control_phy_power(phy->control_dev, 1);
158 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
161 unsigned long timeout;
163 timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
166 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
169 } while (!time_after(jiffies, timeout));
171 if (!(val & PLL_LOCK)) {
172 dev_err(phy->dev, "DPLL failed to lock\n");
179 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
182 struct pipe3_dpll_params *dpll_params;
184 dpll_params = ti_pipe3_get_dpll_params(phy);
188 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
189 val &= ~PLL_REGN_MASK;
190 val |= dpll_params->n << PLL_REGN_SHIFT;
191 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
193 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
194 val &= ~PLL_SELFREQDCO_MASK;
195 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
196 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
198 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
199 val &= ~PLL_REGM_MASK;
200 val |= dpll_params->m << PLL_REGM_SHIFT;
201 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
203 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
204 val &= ~PLL_REGM_F_MASK;
205 val |= dpll_params->mf << PLL_REGM_F_SHIFT;
206 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
208 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
210 val |= dpll_params->sd << PLL_SD_SHIFT;
211 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
213 ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
215 return ti_pipe3_dpll_wait_lock(phy);
218 static int ti_pipe3_init(struct phy *x)
220 struct ti_pipe3 *phy = phy_get_drvdata(x);
225 * Set pcie_pcs register to 0x96 for proper functioning of phy
226 * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
229 if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
230 omap_control_pcie_pcs(phy->control_dev, 0x96);
234 /* Bring it out of IDLE if it is IDLE */
235 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
236 if (val & PLL_IDLE) {
238 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
239 ret = ti_pipe3_dpll_wait_lock(phy);
242 /* Program the DPLL only if not locked */
243 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
244 if (!(val & PLL_LOCK))
245 if (ti_pipe3_dpll_program(phy))
251 static int ti_pipe3_exit(struct phy *x)
253 struct ti_pipe3 *phy = phy_get_drvdata(x);
255 unsigned long timeout;
257 /* SATA DPLL can't be powered down due to Errata i783 and PCIe
258 * does not have internal DPLL
260 if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
261 of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
264 /* Put DPLL in IDLE mode */
265 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
267 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
269 /* wait for LDO and Oscillator to power down */
270 timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
273 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
274 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
276 } while (!time_after(jiffies, timeout));
278 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
279 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
286 static struct phy_ops ops = {
287 .init = ti_pipe3_init,
288 .exit = ti_pipe3_exit,
289 .power_on = ti_pipe3_power_on,
290 .power_off = ti_pipe3_power_off,
291 .owner = THIS_MODULE,
295 static const struct of_device_id ti_pipe3_id_table[];
298 static int ti_pipe3_probe(struct platform_device *pdev)
300 struct ti_pipe3 *phy;
301 struct phy *generic_phy;
302 struct phy_provider *phy_provider;
303 struct resource *res;
304 struct device_node *node = pdev->dev.of_node;
305 struct device_node *control_node;
306 struct platform_device *control_pdev;
307 const struct of_device_id *match;
310 phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
314 phy->dev = &pdev->dev;
315 spin_lock_init(&phy->lock);
317 if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
318 match = of_match_device(of_match_ptr(ti_pipe3_id_table),
323 phy->dpll_map = (struct pipe3_dpll_map *)match->data;
324 if (!phy->dpll_map) {
325 dev_err(&pdev->dev, "no DPLL data\n");
329 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
331 phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
332 if (IS_ERR(phy->pll_ctrl_base))
333 return PTR_ERR(phy->pll_ctrl_base);
335 phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
336 if (IS_ERR(phy->sys_clk)) {
337 dev_err(&pdev->dev, "unable to get sysclk\n");
342 phy->refclk = devm_clk_get(phy->dev, "refclk");
343 if (IS_ERR(phy->refclk)) {
344 dev_err(&pdev->dev, "unable to get refclk\n");
345 /* older DTBs have missing refclk in SATA PHY
346 * so don't bail out in case of SATA PHY.
348 if (!of_device_is_compatible(node, "ti,phy-pipe3-sata"))
349 return PTR_ERR(phy->refclk);
352 if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
353 phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
354 if (IS_ERR(phy->wkupclk)) {
355 dev_err(&pdev->dev, "unable to get wkupclk\n");
356 return PTR_ERR(phy->wkupclk);
359 phy->wkupclk = ERR_PTR(-ENODEV);
362 if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
364 clk = devm_clk_get(phy->dev, "dpll_ref");
366 dev_err(&pdev->dev, "unable to get dpll ref clk\n");
369 clk_set_rate(clk, 1500000000);
371 clk = devm_clk_get(phy->dev, "dpll_ref_m2");
373 dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
376 clk_set_rate(clk, 100000000);
378 clk = devm_clk_get(phy->dev, "phy-div");
380 dev_err(&pdev->dev, "unable to get phy-div clk\n");
383 clk_set_rate(clk, 100000000);
385 phy->div_clk = devm_clk_get(phy->dev, "div-clk");
386 if (IS_ERR(phy->div_clk)) {
387 dev_err(&pdev->dev, "unable to get div-clk\n");
388 return PTR_ERR(phy->div_clk);
391 phy->div_clk = ERR_PTR(-ENODEV);
394 control_node = of_parse_phandle(node, "ctrl-module", 0);
396 dev_err(&pdev->dev, "Failed to get control device phandle\n");
400 control_pdev = of_find_device_by_node(control_node);
402 dev_err(&pdev->dev, "Failed to get control device\n");
406 phy->control_dev = &control_pdev->dev;
408 omap_control_phy_power(phy->control_dev, 0);
410 platform_set_drvdata(pdev, phy);
411 pm_runtime_enable(phy->dev);
413 generic_phy = devm_phy_create(phy->dev, NULL, &ops);
414 if (IS_ERR(generic_phy))
415 return PTR_ERR(generic_phy);
417 phy_set_drvdata(generic_phy, phy);
418 phy_provider = devm_of_phy_provider_register(phy->dev,
419 of_phy_simple_xlate);
420 if (IS_ERR(phy_provider))
421 return PTR_ERR(phy_provider);
423 pm_runtime_get(&pdev->dev);
428 static int ti_pipe3_remove(struct platform_device *pdev)
430 if (!pm_runtime_suspended(&pdev->dev))
431 pm_runtime_put(&pdev->dev);
432 pm_runtime_disable(&pdev->dev);
438 static int ti_pipe3_enable_refclk(struct ti_pipe3 *phy)
440 if (!IS_ERR(phy->refclk) && !phy->refclk_enabled) {
443 ret = clk_prepare_enable(phy->refclk);
445 dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
448 phy->refclk_enabled = true;
454 static void ti_pipe3_disable_refclk(struct ti_pipe3 *phy)
456 if (!IS_ERR(phy->refclk))
457 clk_disable_unprepare(phy->refclk);
459 phy->refclk_enabled = false;
462 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
467 spin_lock_irqsave(&phy->lock, flags);
471 ret = ti_pipe3_enable_refclk(phy);
475 if (!IS_ERR(phy->wkupclk)) {
476 ret = clk_prepare_enable(phy->wkupclk);
478 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
483 if (!IS_ERR(phy->div_clk)) {
484 ret = clk_prepare_enable(phy->div_clk);
486 dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
492 spin_unlock_irqrestore(&phy->lock, flags);
496 if (!IS_ERR(phy->wkupclk))
497 clk_disable_unprepare(phy->wkupclk);
500 if (!IS_ERR(phy->refclk))
501 clk_disable_unprepare(phy->refclk);
503 ti_pipe3_disable_refclk(phy);
505 spin_unlock_irqrestore(&phy->lock, flags);
509 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
513 spin_lock_irqsave(&phy->lock, flags);
515 spin_unlock_irqrestore(&phy->lock, flags);
519 if (!IS_ERR(phy->wkupclk))
520 clk_disable_unprepare(phy->wkupclk);
521 /* Don't disable refclk for SATA PHY due to Errata i783 */
522 if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata"))
523 ti_pipe3_disable_refclk(phy);
524 if (!IS_ERR(phy->div_clk))
525 clk_disable_unprepare(phy->div_clk);
526 phy->enabled = false;
527 spin_unlock_irqrestore(&phy->lock, flags);
530 static int ti_pipe3_runtime_suspend(struct device *dev)
532 struct ti_pipe3 *phy = dev_get_drvdata(dev);
534 ti_pipe3_disable_clocks(phy);
538 static int ti_pipe3_runtime_resume(struct device *dev)
540 struct ti_pipe3 *phy = dev_get_drvdata(dev);
543 ret = ti_pipe3_enable_clocks(phy);
547 static int ti_pipe3_suspend(struct device *dev)
549 struct ti_pipe3 *phy = dev_get_drvdata(dev);
551 ti_pipe3_disable_clocks(phy);
555 static int ti_pipe3_resume(struct device *dev)
557 struct ti_pipe3 *phy = dev_get_drvdata(dev);
560 ret = ti_pipe3_enable_clocks(phy);
564 pm_runtime_disable(dev);
565 pm_runtime_set_active(dev);
566 pm_runtime_enable(dev);
571 static const struct dev_pm_ops ti_pipe3_pm_ops = {
572 SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
573 ti_pipe3_runtime_resume, NULL)
574 SET_SYSTEM_SLEEP_PM_OPS(ti_pipe3_suspend, ti_pipe3_resume)
578 static const struct of_device_id ti_pipe3_id_table[] = {
580 .compatible = "ti,phy-usb3",
581 .data = dpll_map_usb,
584 .compatible = "ti,omap-usb3",
585 .data = dpll_map_usb,
588 .compatible = "ti,phy-pipe3-sata",
589 .data = dpll_map_sata,
592 .compatible = "ti,phy-pipe3-pcie",
596 MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
599 static struct platform_driver ti_pipe3_driver = {
600 .probe = ti_pipe3_probe,
601 .remove = ti_pipe3_remove,
604 .pm = &ti_pipe3_pm_ops,
605 .of_match_table = of_match_ptr(ti_pipe3_id_table),
609 module_platform_driver(ti_pipe3_driver);
611 MODULE_ALIAS("platform: ti_pipe3");
612 MODULE_AUTHOR("Texas Instruments Inc.");
613 MODULE_DESCRIPTION("TI PIPE3 phy driver");
614 MODULE_LICENSE("GPL v2");