2 * Pin controller and GPIO driver for Amlogic Meson SoCs
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
16 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
17 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
18 * variable number of pins.
20 * The AO bank is special because it belongs to the Always-On power
21 * domain which can't be powered off; the bank also uses a set of
22 * registers different from the other banks.
24 * For each of the two power domains (regular and always-on) there are
25 * 4 different register ranges that control the following properties
28 * 2) pull enable/disable
30 * 4) GPIO direction, output value, input value
32 * In some cases the register ranges for pull enable and pull
33 * direction are the same and thus there are only 3 register ranges.
35 * Every pinmux group can be enabled by a specific bit in the first
36 * register range of the domain; when all groups for a given pin are
37 * disabled the pin acts as a GPIO.
39 * For the pull and GPIO configuration every bank uses a contiguous
40 * set of bits in the register sets described above; the same register
41 * can be shared by more banks with different offsets.
43 * In addition to this there are some registers shared between all
44 * banks that control the IRQ functionality. This feature is not
45 * supported at the moment by the driver.
48 #include <linux/device.h>
49 #include <linux/gpio.h>
50 #include <linux/init.h>
52 #include <linux/module.h>
54 #include <linux/of_address.h>
55 #include <linux/pinctrl/pinconf-generic.h>
56 #include <linux/pinctrl/pinconf.h>
57 #include <linux/pinctrl/pinctrl.h>
58 #include <linux/pinctrl/pinmux.h>
59 #include <linux/platform_device.h>
60 #include <linux/regmap.h>
61 #include <linux/seq_file.h>
64 #include "../pinctrl-utils.h"
65 #include "pinctrl-meson.h"
68 * meson_get_bank() - find the bank containing a given pin
70 * @domain: the domain containing the pin
71 * @pin: the pin number
72 * @bank: the found bank
74 * Return: 0 on success, a negative value on error
76 static int meson_get_bank(struct meson_domain *domain, unsigned int pin,
77 struct meson_bank **bank)
81 for (i = 0; i < domain->data->num_banks; i++) {
82 if (pin >= domain->data->banks[i].first &&
83 pin <= domain->data->banks[i].last) {
84 *bank = &domain->data->banks[i];
93 * meson_get_domain_and_bank() - find domain and bank containing a given pin
95 * @pc: Meson pin controller device
96 * @pin: the pin number
97 * @domain: the found domain
98 * @bank: the found bank
100 * Return: 0 on success, a negative value on error
102 static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin,
103 struct meson_domain **domain,
104 struct meson_bank **bank)
106 struct meson_domain *d;
109 for (i = 0; i < pc->data->num_domains; i++) {
111 if (pin >= d->data->pin_base &&
112 pin < d->data->pin_base + d->data->num_pins) {
114 return meson_get_bank(d, pin, bank);
122 * meson_calc_reg_and_bit() - calculate register and bit for a pin
124 * @bank: the bank containing the pin
125 * @pin: the pin number
126 * @reg_type: the type of register needed (pull-enable, pull, etc...)
127 * @reg: the computed register offset
128 * @bit: the computed bit
130 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
131 enum meson_reg_type reg_type,
132 unsigned int *reg, unsigned int *bit)
134 struct meson_reg_desc *desc = &bank->regs[reg_type];
136 *reg = desc->reg * 4;
137 *bit = desc->bit + pin - bank->first;
140 static int meson_get_groups_count(struct pinctrl_dev *pcdev)
142 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
144 return pc->data->num_groups;
147 static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
150 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
152 return pc->data->groups[selector].name;
155 static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
156 const unsigned **pins, unsigned *num_pins)
158 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
160 *pins = pc->data->groups[selector].pins;
161 *num_pins = pc->data->groups[selector].num_pins;
166 static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
169 seq_printf(s, " %s", dev_name(pcdev->dev));
172 static const struct pinctrl_ops meson_pctrl_ops = {
173 .get_groups_count = meson_get_groups_count,
174 .get_group_name = meson_get_group_name,
175 .get_group_pins = meson_get_group_pins,
176 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
177 .dt_free_map = pinctrl_utils_dt_free_map,
178 .pin_dbg_show = meson_pin_dbg_show,
182 * meson_pmx_disable_other_groups() - disable other groups using a given pin
184 * @pc: meson pin controller device
185 * @pin: number of the pin
186 * @sel_group: index of the selected group, or -1 if none
188 * The function disables all pinmux groups using a pin except the
189 * selected one. If @sel_group is -1 all groups are disabled, leaving
190 * the pin in GPIO mode.
192 static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
193 unsigned int pin, int sel_group)
195 struct meson_pmx_group *group;
196 struct meson_domain *domain;
199 for (i = 0; i < pc->data->num_groups; i++) {
200 group = &pc->data->groups[i];
201 if (group->is_gpio || i == sel_group)
204 for (j = 0; j < group->num_pins; j++) {
205 if (group->pins[j] == pin) {
206 /* We have found a group using the pin */
207 domain = &pc->domains[group->domain];
208 regmap_update_bits(domain->reg_mux,
216 static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
219 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
220 struct meson_pmx_func *func = &pc->data->funcs[func_num];
221 struct meson_pmx_group *group = &pc->data->groups[group_num];
222 struct meson_domain *domain = &pc->domains[group->domain];
225 dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
229 * Disable groups using the same pin.
230 * The selected group is not disabled to avoid glitches.
232 for (i = 0; i < group->num_pins; i++)
233 meson_pmx_disable_other_groups(pc, group->pins[i], group_num);
235 /* Function 0 (GPIO) doesn't need any additional setting */
237 ret = regmap_update_bits(domain->reg_mux, group->reg * 4,
238 BIT(group->bit), BIT(group->bit));
243 static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
244 struct pinctrl_gpio_range *range,
247 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
249 meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1);
254 static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
256 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
258 return pc->data->num_funcs;
261 static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
264 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
266 return pc->data->funcs[selector].name;
269 static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
270 const char * const **groups,
271 unsigned * const num_groups)
273 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
275 *groups = pc->data->funcs[selector].groups;
276 *num_groups = pc->data->funcs[selector].num_groups;
281 static const struct pinmux_ops meson_pmx_ops = {
282 .set_mux = meson_pmx_set_mux,
283 .get_functions_count = meson_pmx_get_funcs_count,
284 .get_function_name = meson_pmx_get_func_name,
285 .get_function_groups = meson_pmx_get_groups,
286 .gpio_request_enable = meson_pmx_request_gpio,
289 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
290 unsigned long *configs, unsigned num_configs)
292 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
293 struct meson_domain *domain;
294 struct meson_bank *bank;
295 enum pin_config_param param;
296 unsigned int reg, bit;
300 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
304 for (i = 0; i < num_configs; i++) {
305 param = pinconf_to_config_param(configs[i]);
306 arg = pinconf_to_config_argument(configs[i]);
309 case PIN_CONFIG_BIAS_DISABLE:
310 dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
312 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
313 ret = regmap_update_bits(domain->reg_pull, reg,
318 case PIN_CONFIG_BIAS_PULL_UP:
319 dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
321 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
323 ret = regmap_update_bits(domain->reg_pullen, reg,
328 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
329 ret = regmap_update_bits(domain->reg_pull, reg,
334 case PIN_CONFIG_BIAS_PULL_DOWN:
335 dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
337 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
339 ret = regmap_update_bits(domain->reg_pullen, reg,
344 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
345 ret = regmap_update_bits(domain->reg_pull, reg,
358 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
360 struct meson_domain *domain;
361 struct meson_bank *bank;
362 unsigned int reg, bit, val;
365 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
369 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit);
371 ret = regmap_read(domain->reg_pullen, reg, &val);
375 if (!(val & BIT(bit))) {
376 conf = PIN_CONFIG_BIAS_DISABLE;
378 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
380 ret = regmap_read(domain->reg_pull, reg, &val);
385 conf = PIN_CONFIG_BIAS_PULL_UP;
387 conf = PIN_CONFIG_BIAS_PULL_DOWN;
393 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
394 unsigned long *config)
396 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
397 enum pin_config_param param = pinconf_to_config_param(*config);
401 case PIN_CONFIG_BIAS_DISABLE:
402 case PIN_CONFIG_BIAS_PULL_DOWN:
403 case PIN_CONFIG_BIAS_PULL_UP:
404 if (meson_pinconf_get_pull(pc, pin) == param)
413 *config = pinconf_to_config_packed(param, arg);
414 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
419 static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
420 unsigned int num_group,
421 unsigned long *configs, unsigned num_configs)
423 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
424 struct meson_pmx_group *group = &pc->data->groups[num_group];
427 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
429 for (i = 0; i < group->num_pins; i++) {
430 meson_pinconf_set(pcdev, group->pins[i], configs,
437 static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
438 unsigned int group, unsigned long *config)
443 static const struct pinconf_ops meson_pinconf_ops = {
444 .pin_config_get = meson_pinconf_get,
445 .pin_config_set = meson_pinconf_set,
446 .pin_config_group_get = meson_pinconf_group_get,
447 .pin_config_group_set = meson_pinconf_group_set,
451 static inline struct meson_domain *to_meson_domain(struct gpio_chip *chip)
453 return container_of(chip, struct meson_domain, chip);
456 static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio)
458 return pinctrl_request_gpio(chip->base + gpio);
461 static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio)
463 struct meson_domain *domain = to_meson_domain(chip);
465 pinctrl_free_gpio(domain->data->pin_base + gpio);
468 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
470 struct meson_domain *domain = to_meson_domain(chip);
471 unsigned int reg, bit, pin;
472 struct meson_bank *bank;
475 pin = domain->data->pin_base + gpio;
476 ret = meson_get_bank(domain, pin, &bank);
480 meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit);
482 return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit));
485 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
488 struct meson_domain *domain = to_meson_domain(chip);
489 unsigned int reg, bit, pin;
490 struct meson_bank *bank;
493 pin = domain->data->pin_base + gpio;
494 ret = meson_get_bank(domain, pin, &bank);
498 meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit);
499 ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0);
503 meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit);
504 return regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
505 value ? BIT(bit) : 0);
508 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
510 struct meson_domain *domain = to_meson_domain(chip);
511 unsigned int reg, bit, pin;
512 struct meson_bank *bank;
515 pin = domain->data->pin_base + gpio;
516 ret = meson_get_bank(domain, pin, &bank);
520 meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit);
521 regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
522 value ? BIT(bit) : 0);
525 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
527 struct meson_domain *domain = to_meson_domain(chip);
528 unsigned int reg, bit, val, pin;
529 struct meson_bank *bank;
532 pin = domain->data->pin_base + gpio;
533 ret = meson_get_bank(domain, pin, &bank);
537 meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit);
538 regmap_read(domain->reg_gpio, reg, &val);
540 return !!(val & BIT(bit));
543 static const struct of_device_id meson_pinctrl_dt_match[] = {
545 .compatible = "amlogic,meson8-pinctrl",
546 .data = &meson8_pinctrl_data,
549 .compatible = "amlogic,meson8b-pinctrl",
550 .data = &meson8b_pinctrl_data,
554 MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);
556 static int meson_gpiolib_register(struct meson_pinctrl *pc)
558 struct meson_domain *domain;
561 for (i = 0; i < pc->data->num_domains; i++) {
562 domain = &pc->domains[i];
564 domain->chip.label = domain->data->name;
565 domain->chip.dev = pc->dev;
566 domain->chip.request = meson_gpio_request;
567 domain->chip.free = meson_gpio_free;
568 domain->chip.direction_input = meson_gpio_direction_input;
569 domain->chip.direction_output = meson_gpio_direction_output;
570 domain->chip.get = meson_gpio_get;
571 domain->chip.set = meson_gpio_set;
572 domain->chip.base = domain->data->pin_base;
573 domain->chip.ngpio = domain->data->num_pins;
574 domain->chip.can_sleep = false;
575 domain->chip.of_node = domain->of_node;
576 domain->chip.of_gpio_n_cells = 2;
578 ret = gpiochip_add(&domain->chip);
580 dev_err(pc->dev, "can't add gpio chip %s\n",
585 ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
586 0, domain->data->pin_base,
589 dev_err(pc->dev, "can't add pin range\n");
596 for (i--; i >= 0; i--)
597 gpiochip_remove(&pc->domains[i].chip);
602 static struct meson_domain_data *meson_get_domain_data(struct meson_pinctrl *pc,
603 struct device_node *np)
607 for (i = 0; i < pc->data->num_domains; i++) {
608 if (!strcmp(np->name, pc->data->domain_data[i].name))
609 return &pc->data->domain_data[i];
615 static struct regmap_config meson_regmap_config = {
621 static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
622 struct device_node *node, char *name)
628 i = of_property_match_string(node, "reg-names", name);
629 if (of_address_to_resource(node, i, &res))
630 return ERR_PTR(-ENOENT);
632 base = devm_ioremap_resource(pc->dev, &res);
634 return ERR_CAST(base);
636 meson_regmap_config.max_register = resource_size(&res) - 4;
637 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
640 if (!meson_regmap_config.name)
641 return ERR_PTR(-ENOMEM);
643 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
646 static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
647 struct device_node *node)
649 struct device_node *np;
650 struct meson_domain *domain;
651 int i = 0, num_domains = 0;
653 for_each_child_of_node(node, np) {
654 if (!of_find_property(np, "gpio-controller", NULL))
659 if (num_domains != pc->data->num_domains) {
660 dev_err(pc->dev, "wrong number of subnodes\n");
664 pc->domains = devm_kzalloc(pc->dev, num_domains *
665 sizeof(struct meson_domain), GFP_KERNEL);
669 for_each_child_of_node(node, np) {
670 if (!of_find_property(np, "gpio-controller", NULL))
673 domain = &pc->domains[i];
675 domain->data = meson_get_domain_data(pc, np);
677 dev_err(pc->dev, "domain data not found for node %s\n",
682 domain->of_node = np;
684 domain->reg_mux = meson_map_resource(pc, np, "mux");
685 if (IS_ERR(domain->reg_mux)) {
686 dev_err(pc->dev, "mux registers not found\n");
687 return PTR_ERR(domain->reg_mux);
690 domain->reg_pull = meson_map_resource(pc, np, "pull");
691 if (IS_ERR(domain->reg_pull)) {
692 dev_err(pc->dev, "pull registers not found\n");
693 return PTR_ERR(domain->reg_pull);
696 domain->reg_pullen = meson_map_resource(pc, np, "pull-enable");
697 /* Use pull region if pull-enable one is not present */
698 if (IS_ERR(domain->reg_pullen))
699 domain->reg_pullen = domain->reg_pull;
701 domain->reg_gpio = meson_map_resource(pc, np, "gpio");
702 if (IS_ERR(domain->reg_gpio)) {
703 dev_err(pc->dev, "gpio registers not found\n");
704 return PTR_ERR(domain->reg_gpio);
713 static int meson_pinctrl_probe(struct platform_device *pdev)
715 const struct of_device_id *match;
716 struct device *dev = &pdev->dev;
717 struct meson_pinctrl *pc;
720 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
725 match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node);
726 pc->data = (struct meson_pinctrl_data *)match->data;
728 ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node);
732 pc->desc.name = "pinctrl-meson";
733 pc->desc.owner = THIS_MODULE;
734 pc->desc.pctlops = &meson_pctrl_ops;
735 pc->desc.pmxops = &meson_pmx_ops;
736 pc->desc.confops = &meson_pinconf_ops;
737 pc->desc.pins = pc->data->pins;
738 pc->desc.npins = pc->data->num_pins;
740 pc->pcdev = pinctrl_register(&pc->desc, pc->dev, pc);
741 if (IS_ERR(pc->pcdev)) {
742 dev_err(pc->dev, "can't register pinctrl device");
743 return PTR_ERR(pc->pcdev);
746 ret = meson_gpiolib_register(pc);
748 pinctrl_unregister(pc->pcdev);
755 static struct platform_driver meson_pinctrl_driver = {
756 .probe = meson_pinctrl_probe,
758 .name = "meson-pinctrl",
759 .of_match_table = meson_pinctrl_dt_match,
762 module_platform_driver(meson_pinctrl_driver);
764 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
765 MODULE_DESCRIPTION("Amlogic Meson pinctrl driver");
766 MODULE_LICENSE("GPL v2");