2 * Marvell Armada XP pinctrl driver based on mvebu pinctrl core
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This file supports the three variants of Armada XP SoCs that are
14 * available: mv78230, mv78260 and mv78460. From a pin muxing
15 * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
16 * both have 67 MPP pins (more GPIOs and address lines for the memory
17 * bus mainly). The only difference between the mv78260 and the
18 * mv78460 in terms of pin muxing is the addition of two functions on
19 * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two
20 * cores, mv78460 has four cores).
23 #include <linux/err.h>
24 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
30 #include <linux/of_device.h>
31 #include <linux/pinctrl/pinctrl.h>
32 #include <linux/bitops.h>
34 #include "pinctrl-mvebu.h"
36 enum armada_xp_variant {
40 V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460),
41 V_MV78260_PLUS = (V_MV78260 | V_MV78460),
44 static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
46 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
47 MPP_VAR_FUNCTION(0x1, "ge0", "txclko", V_MV78230_PLUS),
48 MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)),
50 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
51 MPP_VAR_FUNCTION(0x1, "ge0", "txd0", V_MV78230_PLUS),
52 MPP_VAR_FUNCTION(0x4, "lcd", "d1", V_MV78230_PLUS)),
54 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
55 MPP_VAR_FUNCTION(0x1, "ge0", "txd1", V_MV78230_PLUS),
56 MPP_VAR_FUNCTION(0x4, "lcd", "d2", V_MV78230_PLUS)),
58 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
59 MPP_VAR_FUNCTION(0x1, "ge0", "txd2", V_MV78230_PLUS),
60 MPP_VAR_FUNCTION(0x4, "lcd", "d3", V_MV78230_PLUS)),
62 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
63 MPP_VAR_FUNCTION(0x1, "ge0", "txd3", V_MV78230_PLUS),
64 MPP_VAR_FUNCTION(0x4, "lcd", "d4", V_MV78230_PLUS)),
66 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
67 MPP_VAR_FUNCTION(0x1, "ge0", "txctl", V_MV78230_PLUS),
68 MPP_VAR_FUNCTION(0x4, "lcd", "d5", V_MV78230_PLUS)),
70 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
71 MPP_VAR_FUNCTION(0x1, "ge0", "rxd0", V_MV78230_PLUS),
72 MPP_VAR_FUNCTION(0x4, "lcd", "d6", V_MV78230_PLUS)),
74 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
75 MPP_VAR_FUNCTION(0x1, "ge0", "rxd1", V_MV78230_PLUS),
76 MPP_VAR_FUNCTION(0x4, "lcd", "d7", V_MV78230_PLUS)),
78 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
79 MPP_VAR_FUNCTION(0x1, "ge0", "rxd2", V_MV78230_PLUS),
80 MPP_VAR_FUNCTION(0x4, "lcd", "d8", V_MV78230_PLUS)),
82 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
83 MPP_VAR_FUNCTION(0x1, "ge0", "rxd3", V_MV78230_PLUS),
84 MPP_VAR_FUNCTION(0x4, "lcd", "d9", V_MV78230_PLUS)),
86 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
87 MPP_VAR_FUNCTION(0x1, "ge0", "rxctl", V_MV78230_PLUS),
88 MPP_VAR_FUNCTION(0x4, "lcd", "d10", V_MV78230_PLUS)),
90 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
91 MPP_VAR_FUNCTION(0x1, "ge0", "rxclk", V_MV78230_PLUS),
92 MPP_VAR_FUNCTION(0x4, "lcd", "d11", V_MV78230_PLUS)),
94 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
95 MPP_VAR_FUNCTION(0x1, "ge0", "txd4", V_MV78230_PLUS),
96 MPP_VAR_FUNCTION(0x2, "ge1", "clkout", V_MV78230_PLUS),
97 MPP_VAR_FUNCTION(0x4, "lcd", "d12", V_MV78230_PLUS)),
99 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
100 MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS),
101 MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS),
102 MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)),
104 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
105 MPP_VAR_FUNCTION(0x1, "ge0", "txd6", V_MV78230_PLUS),
106 MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS),
107 MPP_VAR_FUNCTION(0x4, "lcd", "d14", V_MV78230_PLUS)),
109 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
110 MPP_VAR_FUNCTION(0x1, "ge0", "txd7", V_MV78230_PLUS),
111 MPP_VAR_FUNCTION(0x2, "ge1", "txd2", V_MV78230_PLUS),
112 MPP_VAR_FUNCTION(0x4, "lcd", "d15", V_MV78230_PLUS)),
114 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
115 MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS),
116 MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS),
117 MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)),
119 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
120 MPP_VAR_FUNCTION(0x1, "ge0", "col", V_MV78230_PLUS),
121 MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS),
122 MPP_VAR_FUNCTION(0x4, "lcd", "d17", V_MV78230_PLUS)),
124 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
125 MPP_VAR_FUNCTION(0x1, "ge0", "rxerr", V_MV78230_PLUS),
126 MPP_VAR_FUNCTION(0x2, "ge1", "rxd0", V_MV78230_PLUS),
127 MPP_VAR_FUNCTION(0x3, "ptp", "trig", V_MV78230_PLUS),
128 MPP_VAR_FUNCTION(0x4, "lcd", "d18", V_MV78230_PLUS)),
130 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
131 MPP_VAR_FUNCTION(0x1, "ge0", "crs", V_MV78230_PLUS),
132 MPP_VAR_FUNCTION(0x2, "ge1", "rxd1", V_MV78230_PLUS),
133 MPP_VAR_FUNCTION(0x3, "ptp", "evreq", V_MV78230_PLUS),
134 MPP_VAR_FUNCTION(0x4, "lcd", "d19", V_MV78230_PLUS)),
136 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
137 MPP_VAR_FUNCTION(0x1, "ge0", "rxd4", V_MV78230_PLUS),
138 MPP_VAR_FUNCTION(0x2, "ge1", "rxd2", V_MV78230_PLUS),
139 MPP_VAR_FUNCTION(0x3, "ptp", "clk", V_MV78230_PLUS),
140 MPP_VAR_FUNCTION(0x4, "lcd", "d20", V_MV78230_PLUS)),
142 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
143 MPP_VAR_FUNCTION(0x1, "ge0", "rxd5", V_MV78230_PLUS),
144 MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS),
145 MPP_VAR_FUNCTION(0x3, "mem", "bat", V_MV78230_PLUS),
146 MPP_VAR_FUNCTION(0x4, "lcd", "d21", V_MV78230_PLUS)),
148 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
149 MPP_VAR_FUNCTION(0x1, "ge0", "rxd6", V_MV78230_PLUS),
150 MPP_VAR_FUNCTION(0x2, "ge1", "rxctl", V_MV78230_PLUS),
151 MPP_VAR_FUNCTION(0x3, "sata0", "prsnt", V_MV78230_PLUS),
152 MPP_VAR_FUNCTION(0x4, "lcd", "d22", V_MV78230_PLUS)),
154 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
155 MPP_VAR_FUNCTION(0x1, "ge0", "rxd7", V_MV78230_PLUS),
156 MPP_VAR_FUNCTION(0x2, "ge1", "rxclk", V_MV78230_PLUS),
157 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
158 MPP_VAR_FUNCTION(0x4, "lcd", "d23", V_MV78230_PLUS)),
160 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
161 MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS),
162 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re", V_MV78230_PLUS),
163 MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS),
164 MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)),
166 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
167 MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS),
168 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we", V_MV78230_PLUS),
169 MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS),
170 MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)),
172 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
173 MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS),
174 MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS),
175 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)),
177 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
178 MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS),
179 MPP_VAR_FUNCTION(0x3, "tdm", "dtx", V_MV78230_PLUS),
180 MPP_VAR_FUNCTION(0x4, "lcd", "e", V_MV78230_PLUS)),
182 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
183 MPP_VAR_FUNCTION(0x1, "ptp", "evreq", V_MV78230_PLUS),
184 MPP_VAR_FUNCTION(0x3, "tdm", "drx", V_MV78230_PLUS),
185 MPP_VAR_FUNCTION(0x4, "lcd", "pwm", V_MV78230_PLUS)),
187 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
188 MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS),
189 MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS),
190 MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS),
191 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
193 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
194 MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS),
195 MPP_VAR_FUNCTION(0x3, "tdm", "int1", V_MV78230_PLUS)),
197 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
198 MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS),
199 MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS),
200 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
202 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
203 MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS),
204 MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS),
205 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)),
207 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
208 MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS),
209 MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS),
210 MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS)),
212 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
213 MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS),
214 MPP_VAR_FUNCTION(0x2, "sata0", "prsnt", V_MV78230_PLUS),
215 MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS)),
217 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
218 MPP_VAR_FUNCTION(0x1, "sd0", "d3", V_MV78230_PLUS),
219 MPP_VAR_FUNCTION(0x2, "sata1", "prsnt", V_MV78230_PLUS),
220 MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)),
222 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
223 MPP_VAR_FUNCTION(0x1, "spi", "mosi", V_MV78230_PLUS)),
225 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
226 MPP_VAR_FUNCTION(0x1, "spi", "miso", V_MV78230_PLUS)),
228 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
229 MPP_VAR_FUNCTION(0x1, "spi", "sck", V_MV78230_PLUS)),
231 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
232 MPP_VAR_FUNCTION(0x1, "spi", "cs0", V_MV78230_PLUS)),
234 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
235 MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS),
236 MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS),
237 MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd", V_MV78230_PLUS),
238 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
239 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)),
241 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
242 MPP_VAR_FUNCTION(0x1, "spi", "cs2", V_MV78230_PLUS),
243 MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS),
244 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
245 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
246 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS)),
248 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
249 MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS),
250 MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS),
251 MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS),
252 MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS),
253 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
255 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
256 MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS),
257 MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS),
258 MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS),
259 MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS),
260 MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd", V_MV78460)),
262 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
263 MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS),
264 MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS),
265 MPP_VAR_FUNCTION(0x3, "spi", "cs4", V_MV78230_PLUS),
266 MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS),
267 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)),
269 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
270 MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS),
271 MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS),
272 MPP_VAR_FUNCTION(0x3, "spi", "cs5", V_MV78230_PLUS),
273 MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS)),
275 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
276 MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS),
277 MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS),
278 MPP_VAR_FUNCTION(0x3, "spi", "cs6", V_MV78230_PLUS),
279 MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS)),
281 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
282 MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS),
283 MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS),
284 MPP_VAR_FUNCTION(0x3, "spi", "cs7", V_MV78230_PLUS),
285 MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS),
286 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)),
288 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
289 MPP_VAR_FUNCTION(0x1, "tclk", NULL, V_MV78230_PLUS),
290 MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)),
292 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
293 MPP_VAR_FUNCTION(0x1, "dev", "we3", V_MV78260_PLUS)),
295 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
296 MPP_VAR_FUNCTION(0x1, "dev", "we2", V_MV78260_PLUS)),
298 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
299 MPP_VAR_FUNCTION(0x1, "dev", "ad16", V_MV78260_PLUS)),
301 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
302 MPP_VAR_FUNCTION(0x1, "dev", "ad17", V_MV78260_PLUS)),
304 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
305 MPP_VAR_FUNCTION(0x1, "dev", "ad18", V_MV78260_PLUS)),
307 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
308 MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)),
310 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
311 MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS),
312 MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd", V_MV78260_PLUS)),
314 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
315 MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS),
316 MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd", V_MV78260_PLUS)),
318 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
319 MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS),
320 MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd", V_MV78460)),
322 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
323 MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)),
325 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
326 MPP_VAR_FUNCTION(0x1, "dev", "ad24", V_MV78260_PLUS)),
328 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
329 MPP_VAR_FUNCTION(0x1, "dev", "ad25", V_MV78260_PLUS)),
331 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
332 MPP_VAR_FUNCTION(0x1, "dev", "ad26", V_MV78260_PLUS)),
334 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
335 MPP_VAR_FUNCTION(0x1, "dev", "ad27", V_MV78260_PLUS)),
337 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
338 MPP_VAR_FUNCTION(0x1, "dev", "ad28", V_MV78260_PLUS)),
340 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
341 MPP_VAR_FUNCTION(0x1, "dev", "ad29", V_MV78260_PLUS)),
343 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
344 MPP_VAR_FUNCTION(0x1, "dev", "ad30", V_MV78260_PLUS)),
346 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
347 MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)),
350 static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
352 static struct of_device_id armada_xp_pinctrl_of_match[] = {
354 .compatible = "marvell,mv78230-pinctrl",
355 .data = (void *) V_MV78230,
358 .compatible = "marvell,mv78260-pinctrl",
359 .data = (void *) V_MV78260,
362 .compatible = "marvell,mv78460-pinctrl",
363 .data = (void *) V_MV78460,
368 static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
372 static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
373 MPP_GPIO_RANGE(0, 0, 0, 32),
374 MPP_GPIO_RANGE(1, 32, 32, 17),
377 static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
381 static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
382 MPP_GPIO_RANGE(0, 0, 0, 32),
383 MPP_GPIO_RANGE(1, 32, 32, 32),
384 MPP_GPIO_RANGE(2, 64, 64, 3),
387 static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
391 static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
392 MPP_GPIO_RANGE(0, 0, 0, 32),
393 MPP_GPIO_RANGE(1, 32, 32, 32),
394 MPP_GPIO_RANGE(2, 64, 64, 3),
397 static int armada_xp_pinctrl_probe(struct platform_device *pdev)
399 struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
400 const struct of_device_id *match =
401 of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
406 soc->variant = (unsigned) match->data & 0xff;
408 switch (soc->variant) {
410 soc->controls = mv78230_mpp_controls;
411 soc->ncontrols = ARRAY_SIZE(mv78230_mpp_controls);
412 soc->modes = armada_xp_mpp_modes;
413 /* We don't necessarily want the full list of the
414 * armada_xp_mpp_modes, but only the first 'n' ones
415 * that are available on this SoC */
416 soc->nmodes = mv78230_mpp_controls[0].npins;
417 soc->gpioranges = mv78230_mpp_gpio_ranges;
418 soc->ngpioranges = ARRAY_SIZE(mv78230_mpp_gpio_ranges);
421 soc->controls = mv78260_mpp_controls;
422 soc->ncontrols = ARRAY_SIZE(mv78260_mpp_controls);
423 soc->modes = armada_xp_mpp_modes;
424 /* We don't necessarily want the full list of the
425 * armada_xp_mpp_modes, but only the first 'n' ones
426 * that are available on this SoC */
427 soc->nmodes = mv78260_mpp_controls[0].npins;
428 soc->gpioranges = mv78260_mpp_gpio_ranges;
429 soc->ngpioranges = ARRAY_SIZE(mv78260_mpp_gpio_ranges);
432 soc->controls = mv78460_mpp_controls;
433 soc->ncontrols = ARRAY_SIZE(mv78460_mpp_controls);
434 soc->modes = armada_xp_mpp_modes;
435 /* We don't necessarily want the full list of the
436 * armada_xp_mpp_modes, but only the first 'n' ones
437 * that are available on this SoC */
438 soc->nmodes = mv78460_mpp_controls[0].npins;
439 soc->gpioranges = mv78460_mpp_gpio_ranges;
440 soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
444 pdev->dev.platform_data = soc;
446 return mvebu_pinctrl_probe(pdev);
449 static int armada_xp_pinctrl_remove(struct platform_device *pdev)
451 return mvebu_pinctrl_remove(pdev);
454 static struct platform_driver armada_xp_pinctrl_driver = {
456 .name = "armada-xp-pinctrl",
457 .owner = THIS_MODULE,
458 .of_match_table = armada_xp_pinctrl_of_match,
460 .probe = armada_xp_pinctrl_probe,
461 .remove = armada_xp_pinctrl_remove,
464 module_platform_driver(armada_xp_pinctrl_driver);
466 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
467 MODULE_DESCRIPTION("Marvell Armada XP pinctrl driver");
468 MODULE_LICENSE("GPL v2");