2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/of_device.h>
26 #include <linux/of_address.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 /* Since we request GPIOs from ourself */
32 #include <linux/pinctrl/consumer.h>
33 #include "pinctrl-nomadik.h"
35 #include "../pinctrl-utils.h"
38 * The GPIO module in the Nomadik family of Systems-on-Chip is an
39 * AMBA device, managing 32 pins and alternate functions. The logic block
40 * is currently used in the Nomadik and ux500.
42 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
46 * pin configurations are represented by 32-bit integers:
48 * bit 0.. 8 - Pin Number (512 Pins Maximum)
49 * bit 9..10 - Alternate Function Selection
50 * bit 11..12 - Pull up/down state
51 * bit 13 - Sleep mode behaviour
53 * bit 15 - Value (if output)
54 * bit 16..18 - SLPM pull up/down state
55 * bit 19..20 - SLPM direction
56 * bit 21..22 - SLPM Value (if output)
57 * bit 23..25 - PDIS value (if input)
61 * to facilitate the definition, the following macros are provided
63 * PIN_CFG_DEFAULT - default config (0):
64 * pull up/down = disabled
65 * sleep mode = input/wakeup
68 * SLPM direction = same as normal
69 * SLPM pull = same as normal
70 * SLPM value = same as normal
72 * PIN_CFG - default config with alternate function
75 typedef unsigned long pin_cfg_t;
77 #define PIN_NUM_MASK 0x1ff
78 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
80 #define PIN_ALT_SHIFT 9
81 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
82 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
83 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
84 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
85 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
86 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
88 #define PIN_PULL_SHIFT 11
89 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
90 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
91 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
92 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
93 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
95 #define PIN_SLPM_SHIFT 13
96 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
97 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
98 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
99 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
100 /* These two replace the above in DB8500v2+ */
101 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
102 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
103 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
105 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
106 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
108 #define PIN_DIR_SHIFT 14
109 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
110 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
111 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
112 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
114 #define PIN_VAL_SHIFT 15
115 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
116 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
117 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
118 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
120 #define PIN_SLPM_PULL_SHIFT 16
121 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
122 #define PIN_SLPM_PULL(x) \
123 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
124 #define PIN_SLPM_PULL_NONE \
125 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
126 #define PIN_SLPM_PULL_UP \
127 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
128 #define PIN_SLPM_PULL_DOWN \
129 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
131 #define PIN_SLPM_DIR_SHIFT 19
132 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
133 #define PIN_SLPM_DIR(x) \
134 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
135 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
136 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
138 #define PIN_SLPM_VAL_SHIFT 21
139 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
140 #define PIN_SLPM_VAL(x) \
141 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
142 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
143 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
145 #define PIN_SLPM_PDIS_SHIFT 23
146 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
147 #define PIN_SLPM_PDIS(x) \
148 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
149 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
150 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
151 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
153 #define PIN_LOWEMI_SHIFT 25
154 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
155 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
156 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
157 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
159 #define PIN_GPIOMODE_SHIFT 26
160 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
161 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
162 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
163 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
165 #define PIN_SLEEPMODE_SHIFT 27
166 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
167 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
168 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
169 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
172 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
173 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
174 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
175 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
176 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
177 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
179 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
180 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
181 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
182 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
183 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
185 #define PIN_CFG_DEFAULT (0)
187 #define PIN_CFG(num, alt) \
189 (PIN_NUM(num) | PIN_##alt))
191 #define PIN_CFG_INPUT(num, alt, pull) \
193 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
195 #define PIN_CFG_OUTPUT(num, alt, val) \
197 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
200 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
201 * the "gpio" namespace for generic and cross-machine functions
204 #define GPIO_BLOCK_SHIFT 5
205 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
207 /* Register in the logic block */
208 #define NMK_GPIO_DAT 0x00
209 #define NMK_GPIO_DATS 0x04
210 #define NMK_GPIO_DATC 0x08
211 #define NMK_GPIO_PDIS 0x0c
212 #define NMK_GPIO_DIR 0x10
213 #define NMK_GPIO_DIRS 0x14
214 #define NMK_GPIO_DIRC 0x18
215 #define NMK_GPIO_SLPC 0x1c
216 #define NMK_GPIO_AFSLA 0x20
217 #define NMK_GPIO_AFSLB 0x24
218 #define NMK_GPIO_LOWEMI 0x28
220 #define NMK_GPIO_RIMSC 0x40
221 #define NMK_GPIO_FIMSC 0x44
222 #define NMK_GPIO_IS 0x48
223 #define NMK_GPIO_IC 0x4c
224 #define NMK_GPIO_RWIMSC 0x50
225 #define NMK_GPIO_FWIMSC 0x54
226 #define NMK_GPIO_WKS 0x58
227 /* These appear in DB8540 and later ASICs */
228 #define NMK_GPIO_EDGELEVEL 0x5C
229 #define NMK_GPIO_LEVEL 0x60
232 /* Pull up/down values */
242 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
243 NMK_GPIO_SLPM_NOCHANGE,
244 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
247 struct nmk_gpio_chip {
248 struct gpio_chip chip;
249 struct irq_chip irqchip;
253 unsigned int parent_irq;
254 int latent_parent_irq;
255 u32 (*get_latent_status)(unsigned int bank);
256 void (*set_ioforce)(bool enable);
259 /* Keep track of configured edges */
272 * struct nmk_pinctrl - state container for the Nomadik pin controller
273 * @dev: containing device pointer
274 * @pctl: corresponding pin controller device
275 * @soc: SoC data for this specific chip
276 * @prcm_base: PRCM register range virtual base
280 struct pinctrl_dev *pctl;
281 const struct nmk_pinctrl_soc_data *soc;
282 void __iomem *prcm_base;
285 static struct nmk_gpio_chip *
286 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
288 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
290 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
292 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
293 unsigned offset, int gpio_mode)
295 u32 bit = 1 << offset;
298 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
299 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
300 if (gpio_mode & NMK_GPIO_ALT_A)
302 if (gpio_mode & NMK_GPIO_ALT_B)
304 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
305 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
308 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
309 unsigned offset, enum nmk_gpio_slpm mode)
311 u32 bit = 1 << offset;
314 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
315 if (mode == NMK_GPIO_SLPM_NOCHANGE)
319 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
322 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
323 unsigned offset, enum nmk_gpio_pull pull)
325 u32 bit = 1 << offset;
328 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
329 if (pull == NMK_GPIO_PULL_NONE) {
331 nmk_chip->pull_up &= ~bit;
336 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
338 if (pull == NMK_GPIO_PULL_UP) {
339 nmk_chip->pull_up |= bit;
340 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
341 } else if (pull == NMK_GPIO_PULL_DOWN) {
342 nmk_chip->pull_up &= ~bit;
343 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
347 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
348 unsigned offset, bool lowemi)
350 u32 bit = BIT(offset);
351 bool enabled = nmk_chip->lowemi & bit;
353 if (lowemi == enabled)
357 nmk_chip->lowemi |= bit;
359 nmk_chip->lowemi &= ~bit;
361 writel_relaxed(nmk_chip->lowemi,
362 nmk_chip->addr + NMK_GPIO_LOWEMI);
365 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
368 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
371 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
372 unsigned offset, int val)
375 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
377 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
380 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
381 unsigned offset, int val)
383 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
384 __nmk_gpio_set_output(nmk_chip, offset, val);
387 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
388 unsigned offset, int gpio_mode,
391 u32 rwimsc = nmk_chip->rwimsc;
392 u32 fwimsc = nmk_chip->fwimsc;
394 if (glitch && nmk_chip->set_ioforce) {
395 u32 bit = BIT(offset);
397 /* Prevent spurious wakeups */
398 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
399 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
401 nmk_chip->set_ioforce(true);
404 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
406 if (glitch && nmk_chip->set_ioforce) {
407 nmk_chip->set_ioforce(false);
409 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
410 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
415 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
417 u32 falling = nmk_chip->fimsc & BIT(offset);
418 u32 rising = nmk_chip->rimsc & BIT(offset);
419 int gpio = nmk_chip->chip.base + offset;
420 int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset);
421 struct irq_data *d = irq_get_irq_data(irq);
423 if (!rising && !falling)
426 if (!d || !irqd_irq_disabled(d))
430 nmk_chip->rimsc &= ~BIT(offset);
431 writel_relaxed(nmk_chip->rimsc,
432 nmk_chip->addr + NMK_GPIO_RIMSC);
436 nmk_chip->fimsc &= ~BIT(offset);
437 writel_relaxed(nmk_chip->fimsc,
438 nmk_chip->addr + NMK_GPIO_FIMSC);
441 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
444 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
449 val = ((val & ~mask) | (value & mask));
453 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
454 unsigned offset, unsigned alt_num)
460 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
461 const u16 *gpiocr_regs;
463 if (!npct->prcm_base)
466 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
467 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
472 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
473 if (npct->soc->altcx_pins[i].pin == offset)
476 if (i == npct->soc->npins_altcx) {
477 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
482 pin_desc = npct->soc->altcx_pins + i;
483 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
486 * If alt_num is NULL, just clear current ALTCx selection
487 * to make sure we come back to a pure ALTC selection
490 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
491 if (pin_desc->altcx[i].used == true) {
492 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
493 bit = pin_desc->altcx[i].control_bit;
494 if (readl(npct->prcm_base + reg) & BIT(bit)) {
495 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
497 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
505 alt_index = alt_num - 1;
506 if (pin_desc->altcx[alt_index].used == false) {
508 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
514 * Check if any other ALTCx functions are activated on this pin
515 * and disable it first.
517 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
520 if (pin_desc->altcx[i].used == true) {
521 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
522 bit = pin_desc->altcx[i].control_bit;
523 if (readl(npct->prcm_base + reg) & BIT(bit)) {
524 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
526 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
532 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
533 bit = pin_desc->altcx[alt_index].control_bit;
534 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
535 offset, alt_index+1);
536 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
540 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
541 * - Save SLPM registers
542 * - Set SLPM=0 for the IOs you want to switch and others to 1
543 * - Configure the GPIO registers for the IOs that are being switched
545 * - Modify the AFLSA/B registers for the IOs that are being switched
547 * - Restore SLPM registers
548 * - Any spurious wake up event during switch sequence to be ignored and
551 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
555 for (i = 0; i < NUM_BANKS; i++) {
556 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
557 unsigned int temp = slpm[i];
562 clk_enable(chip->clk);
564 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
565 writel(temp, chip->addr + NMK_GPIO_SLPC);
569 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
573 for (i = 0; i < NUM_BANKS; i++) {
574 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
579 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
581 clk_disable(chip->clk);
585 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
590 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
591 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
592 const u16 *gpiocr_regs;
594 if (!npct->prcm_base)
595 return NMK_GPIO_ALT_C;
597 for (i = 0; i < npct->soc->npins_altcx; i++) {
598 if (npct->soc->altcx_pins[i].pin == gpio)
601 if (i == npct->soc->npins_altcx)
602 return NMK_GPIO_ALT_C;
604 pin_desc = npct->soc->altcx_pins + i;
605 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
606 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
607 if (pin_desc->altcx[i].used == true) {
608 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
609 bit = pin_desc->altcx[i].control_bit;
610 if (readl(npct->prcm_base + reg) & BIT(bit))
611 return NMK_GPIO_ALT_C+i+1;
614 return NMK_GPIO_ALT_C;
617 int nmk_gpio_get_mode(int gpio)
619 struct nmk_gpio_chip *nmk_chip;
620 u32 afunc, bfunc, bit;
622 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
626 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
628 clk_enable(nmk_chip->clk);
630 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
631 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
633 clk_disable(nmk_chip->clk);
635 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
637 EXPORT_SYMBOL(nmk_gpio_get_mode);
641 static inline int nmk_gpio_get_bitmask(int gpio)
643 return 1 << (gpio % NMK_GPIO_PER_CHIP);
646 static void nmk_gpio_irq_ack(struct irq_data *d)
648 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
649 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
651 clk_enable(nmk_chip->clk);
652 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
653 clk_disable(nmk_chip->clk);
656 enum nmk_gpio_irq_type {
661 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
662 int gpio, enum nmk_gpio_irq_type which,
665 u32 bitmask = nmk_gpio_get_bitmask(gpio);
671 if (which == NORMAL) {
672 rimscreg = NMK_GPIO_RIMSC;
673 fimscreg = NMK_GPIO_FIMSC;
674 rimscval = &nmk_chip->rimsc;
675 fimscval = &nmk_chip->fimsc;
677 rimscreg = NMK_GPIO_RWIMSC;
678 fimscreg = NMK_GPIO_FWIMSC;
679 rimscval = &nmk_chip->rwimsc;
680 fimscval = &nmk_chip->fwimsc;
683 /* we must individually set/clear the two edges */
684 if (nmk_chip->edge_rising & bitmask) {
686 *rimscval |= bitmask;
688 *rimscval &= ~bitmask;
689 writel(*rimscval, nmk_chip->addr + rimscreg);
691 if (nmk_chip->edge_falling & bitmask) {
693 *fimscval |= bitmask;
695 *fimscval &= ~bitmask;
696 writel(*fimscval, nmk_chip->addr + fimscreg);
700 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
704 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
705 * disabled, since setting SLPM to 1 increases power consumption, and
706 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
708 if (nmk_chip->sleepmode && on) {
709 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
710 NMK_GPIO_SLPM_WAKEUP_ENABLE);
713 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
716 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
718 struct nmk_gpio_chip *nmk_chip;
722 nmk_chip = irq_data_get_irq_chip_data(d);
723 bitmask = nmk_gpio_get_bitmask(d->hwirq);
727 clk_enable(nmk_chip->clk);
728 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
729 spin_lock(&nmk_chip->lock);
731 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
733 if (!(nmk_chip->real_wake & bitmask))
734 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
736 spin_unlock(&nmk_chip->lock);
737 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
738 clk_disable(nmk_chip->clk);
743 static void nmk_gpio_irq_mask(struct irq_data *d)
745 nmk_gpio_irq_maskunmask(d, false);
748 static void nmk_gpio_irq_unmask(struct irq_data *d)
750 nmk_gpio_irq_maskunmask(d, true);
753 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
755 struct nmk_gpio_chip *nmk_chip;
759 nmk_chip = irq_data_get_irq_chip_data(d);
762 bitmask = nmk_gpio_get_bitmask(d->hwirq);
764 clk_enable(nmk_chip->clk);
765 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
766 spin_lock(&nmk_chip->lock);
768 if (irqd_irq_disabled(d))
769 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
772 nmk_chip->real_wake |= bitmask;
774 nmk_chip->real_wake &= ~bitmask;
776 spin_unlock(&nmk_chip->lock);
777 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
778 clk_disable(nmk_chip->clk);
783 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
785 bool enabled = !irqd_irq_disabled(d);
786 bool wake = irqd_is_wakeup_set(d);
787 struct nmk_gpio_chip *nmk_chip;
791 nmk_chip = irq_data_get_irq_chip_data(d);
792 bitmask = nmk_gpio_get_bitmask(d->hwirq);
795 if (type & IRQ_TYPE_LEVEL_HIGH)
797 if (type & IRQ_TYPE_LEVEL_LOW)
800 clk_enable(nmk_chip->clk);
801 spin_lock_irqsave(&nmk_chip->lock, flags);
804 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
807 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
809 nmk_chip->edge_rising &= ~bitmask;
810 if (type & IRQ_TYPE_EDGE_RISING)
811 nmk_chip->edge_rising |= bitmask;
813 nmk_chip->edge_falling &= ~bitmask;
814 if (type & IRQ_TYPE_EDGE_FALLING)
815 nmk_chip->edge_falling |= bitmask;
818 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
821 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
823 spin_unlock_irqrestore(&nmk_chip->lock, flags);
824 clk_disable(nmk_chip->clk);
829 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
831 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
833 clk_enable(nmk_chip->clk);
834 nmk_gpio_irq_unmask(d);
838 static void nmk_gpio_irq_shutdown(struct irq_data *d)
840 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
842 nmk_gpio_irq_mask(d);
843 clk_disable(nmk_chip->clk);
846 static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status)
848 struct irq_chip *host_chip = irq_desc_get_chip(desc);
849 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
851 chained_irq_enter(host_chip, desc);
854 int bit = __ffs(status);
856 generic_handle_irq(irq_find_mapping(chip->irqdomain, bit));
860 chained_irq_exit(host_chip, desc);
863 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
865 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
866 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
869 clk_enable(nmk_chip->clk);
870 status = readl(nmk_chip->addr + NMK_GPIO_IS);
871 clk_disable(nmk_chip->clk);
873 __nmk_gpio_irq_handler(desc, status);
876 static void nmk_gpio_latent_irq_handler(unsigned int irq, struct irq_desc *desc)
878 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
879 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
880 u32 status = nmk_chip->get_latent_status(nmk_chip->bank);
882 __nmk_gpio_irq_handler(desc, status);
887 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
890 * Map back to global GPIO space and request muxing, the direction
891 * parameter does not matter for this controller.
893 int gpio = chip->base + offset;
895 return pinctrl_request_gpio(gpio);
898 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
900 int gpio = chip->base + offset;
902 pinctrl_free_gpio(gpio);
905 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
907 struct nmk_gpio_chip *nmk_chip =
908 container_of(chip, struct nmk_gpio_chip, chip);
910 clk_enable(nmk_chip->clk);
912 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
914 clk_disable(nmk_chip->clk);
919 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
921 struct nmk_gpio_chip *nmk_chip =
922 container_of(chip, struct nmk_gpio_chip, chip);
923 u32 bit = 1 << offset;
926 clk_enable(nmk_chip->clk);
928 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
930 clk_disable(nmk_chip->clk);
935 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
938 struct nmk_gpio_chip *nmk_chip =
939 container_of(chip, struct nmk_gpio_chip, chip);
941 clk_enable(nmk_chip->clk);
943 __nmk_gpio_set_output(nmk_chip, offset, val);
945 clk_disable(nmk_chip->clk);
948 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
951 struct nmk_gpio_chip *nmk_chip =
952 container_of(chip, struct nmk_gpio_chip, chip);
954 clk_enable(nmk_chip->clk);
956 __nmk_gpio_make_output(nmk_chip, offset, val);
958 clk_disable(nmk_chip->clk);
963 #ifdef CONFIG_DEBUG_FS
965 #include <linux/seq_file.h>
967 static void nmk_gpio_dbg_show_one(struct seq_file *s,
968 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
969 unsigned offset, unsigned gpio)
971 const char *label = gpiochip_is_requested(chip, offset);
972 struct nmk_gpio_chip *nmk_chip =
973 container_of(chip, struct nmk_gpio_chip, chip);
978 u32 bit = 1 << offset;
979 const char *modes[] = {
980 [NMK_GPIO_ALT_GPIO] = "gpio",
981 [NMK_GPIO_ALT_A] = "altA",
982 [NMK_GPIO_ALT_B] = "altB",
983 [NMK_GPIO_ALT_C] = "altC",
984 [NMK_GPIO_ALT_C+1] = "altC1",
985 [NMK_GPIO_ALT_C+2] = "altC2",
986 [NMK_GPIO_ALT_C+3] = "altC3",
987 [NMK_GPIO_ALT_C+4] = "altC4",
989 const char *pulls[] = {
995 clk_enable(nmk_chip->clk);
996 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
997 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
998 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit);
999 mode = nmk_gpio_get_mode(gpio);
1000 if ((mode == NMK_GPIO_ALT_C) && pctldev)
1001 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1004 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
1007 data_out ? "hi" : "lo",
1008 (mode < 0) ? "unknown" : modes[mode]);
1010 int irq = gpio_to_irq(gpio);
1011 struct irq_desc *desc = irq_to_desc(irq);
1015 pullidx = data_out ? 1 : 2;
1017 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
1021 (mode < 0) ? "unknown" : modes[mode]);
1023 * This races with request_irq(), set_irq_type(),
1024 * and set_irq_wake() ... but those are "rare".
1026 if (irq > 0 && desc && desc->action) {
1028 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1030 if (nmk_chip->edge_rising & bitmask)
1031 trigger = "edge-rising";
1032 else if (nmk_chip->edge_falling & bitmask)
1033 trigger = "edge-falling";
1035 trigger = "edge-undefined";
1037 seq_printf(s, " irq-%d %s%s",
1039 irqd_is_wakeup_set(&desc->irq_data)
1043 clk_disable(nmk_chip->clk);
1046 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1049 unsigned gpio = chip->base;
1051 for (i = 0; i < chip->ngpio; i++, gpio++) {
1052 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1053 seq_printf(s, "\n");
1058 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1059 struct pinctrl_dev *pctldev,
1060 struct gpio_chip *chip,
1061 unsigned offset, unsigned gpio)
1064 #define nmk_gpio_dbg_show NULL
1067 void nmk_gpio_clocks_enable(void)
1071 for (i = 0; i < NUM_BANKS; i++) {
1072 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1077 clk_enable(chip->clk);
1081 void nmk_gpio_clocks_disable(void)
1085 for (i = 0; i < NUM_BANKS; i++) {
1086 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1091 clk_disable(chip->clk);
1096 * Called from the suspend/resume path to only keep the real wakeup interrupts
1097 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1098 * and not the rest of the interrupts which we needed to have as wakeups for
1101 * PM ops are not used since this needs to be done at the end, after all the
1102 * other drivers are done with their suspend callbacks.
1104 void nmk_gpio_wakeups_suspend(void)
1108 for (i = 0; i < NUM_BANKS; i++) {
1109 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1114 clk_enable(chip->clk);
1116 writel(chip->rwimsc & chip->real_wake,
1117 chip->addr + NMK_GPIO_RWIMSC);
1118 writel(chip->fwimsc & chip->real_wake,
1119 chip->addr + NMK_GPIO_FWIMSC);
1121 clk_disable(chip->clk);
1125 void nmk_gpio_wakeups_resume(void)
1129 for (i = 0; i < NUM_BANKS; i++) {
1130 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1135 clk_enable(chip->clk);
1137 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1138 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1140 clk_disable(chip->clk);
1145 * Read the pull up/pull down status.
1146 * A bit set in 'pull_up' means that pull up
1147 * is selected if pull is enabled in PDIS register.
1148 * Note: only pull up/down set via this driver can
1149 * be detected due to HW limitations.
1151 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1153 if (gpio_bank < NUM_BANKS) {
1154 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1159 *pull_up = chip->pull_up;
1163 static int nmk_gpio_probe(struct platform_device *dev)
1165 struct device_node *np = dev->dev.of_node;
1166 struct nmk_gpio_chip *nmk_chip;
1167 struct gpio_chip *chip;
1168 struct irq_chip *irqchip;
1169 struct resource *res;
1172 bool supports_sleepmode;
1177 if (of_get_property(np, "st,supports-sleepmode", NULL))
1178 supports_sleepmode = true;
1180 supports_sleepmode = false;
1182 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1183 dev_err(&dev->dev, "gpio-bank property not found\n");
1187 irq = platform_get_irq(dev, 0);
1191 /* It's OK for this IRQ not to be present */
1192 latent_irq = platform_get_irq(dev, 1);
1194 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1195 base = devm_ioremap_resource(&dev->dev, res);
1197 return PTR_ERR(base);
1199 clk = devm_clk_get(&dev->dev, NULL);
1201 return PTR_ERR(clk);
1204 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1209 * The virt address in nmk_chip->addr is in the nomadik register space,
1210 * so we can simply convert the resource address, without remapping
1212 nmk_chip->bank = dev->id;
1213 nmk_chip->clk = clk;
1214 nmk_chip->addr = base;
1215 nmk_chip->parent_irq = irq;
1216 nmk_chip->latent_parent_irq = latent_irq;
1217 nmk_chip->sleepmode = supports_sleepmode;
1218 spin_lock_init(&nmk_chip->lock);
1220 chip = &nmk_chip->chip;
1221 chip->request = nmk_gpio_request;
1222 chip->free = nmk_gpio_free;
1223 chip->direction_input = nmk_gpio_make_input;
1224 chip->get = nmk_gpio_get_input;
1225 chip->direction_output = nmk_gpio_make_output;
1226 chip->set = nmk_gpio_set_output;
1227 chip->dbg_show = nmk_gpio_dbg_show;
1228 chip->can_sleep = false;
1229 chip->base = dev->id * NMK_GPIO_PER_CHIP;
1230 chip->ngpio = NMK_GPIO_PER_CHIP;
1231 chip->label = dev_name(&dev->dev);
1232 chip->dev = &dev->dev;
1233 chip->owner = THIS_MODULE;
1235 irqchip = &nmk_chip->irqchip;
1236 irqchip->irq_ack = nmk_gpio_irq_ack;
1237 irqchip->irq_mask = nmk_gpio_irq_mask;
1238 irqchip->irq_unmask = nmk_gpio_irq_unmask;
1239 irqchip->irq_set_type = nmk_gpio_irq_set_type;
1240 irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
1241 irqchip->irq_startup = nmk_gpio_irq_startup;
1242 irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
1243 irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
1244 irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
1247 chip->base + chip->ngpio - 1);
1249 clk_enable(nmk_chip->clk);
1250 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1251 clk_disable(nmk_chip->clk);
1254 ret = gpiochip_add(&nmk_chip->chip);
1258 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1260 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1262 platform_set_drvdata(dev, nmk_chip);
1265 * Let the generic code handle this edge IRQ, the the chained
1266 * handler will perform the actual work of handling the parent
1269 ret = gpiochip_irqchip_add(chip,
1273 IRQ_TYPE_EDGE_FALLING);
1275 dev_err(&dev->dev, "could not add irqchip\n");
1276 gpiochip_remove(&nmk_chip->chip);
1279 /* Then register the chain on the parent IRQ */
1280 gpiochip_set_chained_irqchip(chip,
1282 nmk_chip->parent_irq,
1283 nmk_gpio_irq_handler);
1284 if (nmk_chip->latent_parent_irq > 0)
1285 gpiochip_set_chained_irqchip(chip,
1287 nmk_chip->latent_parent_irq,
1288 nmk_gpio_latent_irq_handler);
1290 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1295 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1297 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1299 return npct->soc->ngroups;
1302 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1305 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1307 return npct->soc->groups[selector].name;
1310 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1311 const unsigned **pins,
1314 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1316 *pins = npct->soc->groups[selector].pins;
1317 *num_pins = npct->soc->groups[selector].npins;
1321 static struct pinctrl_gpio_range *
1322 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1324 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1327 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1328 struct pinctrl_gpio_range *range;
1330 range = &npct->soc->gpio_ranges[i];
1331 if (offset >= range->pin_base &&
1332 offset <= (range->pin_base + range->npins - 1))
1338 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1341 struct pinctrl_gpio_range *range;
1342 struct gpio_chip *chip;
1344 range = nmk_match_gpio_range(pctldev, offset);
1345 if (!range || !range->gc) {
1346 seq_printf(s, "invalid pin offset");
1350 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1353 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1354 unsigned *num_maps, const char *group,
1355 const char *function)
1357 if (*num_maps == *reserved_maps)
1360 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1361 (*map)[*num_maps].data.mux.group = group;
1362 (*map)[*num_maps].data.mux.function = function;
1368 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1369 unsigned *reserved_maps,
1370 unsigned *num_maps, const char *group,
1371 unsigned long *configs, unsigned num_configs)
1373 unsigned long *dup_configs;
1375 if (*num_maps == *reserved_maps)
1378 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1383 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1385 (*map)[*num_maps].data.configs.group_or_pin = group;
1386 (*map)[*num_maps].data.configs.configs = dup_configs;
1387 (*map)[*num_maps].data.configs.num_configs = num_configs;
1393 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1394 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1395 .size = ARRAY_SIZE(y), }
1397 static const unsigned long nmk_pin_input_modes[] = {
1403 static const unsigned long nmk_pin_output_modes[] = {
1409 static const unsigned long nmk_pin_sleep_modes[] = {
1410 PIN_SLEEPMODE_DISABLED,
1411 PIN_SLEEPMODE_ENABLED,
1414 static const unsigned long nmk_pin_sleep_input_modes[] = {
1415 PIN_SLPM_INPUT_NOPULL,
1416 PIN_SLPM_INPUT_PULLUP,
1417 PIN_SLPM_INPUT_PULLDOWN,
1421 static const unsigned long nmk_pin_sleep_output_modes[] = {
1422 PIN_SLPM_OUTPUT_LOW,
1423 PIN_SLPM_OUTPUT_HIGH,
1424 PIN_SLPM_DIR_OUTPUT,
1427 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1428 PIN_SLPM_WAKEUP_DISABLE,
1429 PIN_SLPM_WAKEUP_ENABLE,
1432 static const unsigned long nmk_pin_gpio_modes[] = {
1433 PIN_GPIOMODE_DISABLED,
1434 PIN_GPIOMODE_ENABLED,
1437 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1438 PIN_SLPM_PDIS_DISABLED,
1439 PIN_SLPM_PDIS_ENABLED,
1442 struct nmk_cfg_param {
1443 const char *property;
1444 unsigned long config;
1445 const unsigned long *choice;
1449 static const struct nmk_cfg_param nmk_cfg_params[] = {
1450 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1451 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1452 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1453 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1454 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1455 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1456 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1457 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1460 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1464 if (nmk_cfg_params[index].choice == NULL)
1465 *config = nmk_cfg_params[index].config;
1467 /* test if out of range */
1468 if (val < nmk_cfg_params[index].size) {
1469 *config = nmk_cfg_params[index].config |
1470 nmk_cfg_params[index].choice[val];
1476 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1479 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1481 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1482 for (i = 0; i < npct->soc->npins; i++)
1483 if (npct->soc->pins[i].number == pin_number)
1484 return npct->soc->pins[i].name;
1488 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1489 unsigned long *configs)
1491 bool has_config = 0;
1492 unsigned long cfg = 0;
1495 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1496 ret = of_property_read_u32(np,
1497 nmk_cfg_params[i].property, &val);
1498 if (ret != -EINVAL) {
1499 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1509 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1510 struct device_node *np,
1511 struct pinctrl_map **map,
1512 unsigned *reserved_maps,
1516 const char *function = NULL;
1517 unsigned long configs = 0;
1518 bool has_config = 0;
1519 struct property *prop;
1520 struct device_node *np_config;
1522 ret = of_property_read_string(np, "function", &function);
1526 ret = of_property_count_strings(np, "groups");
1530 ret = pinctrl_utils_reserve_map(pctldev, map,
1536 of_property_for_each_string(np, "groups", prop, group) {
1537 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1544 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1545 np_config = of_parse_phandle(np, "ste,config", 0);
1547 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1549 const char *gpio_name;
1552 ret = of_property_count_strings(np, "pins");
1555 ret = pinctrl_utils_reserve_map(pctldev, map,
1561 of_property_for_each_string(np, "pins", prop, pin) {
1562 gpio_name = nmk_find_pin_name(pctldev, pin);
1564 ret = nmk_dt_add_map_configs(map, reserved_maps,
1566 gpio_name, &configs, 1);
1576 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1577 struct device_node *np_config,
1578 struct pinctrl_map **map, unsigned *num_maps)
1580 unsigned reserved_maps;
1581 struct device_node *np;
1588 for_each_child_of_node(np_config, np) {
1589 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1590 &reserved_maps, num_maps);
1592 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
1600 static const struct pinctrl_ops nmk_pinctrl_ops = {
1601 .get_groups_count = nmk_get_groups_cnt,
1602 .get_group_name = nmk_get_group_name,
1603 .get_group_pins = nmk_get_group_pins,
1604 .pin_dbg_show = nmk_pin_dbg_show,
1605 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1606 .dt_free_map = pinctrl_utils_dt_free_map,
1609 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1611 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1613 return npct->soc->nfunctions;
1616 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1619 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1621 return npct->soc->functions[function].name;
1624 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1626 const char * const **groups,
1627 unsigned * const num_groups)
1629 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1631 *groups = npct->soc->functions[function].groups;
1632 *num_groups = npct->soc->functions[function].ngroups;
1637 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1640 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1641 const struct nmk_pingroup *g;
1642 static unsigned int slpm[NUM_BANKS];
1643 unsigned long flags = 0;
1648 g = &npct->soc->groups[group];
1650 if (g->altsetting < 0)
1653 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1656 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1657 * we may pass through an undesired state. In this case we take
1660 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1661 * - Save SLPM registers (since we have a shadow register in the
1662 * nmk_chip we're using that as backup)
1663 * - Set SLPM=0 for the IOs you want to switch and others to 1
1664 * - Configure the GPIO registers for the IOs that are being switched
1666 * - Modify the AFLSA/B registers for the IOs that are being switched
1668 * - Restore SLPM registers
1669 * - Any spurious wake up event during switch sequence to be ignored
1672 * We REALLY need to save ALL slpm registers, because the external
1673 * IOFORCE will switch *all* ports to their sleepmode setting to as
1674 * to avoid glitches. (Not just one port!)
1676 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1679 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1681 /* Initially don't put any pins to sleep when switching */
1682 memset(slpm, 0xff, sizeof(slpm));
1685 * Then mask the pins that need to be sleeping now when we're
1686 * switching to the ALT C function.
1688 for (i = 0; i < g->npins; i++)
1689 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1690 nmk_gpio_glitch_slpm_init(slpm);
1693 for (i = 0; i < g->npins; i++) {
1694 struct pinctrl_gpio_range *range;
1695 struct nmk_gpio_chip *nmk_chip;
1696 struct gpio_chip *chip;
1699 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1702 "invalid pin offset %d in group %s at index %d\n",
1703 g->pins[i], g->name, i);
1707 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1708 g->pins[i], g->name, i);
1712 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1713 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1715 clk_enable(nmk_chip->clk);
1716 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1718 * If the pin is switching to altfunc, and there was an
1719 * interrupt installed on it which has been lazy disabled,
1720 * actually mask the interrupt to prevent spurious interrupts
1721 * that would occur while the pin is under control of the
1722 * peripheral. Only SKE does this.
1724 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1726 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1727 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1728 clk_disable(nmk_chip->clk);
1731 * Call PRCM GPIOCR config function in case ALTC
1732 * has been selected:
1733 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1735 * - If selection is pure ALTC and previous selection was ALTCx,
1736 * then some bits in PRCM GPIOCR registers must be cleared.
1738 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1739 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1740 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1743 /* When all pins are successfully reconfigured we get here */
1748 nmk_gpio_glitch_slpm_restore(slpm);
1749 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1755 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1756 struct pinctrl_gpio_range *range,
1759 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1760 struct nmk_gpio_chip *nmk_chip;
1761 struct gpio_chip *chip;
1765 dev_err(npct->dev, "invalid range\n");
1769 dev_err(npct->dev, "missing GPIO chip in range\n");
1773 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1775 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1777 clk_enable(nmk_chip->clk);
1778 bit = offset % NMK_GPIO_PER_CHIP;
1779 /* There is no glitch when converting any pin to GPIO */
1780 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1781 clk_disable(nmk_chip->clk);
1786 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1787 struct pinctrl_gpio_range *range,
1790 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1792 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1793 /* Set the pin to some default state, GPIO is usually default */
1796 static const struct pinmux_ops nmk_pinmux_ops = {
1797 .get_functions_count = nmk_pmx_get_funcs_cnt,
1798 .get_function_name = nmk_pmx_get_func_name,
1799 .get_function_groups = nmk_pmx_get_func_groups,
1800 .set_mux = nmk_pmx_set,
1801 .gpio_request_enable = nmk_gpio_request_enable,
1802 .gpio_disable_free = nmk_gpio_disable_free,
1806 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1807 unsigned long *config)
1809 /* Not implemented */
1813 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1814 unsigned long *configs, unsigned num_configs)
1816 static const char *pullnames[] = {
1817 [NMK_GPIO_PULL_NONE] = "none",
1818 [NMK_GPIO_PULL_UP] = "up",
1819 [NMK_GPIO_PULL_DOWN] = "down",
1820 [3] /* illegal */ = "??"
1822 static const char *slpmnames[] = {
1823 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1824 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1826 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1827 struct nmk_gpio_chip *nmk_chip;
1828 struct pinctrl_gpio_range *range;
1829 struct gpio_chip *chip;
1832 int pull, slpm, output, val, i;
1833 bool lowemi, gpiomode, sleep;
1835 range = nmk_match_gpio_range(pctldev, pin);
1837 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1841 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1846 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1848 for (i = 0; i < num_configs; i++) {
1850 * The pin config contains pin number and altfunction fields,
1851 * here we just ignore that part. It's being handled by the
1852 * framework and pinmux callback respectively.
1854 cfg = (pin_cfg_t) configs[i];
1855 pull = PIN_PULL(cfg);
1856 slpm = PIN_SLPM(cfg);
1857 output = PIN_DIR(cfg);
1859 lowemi = PIN_LOWEMI(cfg);
1860 gpiomode = PIN_GPIOMODE(cfg);
1861 sleep = PIN_SLEEPMODE(cfg);
1864 int slpm_pull = PIN_SLPM_PULL(cfg);
1865 int slpm_output = PIN_SLPM_DIR(cfg);
1866 int slpm_val = PIN_SLPM_VAL(cfg);
1868 /* All pins go into GPIO mode at sleep */
1872 * The SLPM_* values are normal values + 1 to allow zero
1873 * to mean "same as normal".
1876 pull = slpm_pull - 1;
1878 output = slpm_output - 1;
1882 dev_dbg(nmk_chip->chip.dev,
1883 "pin %d: sleep pull %s, dir %s, val %s\n",
1885 slpm_pull ? pullnames[pull] : "same",
1886 slpm_output ? (output ? "output" : "input")
1888 slpm_val ? (val ? "high" : "low") : "same");
1891 dev_dbg(nmk_chip->chip.dev,
1892 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1893 pin, cfg, pullnames[pull], slpmnames[slpm],
1894 output ? "output " : "input",
1895 output ? (val ? "high" : "low") : "",
1896 lowemi ? "on" : "off");
1898 clk_enable(nmk_chip->clk);
1899 bit = pin % NMK_GPIO_PER_CHIP;
1901 /* No glitch when going to GPIO mode */
1902 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1904 __nmk_gpio_make_output(nmk_chip, bit, val);
1906 __nmk_gpio_make_input(nmk_chip, bit);
1907 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1909 /* TODO: isn't this only applicable on output pins? */
1910 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1912 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1913 clk_disable(nmk_chip->clk);
1914 } /* for each config */
1919 static const struct pinconf_ops nmk_pinconf_ops = {
1920 .pin_config_get = nmk_pin_config_get,
1921 .pin_config_set = nmk_pin_config_set,
1924 static struct pinctrl_desc nmk_pinctrl_desc = {
1925 .name = "pinctrl-nomadik",
1926 .pctlops = &nmk_pinctrl_ops,
1927 .pmxops = &nmk_pinmux_ops,
1928 .confops = &nmk_pinconf_ops,
1929 .owner = THIS_MODULE,
1932 static const struct of_device_id nmk_pinctrl_match[] = {
1934 .compatible = "stericsson,stn8815-pinctrl",
1935 .data = (void *)PINCTRL_NMK_STN8815,
1938 .compatible = "stericsson,db8500-pinctrl",
1939 .data = (void *)PINCTRL_NMK_DB8500,
1942 .compatible = "stericsson,db8540-pinctrl",
1943 .data = (void *)PINCTRL_NMK_DB8540,
1948 #ifdef CONFIG_PM_SLEEP
1949 static int nmk_pinctrl_suspend(struct device *dev)
1951 struct nmk_pinctrl *npct;
1953 npct = dev_get_drvdata(dev);
1957 return pinctrl_force_sleep(npct->pctl);
1960 static int nmk_pinctrl_resume(struct device *dev)
1962 struct nmk_pinctrl *npct;
1964 npct = dev_get_drvdata(dev);
1968 return pinctrl_force_default(npct->pctl);
1972 static int nmk_pinctrl_probe(struct platform_device *pdev)
1974 const struct of_device_id *match;
1975 struct device_node *np = pdev->dev.of_node;
1976 struct device_node *prcm_np;
1977 struct nmk_pinctrl *npct;
1978 unsigned int version = 0;
1981 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1985 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1988 version = (unsigned int) match->data;
1990 /* Poke in other ASIC variants here */
1991 if (version == PINCTRL_NMK_STN8815)
1992 nmk_pinctrl_stn8815_init(&npct->soc);
1993 if (version == PINCTRL_NMK_DB8500)
1994 nmk_pinctrl_db8500_init(&npct->soc);
1995 if (version == PINCTRL_NMK_DB8540)
1996 nmk_pinctrl_db8540_init(&npct->soc);
1998 prcm_np = of_parse_phandle(np, "prcm", 0);
2000 npct->prcm_base = of_iomap(prcm_np, 0);
2001 if (!npct->prcm_base) {
2002 if (version == PINCTRL_NMK_STN8815) {
2003 dev_info(&pdev->dev,
2005 "assuming no ALT-Cx control is available\n");
2007 dev_err(&pdev->dev, "missing PRCM base address\n");
2013 * We need all the GPIO drivers to probe FIRST, or we will not be able
2014 * to obtain references to the struct gpio_chip * for them, and we
2015 * need this to proceed.
2017 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
2018 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
2019 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
2020 return -EPROBE_DEFER;
2022 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
2025 nmk_pinctrl_desc.pins = npct->soc->pins;
2026 nmk_pinctrl_desc.npins = npct->soc->npins;
2027 npct->dev = &pdev->dev;
2029 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
2030 if (IS_ERR(npct->pctl)) {
2031 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
2032 return PTR_ERR(npct->pctl);
2035 /* We will handle a range of GPIO pins */
2036 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
2037 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
2039 platform_set_drvdata(pdev, npct);
2040 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
2045 static const struct of_device_id nmk_gpio_match[] = {
2046 { .compatible = "st,nomadik-gpio", },
2050 static struct platform_driver nmk_gpio_driver = {
2053 .of_match_table = nmk_gpio_match,
2055 .probe = nmk_gpio_probe,
2058 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
2059 nmk_pinctrl_suspend,
2060 nmk_pinctrl_resume);
2062 static struct platform_driver nmk_pinctrl_driver = {
2064 .name = "pinctrl-nomadik",
2065 .of_match_table = nmk_pinctrl_match,
2066 .pm = &nmk_pinctrl_pm_ops,
2068 .probe = nmk_pinctrl_probe,
2071 static int __init nmk_gpio_init(void)
2075 ret = platform_driver_register(&nmk_gpio_driver);
2078 return platform_driver_register(&nmk_pinctrl_driver);
2081 core_initcall(nmk_gpio_init);
2083 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
2084 MODULE_DESCRIPTION("Nomadik GPIO Driver");
2085 MODULE_LICENSE("GPL");