2 * Pinctrl Driver for ADI GPIO2 controller
4 * Copyright 2007-2013 Analog Devices Inc.
6 * Licensed under the GPLv2 or later
9 #include <linux/bitops.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
12 #include <linux/err.h>
13 #include <linux/debugfs.h>
14 #include <linux/seq_file.h>
15 #include <linux/irq.h>
16 #include <linux/platform_data/pinctrl-adi2.h>
17 #include <linux/irqdomain.h>
18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/pinctrl/machine.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/gpio.h>
25 #include <asm/portmux.h>
26 #include "pinctrl-adi2.h"
30 According to the BF54x HRM, pint means "pin interrupt".
31 http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf
33 ADSP-BF54x processor Blackfin processors have four SIC interrupt chan-
34 nels dedicated to pin interrupt purposes. These channels are managed by
35 four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx
36 block can sense to up to 32 pins. While PINT0 and PINT1 can sense the
37 pins of port A and port B, PINT2 and PINT3 manage all the pins from port
38 C to port J as shown in Figure 9-2.
41 The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and
42 upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi-
43 plexers shown in Figure 9-3. Lower half units of eight pins can be
44 forwarded to either byte 0 or byte 2 of either associated PINTx block.
45 Upper half units can be forwarded to either byte 1 or byte 3 of the pin
46 interrupt blocks, without further restrictions.
48 All MMR registers in the pin interrupt module are 32 bits wide. To simply the
49 mapping logic, this driver only maps a 16-bit gpio port to the upper or lower
50 16 bits of a PINTx block. You can find the Figure 9-3 on page 583.
52 Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map
53 to one PINT device. Two in "struct gpio_pint" are used to ease the PINT
56 The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ
57 domain pointer in domain[0]. The IRQ domain pointer of the other bank is set
58 to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out
59 the current domain pointer according to whether the interrupt request mask
60 is in lower 16 bits (domain[0]) or upper 16bits (domain[1]).
62 A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO
63 port devices can be mapped to the same PINT device.
67 static LIST_HEAD(adi_pint_list);
68 static LIST_HEAD(adi_gpio_port_list);
70 #define DRIVER_NAME "pinctrl-adi2"
72 #define PINT_HI_OFFSET 16
75 * struct gpio_port_saved - GPIO port registers that should be saved between
76 * power suspend and resume operations.
78 * @fer: PORTx_FER register
79 * @data: PORTx_DATA register
80 * @dir: PORTx_DIR register
81 * @inen: PORTx_INEN register
82 * @mux: PORTx_MUX register
84 struct gpio_port_saved {
93 * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO
94 * banks can be mapped into one Pin interrupt controller.
96 * @node: All gpio_pint instances are added to a global list.
97 * @base: PINT device register base address
98 * @irq: IRQ of the PINT device, it is the parent IRQ of all
99 * GPIO IRQs mapping to this device.
100 * @domain: [0] irq domain of the gpio port, whose hardware interrupts are
101 * mapping to the low 16-bit of the pint registers.
102 * [1] irq domain of the gpio port, whose hardware interrupts are
103 * mapping to the high 16-bit of the pint registers.
104 * @regs: address pointer to the PINT device
105 * @map_count: No more than 2 GPIO banks can be mapped to this PINT device.
106 * @lock: This lock make sure the irq_chip operations to one PINT device
107 * for different GPIO interrrupts are atomic.
108 * @pint_map_port: Set up the mapping between one PINT device and
109 * multiple GPIO banks.
112 struct list_head node;
115 struct irq_domain *domain[2];
116 struct gpio_pint_regs *regs;
117 struct adi_pm_pint_save saved_data;
121 int (*pint_map_port)(struct gpio_pint *pint, bool assign,
122 u8 map, struct irq_domain *domain);
128 * @dev: a pointer back to containing device
129 * @pctl: the pinctrl device
130 * @soc: SoC data for this specific chip
134 struct pinctrl_dev *pctl;
135 const struct adi_pinctrl_soc_data *soc;
139 * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped
140 * into one pin interrupt controller.
142 * @node: All gpio_port instances are added to a list.
143 * @base: GPIO bank device register base address
144 * @irq_base: base IRQ of the GPIO bank device
145 * @width: PIN number of the GPIO bank device
146 * @regs: address pointer to the GPIO bank device
147 * @saved_data: registers that should be saved between PM operations.
148 * @dev: device structure of this GPIO bank
149 * @pint: GPIO PINT device that this GPIO bank mapped to
150 * @pint_map: GIOP bank mapping code in PINT device
151 * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A
152 * GPIO bank can be mapped into either low 16 bits[0] or high 16
153 * bits[1] of each PINT register.
154 * @lock: This lock make sure the irq_chip operations to one PINT device
155 * for different GPIO interrrupts are atomic.
156 * @chip: abstract a GPIO controller
157 * @domain: The irq domain owned by the GPIO port.
158 * @rsvmap: Reservation map array for each pin in the GPIO bank
161 struct list_head node;
163 unsigned int irq_base;
165 struct gpio_port_t *regs;
166 struct gpio_port_saved saved_data;
169 struct gpio_pint *pint;
174 struct gpio_chip chip;
175 struct irq_domain *domain;
178 static inline u8 pin_to_offset(struct pinctrl_gpio_range *range, unsigned pin)
180 return pin - range->pin_base;
183 static inline u32 hwirq_to_pintbit(struct gpio_port *port, int hwirq)
185 return port->pint_assign ? BIT(hwirq) << PINT_HI_OFFSET : BIT(hwirq);
188 static struct gpio_pint *find_gpio_pint(unsigned id)
190 struct gpio_pint *pint;
193 list_for_each_entry(pint, &adi_pint_list, node) {
202 static inline void port_setup(struct gpio_port *port, unsigned offset,
205 struct gpio_port_t *regs = port->regs;
208 writew(readw(®s->port_fer) & ~BIT(offset),
211 writew(readw(®s->port_fer) | BIT(offset), ®s->port_fer);
214 static inline void portmux_setup(struct gpio_port *port, unsigned offset,
215 unsigned short function)
217 struct gpio_port_t *regs = port->regs;
220 pmux = readl(®s->port_mux);
222 /* The function field of each pin has 2 consecutive bits in
225 pmux &= ~(0x3 << (2 * offset));
226 pmux |= (function & 0x3) << (2 * offset);
228 writel(pmux, ®s->port_mux);
231 static inline u16 get_portmux(struct gpio_port *port, unsigned offset)
233 struct gpio_port_t *regs = port->regs;
234 u32 pmux = readl(®s->port_mux);
236 /* The function field of each pin has 2 consecutive bits in
239 return pmux >> (2 * offset) & 0x3;
242 static void adi_gpio_ack_irq(struct irq_data *d)
245 struct gpio_port *port = irq_data_get_irq_chip_data(d);
246 struct gpio_pint_regs *regs = port->pint->regs;
247 unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
249 spin_lock_irqsave(&port->lock, flags);
250 spin_lock_irqsave(&port->pint->lock, flags);
252 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
253 if (readl(®s->invert_set) & pintbit)
254 writel(pintbit, ®s->invert_clear);
256 writel(pintbit, ®s->invert_set);
259 writel(pintbit, ®s->request);
261 spin_unlock_irqrestore(&port->pint->lock, flags);
262 spin_unlock_irqrestore(&port->lock, flags);
265 static void adi_gpio_mask_ack_irq(struct irq_data *d)
268 struct gpio_port *port = irq_data_get_irq_chip_data(d);
269 struct gpio_pint_regs *regs = port->pint->regs;
270 unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
272 spin_lock_irqsave(&port->lock, flags);
273 spin_lock_irqsave(&port->pint->lock, flags);
275 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
276 if (readl(®s->invert_set) & pintbit)
277 writel(pintbit, ®s->invert_clear);
279 writel(pintbit, ®s->invert_set);
282 writel(pintbit, ®s->request);
283 writel(pintbit, ®s->mask_clear);
285 spin_unlock_irqrestore(&port->pint->lock, flags);
286 spin_unlock_irqrestore(&port->lock, flags);
289 static void adi_gpio_mask_irq(struct irq_data *d)
292 struct gpio_port *port = irq_data_get_irq_chip_data(d);
293 struct gpio_pint_regs *regs = port->pint->regs;
295 spin_lock_irqsave(&port->lock, flags);
296 spin_lock_irqsave(&port->pint->lock, flags);
298 writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear);
300 spin_unlock_irqrestore(&port->pint->lock, flags);
301 spin_unlock_irqrestore(&port->lock, flags);
304 static void adi_gpio_unmask_irq(struct irq_data *d)
307 struct gpio_port *port = irq_data_get_irq_chip_data(d);
308 struct gpio_pint_regs *regs = port->pint->regs;
310 spin_lock_irqsave(&port->lock, flags);
311 spin_lock_irqsave(&port->pint->lock, flags);
313 writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set);
315 spin_unlock_irqrestore(&port->pint->lock, flags);
316 spin_unlock_irqrestore(&port->lock, flags);
319 static unsigned int adi_gpio_irq_startup(struct irq_data *d)
322 struct gpio_port *port = irq_data_get_irq_chip_data(d);
323 struct gpio_pint_regs *regs = port->pint->regs;
326 dev_err(port->dev, "GPIO IRQ %d :Not exist\n", d->irq);
330 spin_lock_irqsave(&port->lock, flags);
331 spin_lock_irqsave(&port->pint->lock, flags);
333 port_setup(port, d->hwirq, true);
334 writew(BIT(d->hwirq), &port->regs->dir_clear);
335 writew(readw(&port->regs->inen) | BIT(d->hwirq), &port->regs->inen);
337 writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set);
339 spin_unlock_irqrestore(&port->pint->lock, flags);
340 spin_unlock_irqrestore(&port->lock, flags);
345 static void adi_gpio_irq_shutdown(struct irq_data *d)
348 struct gpio_port *port = irq_data_get_irq_chip_data(d);
349 struct gpio_pint_regs *regs = port->pint->regs;
351 spin_lock_irqsave(&port->lock, flags);
352 spin_lock_irqsave(&port->pint->lock, flags);
354 writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear);
356 spin_unlock_irqrestore(&port->pint->lock, flags);
357 spin_unlock_irqrestore(&port->lock, flags);
360 static int adi_gpio_irq_type(struct irq_data *d, unsigned int type)
363 struct gpio_port *port = irq_data_get_irq_chip_data(d);
364 struct gpio_pint_regs *pint_regs = port->pint->regs;
366 unsigned int irq = d->irq;
371 dev_err(port->dev, "GPIO IRQ %d :Not exist\n", irq);
375 pintmask = hwirq_to_pintbit(port, d->hwirq);
377 spin_lock_irqsave(&port->lock, flags);
378 spin_lock_irqsave(&port->pint->lock, flags);
380 /* In case of interrupt autodetect, set irq type to edge sensitive. */
381 if (type == IRQ_TYPE_PROBE)
382 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
384 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
385 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
386 snprintf(buf, 16, "gpio-irq%d", irq);
387 port_setup(port, d->hwirq, true);
391 /* The GPIO interrupt is triggered only when its input value
392 * transfer from 0 to 1. So, invert the input value if the
393 * irq type is low or falling
395 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
396 writel(pintmask, &pint_regs->invert_set);
398 writel(pintmask, &pint_regs->invert_clear);
400 /* In edge sensitive case, if the input value of the requested irq
401 * is already 1, invert it.
403 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
404 if (gpio_get_value(port->chip.base + d->hwirq))
405 writel(pintmask, &pint_regs->invert_set);
407 writel(pintmask, &pint_regs->invert_clear);
410 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
411 writel(pintmask, &pint_regs->edge_set);
412 __irq_set_handler_locked(irq, handle_edge_irq);
414 writel(pintmask, &pint_regs->edge_clear);
415 __irq_set_handler_locked(irq, handle_level_irq);
419 spin_unlock_irqrestore(&port->pint->lock, flags);
420 spin_unlock_irqrestore(&port->lock, flags);
426 static int adi_gpio_set_wake(struct irq_data *d, unsigned int state)
428 struct gpio_port *port = irq_data_get_irq_chip_data(d);
430 if (!port || !port->pint || port->pint->irq != d->irq)
434 adi_internal_set_wake(port->pint->irq, state);
440 static int adi_pint_suspend(void)
442 struct gpio_pint *pint;
444 list_for_each_entry(pint, &adi_pint_list, node) {
445 writel(0xffffffff, &pint->regs->mask_clear);
446 pint->saved_data.assign = readl(&pint->regs->assign);
447 pint->saved_data.edge_set = readl(&pint->regs->edge_set);
448 pint->saved_data.invert_set = readl(&pint->regs->invert_set);
454 static void adi_pint_resume(void)
456 struct gpio_pint *pint;
458 list_for_each_entry(pint, &adi_pint_list, node) {
459 writel(pint->saved_data.assign, &pint->regs->assign);
460 writel(pint->saved_data.edge_set, &pint->regs->edge_set);
461 writel(pint->saved_data.invert_set, &pint->regs->invert_set);
465 static int adi_gpio_suspend(void)
467 struct gpio_port *port;
469 list_for_each_entry(port, &adi_gpio_port_list, node) {
470 port->saved_data.fer = readw(&port->regs->port_fer);
471 port->saved_data.mux = readl(&port->regs->port_mux);
472 port->saved_data.data = readw(&port->regs->data);
473 port->saved_data.inen = readw(&port->regs->inen);
474 port->saved_data.dir = readw(&port->regs->dir_set);
477 return adi_pint_suspend();
480 static void adi_gpio_resume(void)
482 struct gpio_port *port;
486 list_for_each_entry(port, &adi_gpio_port_list, node) {
487 writel(port->saved_data.mux, &port->regs->port_mux);
488 writew(port->saved_data.fer, &port->regs->port_fer);
489 writew(port->saved_data.inen, &port->regs->inen);
490 writew(port->saved_data.data & port->saved_data.dir,
491 &port->regs->data_set);
492 writew(port->saved_data.dir, &port->regs->dir_set);
497 static struct syscore_ops gpio_pm_syscore_ops = {
498 .suspend = adi_gpio_suspend,
499 .resume = adi_gpio_resume,
501 #else /* CONFIG_PM */
502 #define adi_gpio_set_wake NULL
503 #endif /* CONFIG_PM */
505 #ifdef CONFIG_IRQ_PREFLOW_FASTEOI
506 static inline void preflow_handler(struct irq_desc *desc)
508 if (desc->preflow_handler)
509 desc->preflow_handler(&desc->irq_data);
512 static inline void preflow_handler(struct irq_desc *desc) { }
515 static void adi_gpio_handle_pint_irq(unsigned int inta_irq,
516 struct irq_desc *desc)
519 u32 level_mask, hwirq;
521 struct gpio_pint *pint = irq_desc_get_handler_data(desc);
522 struct irq_chip *chip = irq_desc_get_chip(desc);
523 struct gpio_pint_regs *regs = pint->regs;
524 struct irq_domain *domain;
526 preflow_handler(desc);
527 chained_irq_enter(chip, desc);
529 request = readl(®s->request);
530 level_mask = readl(®s->edge_set) & request;
533 domain = pint->domain[0];
535 /* domain pointer need to be changed only once at IRQ 16 when
536 * we go through IRQ requests from bit 0 to bit 31.
538 if (hwirq == PINT_HI_OFFSET)
539 domain = pint->domain[1];
542 if (level_mask & BIT(hwirq)) {
544 chained_irq_exit(chip, desc);
546 generic_handle_irq(irq_find_mapping(domain,
547 hwirq % PINT_HI_OFFSET));
555 chained_irq_exit(chip, desc);
558 static struct irq_chip adi_gpio_irqchip = {
560 .irq_ack = adi_gpio_ack_irq,
561 .irq_mask = adi_gpio_mask_irq,
562 .irq_mask_ack = adi_gpio_mask_ack_irq,
563 .irq_unmask = adi_gpio_unmask_irq,
564 .irq_disable = adi_gpio_mask_irq,
565 .irq_enable = adi_gpio_unmask_irq,
566 .irq_set_type = adi_gpio_irq_type,
567 .irq_startup = adi_gpio_irq_startup,
568 .irq_shutdown = adi_gpio_irq_shutdown,
569 .irq_set_wake = adi_gpio_set_wake,
572 static int adi_get_groups_count(struct pinctrl_dev *pctldev)
574 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
576 return pinctrl->soc->ngroups;
579 static const char *adi_get_group_name(struct pinctrl_dev *pctldev,
582 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
584 return pinctrl->soc->groups[selector].name;
587 static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
588 const unsigned **pins,
591 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
593 *pins = pinctrl->soc->groups[selector].pins;
594 *num_pins = pinctrl->soc->groups[selector].num;
598 static struct pinctrl_ops adi_pctrl_ops = {
599 .get_groups_count = adi_get_groups_count,
600 .get_group_name = adi_get_group_name,
601 .get_group_pins = adi_get_group_pins,
604 static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
607 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
608 struct gpio_port *port;
609 struct pinctrl_gpio_range *range;
611 unsigned short *mux, pin;
613 mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
618 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
619 if (range == NULL) /* should not happen */
622 port = container_of(range->gc, struct gpio_port, chip);
624 spin_lock_irqsave(&port->lock, flags);
626 portmux_setup(port, pin_to_offset(range, pin),
628 port_setup(port, pin_to_offset(range, pin), false);
631 spin_unlock_irqrestore(&port->lock, flags);
637 static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned selector,
640 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
641 struct gpio_port *port;
642 struct pinctrl_gpio_range *range;
644 unsigned short *mux, pin;
646 mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
651 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
652 if (range == NULL) /* should not happen */
655 port = container_of(range->gc, struct gpio_port, chip);
657 spin_lock_irqsave(&port->lock, flags);
659 port_setup(port, pin_to_offset(range, pin), true);
662 spin_unlock_irqrestore(&port->lock, flags);
666 static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
668 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
670 return pinctrl->soc->nfunctions;
673 static const char *adi_pinmux_get_func_name(struct pinctrl_dev *pctldev,
676 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
678 return pinctrl->soc->functions[selector].name;
681 static int adi_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
682 const char * const **groups,
683 unsigned * const num_groups)
685 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
687 *groups = pinctrl->soc->functions[selector].groups;
688 *num_groups = pinctrl->soc->functions[selector].num_groups;
692 static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
693 struct pinctrl_gpio_range *range, unsigned pin)
695 struct gpio_port *port;
699 port = container_of(range->gc, struct gpio_port, chip);
700 offset = pin_to_offset(range, pin);
702 spin_lock_irqsave(&port->lock, flags);
704 port_setup(port, offset, true);
706 spin_unlock_irqrestore(&port->lock, flags);
711 static struct pinmux_ops adi_pinmux_ops = {
712 .enable = adi_pinmux_enable,
713 .disable = adi_pinmux_disable,
714 .get_functions_count = adi_pinmux_get_funcs_count,
715 .get_function_name = adi_pinmux_get_func_name,
716 .get_function_groups = adi_pinmux_get_groups,
717 .gpio_request_enable = adi_pinmux_request_gpio,
721 static struct pinctrl_desc adi_pinmux_desc = {
723 .pctlops = &adi_pctrl_ops,
724 .pmxops = &adi_pinmux_ops,
725 .owner = THIS_MODULE,
728 static int adi_gpio_request(struct gpio_chip *chip, unsigned offset)
730 return pinctrl_request_gpio(chip->base + offset);
733 static void adi_gpio_free(struct gpio_chip *chip, unsigned offset)
735 pinctrl_free_gpio(chip->base + offset);
738 static int adi_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
740 struct gpio_port *port;
743 port = container_of(chip, struct gpio_port, chip);
745 spin_lock_irqsave(&port->lock, flags);
747 writew(BIT(offset), &port->regs->dir_clear);
748 writew(readw(&port->regs->inen) | BIT(offset), &port->regs->inen);
750 spin_unlock_irqrestore(&port->lock, flags);
755 static void adi_gpio_set_value(struct gpio_chip *chip, unsigned offset,
758 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
759 struct gpio_port_t *regs = port->regs;
762 spin_lock_irqsave(&port->lock, flags);
765 writew(1 << offset, ®s->data_set);
767 writew(1 << offset, ®s->data_clear);
769 spin_unlock_irqrestore(&port->lock, flags);
772 static int adi_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
775 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
776 struct gpio_port_t *regs = port->regs;
779 adi_gpio_set_value(chip, offset, value);
781 spin_lock_irqsave(&port->lock, flags);
783 writew(readw(®s->inen) & ~(1 << offset), ®s->inen);
784 writew(1 << offset, ®s->dir_set);
786 spin_unlock_irqrestore(&port->lock, flags);
791 static int adi_gpio_get_value(struct gpio_chip *chip, unsigned offset)
793 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
794 struct gpio_port_t *regs = port->regs;
798 spin_lock_irqsave(&port->lock, flags);
800 ret = !!(readw(®s->data) & BIT(offset));
802 spin_unlock_irqrestore(&port->lock, flags);
807 static int adi_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
809 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
811 if (port->irq_base >= 0)
812 return irq_find_mapping(port->domain, offset);
814 return irq_create_mapping(port->domain, offset);
817 static int adi_pint_map_port(struct gpio_pint *pint, bool assign, u8 map,
818 struct irq_domain *domain)
820 struct gpio_pint_regs *regs = pint->regs;
823 if (pint->map_count > 1)
828 /* The map_mask of each gpio port is a 16-bit duplicate
829 * of the 8-bit map. It can be set to either high 16 bits or low
830 * 16 bits of the pint assignment register.
832 map_mask = (map << 8) | map;
834 map_mask <<= PINT_HI_OFFSET;
835 writel((readl(®s->assign) & 0xFFFF) | map_mask,
838 writel((readl(®s->assign) & 0xFFFF0000) | map_mask,
841 pint->domain[assign] = domain;
846 static int adi_gpio_pint_probe(struct platform_device *pdev)
848 struct device *dev = &pdev->dev;
849 struct resource *res;
850 struct gpio_pint *pint;
852 pint = devm_kzalloc(dev, sizeof(struct gpio_pint), GFP_KERNEL);
854 dev_err(dev, "Memory alloc failed\n");
858 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
859 pint->base = devm_ioremap_resource(dev, res);
860 if (IS_ERR(pint->base))
861 return PTR_ERR(pint->base);
863 pint->regs = (struct gpio_pint_regs *)pint->base;
865 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
867 dev_err(dev, "Invalid IRQ resource\n");
871 spin_lock_init(&pint->lock);
873 pint->irq = res->start;
874 pint->pint_map_port = adi_pint_map_port;
875 platform_set_drvdata(pdev, pint);
877 irq_set_chained_handler(pint->irq, adi_gpio_handle_pint_irq);
878 irq_set_handler_data(pint->irq, pint);
880 list_add_tail(&pint->node, &adi_pint_list);
885 static int adi_gpio_pint_remove(struct platform_device *pdev)
887 struct gpio_pint *pint = platform_get_drvdata(pdev);
889 list_del(&pint->node);
890 irq_set_handler(pint->irq, handle_simple_irq);
895 static int adi_gpio_irq_map(struct irq_domain *d, unsigned int irq,
896 irq_hw_number_t hwirq)
898 struct gpio_port *port = d->host_data;
903 irq_set_chip_data(irq, port);
904 irq_set_chip_and_handler(irq, &adi_gpio_irqchip,
910 const struct irq_domain_ops adi_gpio_irq_domain_ops = {
911 .map = adi_gpio_irq_map,
912 .xlate = irq_domain_xlate_onecell,
915 static int adi_gpio_init_int(struct gpio_port *port)
917 struct device_node *node = port->dev->of_node;
918 struct gpio_pint *pint = port->pint;
921 port->domain = irq_domain_add_linear(node, port->width,
922 &adi_gpio_irq_domain_ops, port);
924 dev_err(port->dev, "Failed to create irqdomain\n");
928 /* According to BF54x and BF60x HRM, pin interrupt devices are not
929 * part of the GPIO port device. in GPIO interrupt mode, the GPIO
930 * pins of multiple port devices can be routed into one pin interrupt
931 * device. The mapping can be configured by setting pint assignment
932 * register with the mapping value of different GPIO port. This is
933 * done via function pint_map_port().
935 ret = pint->pint_map_port(port->pint, port->pint_assign,
936 port->pint_map, port->domain);
940 if (port->irq_base >= 0) {
941 ret = irq_create_strict_mappings(port->domain, port->irq_base,
944 dev_err(port->dev, "Couldn't associate to domain\n");
952 #define DEVNAME_SIZE 16
954 static int adi_gpio_probe(struct platform_device *pdev)
956 struct device *dev = &pdev->dev;
957 const struct adi_pinctrl_gpio_platform_data *pdata;
958 struct resource *res;
959 struct gpio_port *port;
960 char pinctrl_devname[DEVNAME_SIZE];
964 pdata = dev->platform_data;
968 port = devm_kzalloc(dev, sizeof(struct gpio_port), GFP_KERNEL);
970 dev_err(dev, "Memory alloc failed\n");
974 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
975 port->base = devm_ioremap_resource(dev, res);
976 if (IS_ERR(port->base))
977 return PTR_ERR(port->base);
979 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
983 port->irq_base = res->start;
985 port->width = pdata->port_width;
987 port->regs = (struct gpio_port_t *)port->base;
988 port->pint_assign = pdata->pint_assign;
989 port->pint_map = pdata->pint_map;
991 port->pint = find_gpio_pint(pdata->pint_id);
993 ret = adi_gpio_init_int(port);
998 spin_lock_init(&port->lock);
1000 platform_set_drvdata(pdev, port);
1002 port->chip.label = "adi-gpio";
1003 port->chip.direction_input = adi_gpio_direction_input;
1004 port->chip.get = adi_gpio_get_value;
1005 port->chip.direction_output = adi_gpio_direction_output;
1006 port->chip.set = adi_gpio_set_value;
1007 port->chip.request = adi_gpio_request;
1008 port->chip.free = adi_gpio_free;
1009 port->chip.to_irq = adi_gpio_to_irq;
1010 if (pdata->port_gpio_base > 0)
1011 port->chip.base = pdata->port_gpio_base;
1013 port->chip.base = gpio;
1014 port->chip.ngpio = port->width;
1015 gpio = port->chip.base + port->width;
1017 ret = gpiochip_add(&port->chip);
1019 dev_err(&pdev->dev, "Fail to add GPIO chip.\n");
1020 goto out_remove_domain;
1023 /* Add gpio pin range */
1024 snprintf(pinctrl_devname, DEVNAME_SIZE, "pinctrl-adi2.%d",
1026 pinctrl_devname[DEVNAME_SIZE - 1] = 0;
1027 ret = gpiochip_add_pin_range(&port->chip, pinctrl_devname,
1028 0, pdata->port_pin_base, port->width);
1030 dev_err(&pdev->dev, "Fail to add pin range to %s.\n",
1032 goto out_remove_gpiochip;
1035 list_add_tail(&port->node, &adi_gpio_port_list);
1039 out_remove_gpiochip:
1040 ret1 = gpiochip_remove(&port->chip);
1043 irq_domain_remove(port->domain);
1048 static int adi_gpio_remove(struct platform_device *pdev)
1050 struct gpio_port *port = platform_get_drvdata(pdev);
1054 list_del(&port->node);
1055 gpiochip_remove_pin_ranges(&port->chip);
1056 ret = gpiochip_remove(&port->chip);
1058 for (offset = 0; offset < port->width; offset++)
1059 irq_dispose_mapping(irq_find_mapping(port->domain,
1061 irq_domain_remove(port->domain);
1067 static int adi_pinctrl_probe(struct platform_device *pdev)
1069 struct adi_pinctrl *pinctrl;
1071 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1075 pinctrl->dev = &pdev->dev;
1077 adi_pinctrl_soc_init(&pinctrl->soc);
1079 adi_pinmux_desc.pins = pinctrl->soc->pins;
1080 adi_pinmux_desc.npins = pinctrl->soc->npins;
1082 /* Now register the pin controller and all pins it handles */
1083 pinctrl->pctl = pinctrl_register(&adi_pinmux_desc, &pdev->dev, pinctrl);
1084 if (!pinctrl->pctl) {
1085 dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n");
1089 platform_set_drvdata(pdev, pinctrl);
1094 static int adi_pinctrl_remove(struct platform_device *pdev)
1096 struct adi_pinctrl *pinctrl = platform_get_drvdata(pdev);
1098 pinctrl_unregister(pinctrl->pctl);
1103 static struct platform_driver adi_pinctrl_driver = {
1104 .probe = adi_pinctrl_probe,
1105 .remove = adi_pinctrl_remove,
1107 .name = DRIVER_NAME,
1111 static struct platform_driver adi_gpio_pint_driver = {
1112 .probe = adi_gpio_pint_probe,
1113 .remove = adi_gpio_pint_remove,
1115 .name = "adi-gpio-pint",
1119 static struct platform_driver adi_gpio_driver = {
1120 .probe = adi_gpio_probe,
1121 .remove = adi_gpio_remove,
1127 static int __init adi_pinctrl_setup(void)
1131 ret = platform_driver_register(&adi_pinctrl_driver);
1135 ret = platform_driver_register(&adi_gpio_pint_driver);
1139 ret = platform_driver_register(&adi_gpio_driver);
1144 register_syscore_ops(&gpio_pm_syscore_ops);
1148 platform_driver_unregister(&adi_gpio_pint_driver);
1150 platform_driver_unregister(&adi_pinctrl_driver);
1154 arch_initcall(adi_pinctrl_setup);
1156 MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
1157 MODULE_DESCRIPTION("ADI gpio2 pin control driver");
1158 MODULE_LICENSE("GPL");