2 * at91 pinctrl driver based on at91 pinmux core
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
22 #include <linux/gpio.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 /* Since we request GPIOs from ourself */
28 #include <linux/pinctrl/consumer.h>
30 #include <asm/mach/irq.h>
32 #include <mach/hardware.h>
33 #include <mach/at91_pio.h>
37 #define MAX_NB_GPIO_PER_BANK 32
39 struct at91_pinctrl_mux_ops;
41 struct at91_gpio_chip {
42 struct gpio_chip chip;
43 struct pinctrl_gpio_range range;
44 struct at91_gpio_chip *next; /* Bank sharing same clock */
45 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
46 int pioc_virq; /* PIO bank Linux virtual interrupt */
47 int pioc_idx; /* PIO bank index */
48 void __iomem *regbase; /* PIO bank virtual address */
49 struct clk *clock; /* associated clock */
50 struct irq_domain *domain; /* associated irq domain */
51 struct at91_pinctrl_mux_ops *ops; /* ops */
54 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
56 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
58 static int gpio_banks;
60 #define PULL_UP (1 << 0)
61 #define MULTI_DRIVE (1 << 1)
62 #define DEGLITCH (1 << 2)
63 #define PULL_DOWN (1 << 3)
64 #define DIS_SCHMIT (1 << 4)
65 #define DEBOUNCE (1 << 16)
66 #define DEBOUNCE_VAL_SHIFT 17
67 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
70 * struct at91_pmx_func - describes AT91 pinmux functions
71 * @name: the name of this specific function
72 * @groups: corresponding pin groups
73 * @ngroups: the number of groups
75 struct at91_pmx_func {
83 AT91_MUX_PERIPH_A = 1,
84 AT91_MUX_PERIPH_B = 2,
85 AT91_MUX_PERIPH_C = 3,
86 AT91_MUX_PERIPH_D = 4,
90 * struct at91_pmx_pin - describes an At91 pin mux
91 * @bank: the bank of the pin
92 * @pin: the pin number in the @bank
93 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
94 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
104 * struct at91_pin_group - describes an At91 pin group
105 * @name: the name of this specific pin group
106 * @pins_conf: the mux mode for each pin in this group. The size of this
107 * array is the same as pins.
108 * @pins: an array of discrete physical pins used in this group, taken
109 * from the driver-local pin enumeration space
110 * @npins: the number of pins in this group array, i.e. the number of
111 * elements in .pins so we can iterate over that array
113 struct at91_pin_group {
115 struct at91_pmx_pin *pins_conf;
121 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
122 * on new IP with support for periph C and D the way to mux in
123 * periph A and B has changed
124 * So provide the right call back
125 * if not present means the IP does not support it
126 * @get_periph: return the periph mode configured
127 * @mux_A_periph: mux as periph A
128 * @mux_B_periph: mux as periph B
129 * @mux_C_periph: mux as periph C
130 * @mux_D_periph: mux as periph D
131 * @get_deglitch: get deglitch status
132 * @set_deglitch: enable/disable deglitch
133 * @get_debounce: get debounce status
134 * @set_debounce: enable/disable debounce
135 * @get_pulldown: get pulldown status
136 * @set_pulldown: enable/disable pulldown
137 * @get_schmitt_trig: get schmitt trigger status
138 * @disable_schmitt_trig: disable schmitt trigger
139 * @irq_type: return irq type
141 struct at91_pinctrl_mux_ops {
142 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
143 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
144 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
145 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
146 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
147 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
148 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on);
149 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
150 void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div);
151 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
152 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on);
153 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
154 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
156 int (*irq_type)(struct irq_data *d, unsigned type);
159 static int gpio_irq_type(struct irq_data *d, unsigned type);
160 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
162 struct at91_pinctrl {
164 struct pinctrl_dev *pctl;
171 struct at91_pmx_func *functions;
174 struct at91_pin_group *groups;
177 struct at91_pinctrl_mux_ops *ops;
180 static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
181 const struct at91_pinctrl *info,
184 const struct at91_pin_group *grp = NULL;
187 for (i = 0; i < info->ngroups; i++) {
188 if (strcmp(info->groups[i].name, name))
191 grp = &info->groups[i];
192 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
199 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
201 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
203 return info->ngroups;
206 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
209 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
211 return info->groups[selector].name;
214 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
215 const unsigned **pins,
218 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
220 if (selector >= info->ngroups)
223 *pins = info->groups[selector].pins;
224 *npins = info->groups[selector].npins;
229 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
232 seq_printf(s, "%s", dev_name(pctldev->dev));
235 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
236 struct device_node *np,
237 struct pinctrl_map **map, unsigned *num_maps)
239 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
240 const struct at91_pin_group *grp;
241 struct pinctrl_map *new_map;
242 struct device_node *parent;
247 * first find the group of this node and check if we need create
248 * config maps for pins
250 grp = at91_pinctrl_find_group_by_name(info, np->name);
252 dev_err(info->dev, "unable to find group for node %s\n",
257 map_num += grp->npins;
258 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
266 parent = of_get_parent(np);
268 devm_kfree(pctldev->dev, new_map);
271 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
272 new_map[0].data.mux.function = parent->name;
273 new_map[0].data.mux.group = np->name;
276 /* create config map */
278 for (i = 0; i < grp->npins; i++) {
279 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
280 new_map[i].data.configs.group_or_pin =
281 pin_get_name(pctldev, grp->pins[i]);
282 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
283 new_map[i].data.configs.num_configs = 1;
286 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
287 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
292 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
293 struct pinctrl_map *map, unsigned num_maps)
297 static struct pinctrl_ops at91_pctrl_ops = {
298 .get_groups_count = at91_get_groups_count,
299 .get_group_name = at91_get_group_name,
300 .get_group_pins = at91_get_group_pins,
301 .pin_dbg_show = at91_pin_dbg_show,
302 .dt_node_to_map = at91_dt_node_to_map,
303 .dt_free_map = at91_dt_free_map,
306 static void __iomem * pin_to_controller(struct at91_pinctrl *info,
309 return gpio_chips[bank]->regbase;
312 static inline int pin_to_bank(unsigned pin)
314 return pin /= MAX_NB_GPIO_PER_BANK;
317 static unsigned pin_to_mask(unsigned int pin)
322 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
324 writel_relaxed(mask, pio + PIO_IDR);
327 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
329 return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1;
332 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
334 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
337 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
339 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
342 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
344 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
347 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
349 writel_relaxed(mask, pio + PIO_ASR);
352 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
354 writel_relaxed(mask, pio + PIO_BSR);
357 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
360 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
362 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
366 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
368 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
370 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
374 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
376 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
377 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
380 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
382 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
383 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
386 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
390 if (readl_relaxed(pio + PIO_PSR) & mask)
391 return AT91_MUX_GPIO;
393 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
394 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
399 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
403 if (readl_relaxed(pio + PIO_PSR) & mask)
404 return AT91_MUX_GPIO;
406 select = readl_relaxed(pio + PIO_ABSR) & mask;
411 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
413 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
416 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
418 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
421 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
424 __raw_writel(mask, pio + PIO_IFSCDR);
425 at91_mux_set_deglitch(pio, mask, is_on);
428 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
430 *div = __raw_readl(pio + PIO_SCDR);
432 return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1;
435 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
439 __raw_writel(mask, pio + PIO_IFSCER);
440 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
441 __raw_writel(mask, pio + PIO_IFER);
443 __raw_writel(mask, pio + PIO_IFDR);
447 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
449 return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1;
452 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
454 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
457 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
459 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
462 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
464 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
467 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
468 .get_periph = at91_mux_get_periph,
469 .mux_A_periph = at91_mux_set_A_periph,
470 .mux_B_periph = at91_mux_set_B_periph,
471 .get_deglitch = at91_mux_get_deglitch,
472 .set_deglitch = at91_mux_set_deglitch,
473 .irq_type = gpio_irq_type,
476 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
477 .get_periph = at91_mux_pio3_get_periph,
478 .mux_A_periph = at91_mux_pio3_set_A_periph,
479 .mux_B_periph = at91_mux_pio3_set_B_periph,
480 .mux_C_periph = at91_mux_pio3_set_C_periph,
481 .mux_D_periph = at91_mux_pio3_set_D_periph,
482 .get_deglitch = at91_mux_get_deglitch,
483 .set_deglitch = at91_mux_pio3_set_deglitch,
484 .get_debounce = at91_mux_pio3_get_debounce,
485 .set_debounce = at91_mux_pio3_set_debounce,
486 .get_pulldown = at91_mux_pio3_get_pulldown,
487 .set_pulldown = at91_mux_pio3_set_pulldown,
488 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
489 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
490 .irq_type = alt_gpio_irq_type,
493 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
496 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
497 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
499 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
500 pin->bank + 'A', pin->pin, pin->conf);
504 static int pin_check_config(struct at91_pinctrl *info, const char* name,
505 int index, const struct at91_pmx_pin *pin)
509 /* check if it's a valid config */
510 if (pin->bank >= info->nbanks) {
511 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
512 name, index, pin->bank, info->nbanks);
516 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
517 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
518 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
527 if (mux >= info->nmux) {
528 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
529 name, index, mux, info->nmux);
533 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
534 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
535 name, index, mux, pin->bank + 'A', pin->pin);
542 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
544 writel_relaxed(mask, pio + PIO_PDR);
547 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
549 writel_relaxed(mask, pio + PIO_PER);
550 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
553 static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
556 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
557 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
558 const struct at91_pmx_pin *pin;
559 uint32_t npins = info->groups[group].npins;
564 dev_dbg(info->dev, "enable function %s group %s\n",
565 info->functions[selector].name, info->groups[group].name);
567 /* first check that all the pins of the group are valid with a valid
569 for (i = 0; i < npins; i++) {
571 ret = pin_check_config(info, info->groups[group].name, i, pin);
576 for (i = 0; i < npins; i++) {
578 at91_pin_dbg(info->dev, pin);
579 pio = pin_to_controller(info, pin->bank);
580 mask = pin_to_mask(pin->pin);
581 at91_mux_disable_interrupt(pio, mask);
584 at91_mux_gpio_enable(pio, mask, 1);
586 case AT91_MUX_PERIPH_A:
587 info->ops->mux_A_periph(pio, mask);
589 case AT91_MUX_PERIPH_B:
590 info->ops->mux_B_periph(pio, mask);
592 case AT91_MUX_PERIPH_C:
593 if (!info->ops->mux_C_periph)
595 info->ops->mux_C_periph(pio, mask);
597 case AT91_MUX_PERIPH_D:
598 if (!info->ops->mux_D_periph)
600 info->ops->mux_D_periph(pio, mask);
604 at91_mux_gpio_disable(pio, mask);
610 static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
613 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
614 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
615 const struct at91_pmx_pin *pin;
616 uint32_t npins = info->groups[group].npins;
621 for (i = 0; i < npins; i++) {
623 at91_pin_dbg(info->dev, pin);
624 pio = pin_to_controller(info, pin->bank);
625 mask = pin_to_mask(pin->pin);
626 at91_mux_gpio_enable(pio, mask, 1);
630 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
632 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
634 return info->nfunctions;
637 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
640 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
642 return info->functions[selector].name;
645 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
646 const char * const **groups,
647 unsigned * const num_groups)
649 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
651 *groups = info->functions[selector].groups;
652 *num_groups = info->functions[selector].ngroups;
657 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
658 struct pinctrl_gpio_range *range,
661 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
662 struct at91_gpio_chip *at91_chip;
663 struct gpio_chip *chip;
667 dev_err(npct->dev, "invalid range\n");
671 dev_err(npct->dev, "missing GPIO chip in range\n");
675 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
677 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
679 mask = 1 << (offset - chip->base);
681 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
682 offset, 'A' + range->id, offset - chip->base, mask);
684 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
689 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
690 struct pinctrl_gpio_range *range,
693 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
695 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
696 /* Set the pin to some default state, GPIO is usually default */
699 static struct pinmux_ops at91_pmx_ops = {
700 .get_functions_count = at91_pmx_get_funcs_count,
701 .get_function_name = at91_pmx_get_func_name,
702 .get_function_groups = at91_pmx_get_groups,
703 .enable = at91_pmx_enable,
704 .disable = at91_pmx_disable,
705 .gpio_request_enable = at91_gpio_request_enable,
706 .gpio_disable_free = at91_gpio_disable_free,
709 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
710 unsigned pin_id, unsigned long *config)
712 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
717 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config);
718 pio = pin_to_controller(info, pin_to_bank(pin_id));
719 pin = pin_id % MAX_NB_GPIO_PER_BANK;
721 if (at91_mux_get_multidrive(pio, pin))
722 *config |= MULTI_DRIVE;
724 if (at91_mux_get_pullup(pio, pin))
727 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
729 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
730 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
731 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
732 *config |= PULL_DOWN;
733 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
734 *config |= DIS_SCHMIT;
739 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
740 unsigned pin_id, unsigned long config)
742 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
746 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config);
747 pio = pin_to_controller(info, pin_to_bank(pin_id));
748 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
750 if (config & PULL_UP && config & PULL_DOWN)
753 at91_mux_set_pullup(pio, mask, config & PULL_UP);
754 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
755 if (info->ops->set_deglitch)
756 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
757 if (info->ops->set_debounce)
758 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
759 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
760 if (info->ops->set_pulldown)
761 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
762 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
763 info->ops->disable_schmitt_trig(pio, mask);
768 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
769 struct seq_file *s, unsigned pin_id)
774 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
775 struct seq_file *s, unsigned group)
779 static struct pinconf_ops at91_pinconf_ops = {
780 .pin_config_get = at91_pinconf_get,
781 .pin_config_set = at91_pinconf_set,
782 .pin_config_dbg_show = at91_pinconf_dbg_show,
783 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
786 static struct pinctrl_desc at91_pinctrl_desc = {
787 .pctlops = &at91_pctrl_ops,
788 .pmxops = &at91_pmx_ops,
789 .confops = &at91_pinconf_ops,
790 .owner = THIS_MODULE,
793 static const char *gpio_compat = "atmel,at91rm9200-gpio";
795 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
796 struct device_node *np)
798 struct device_node *child;
800 for_each_child_of_node(np, child) {
801 if (of_device_is_compatible(child, gpio_compat)) {
805 info->ngroups += of_get_child_count(child);
810 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
811 struct device_node *np)
815 const const __be32 *list;
817 list = of_get_property(np, "atmel,mux-mask", &size);
819 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
823 size /= sizeof(*list);
824 if (!size || size % info->nbanks) {
825 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
828 info->nmux = size / info->nbanks;
830 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
831 if (!info->mux_mask) {
832 dev_err(info->dev, "could not alloc mux_mask\n");
836 ret = of_property_read_u32_array(np, "atmel,mux-mask",
837 info->mux_mask, size);
839 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
843 static int at91_pinctrl_parse_groups(struct device_node *np,
844 struct at91_pin_group *grp,
845 struct at91_pinctrl *info, u32 index)
847 struct at91_pmx_pin *pin;
849 const const __be32 *list;
852 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
854 /* Initialise group */
855 grp->name = np->name;
858 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
859 * do sanity check and calculate pins number
861 list = of_get_property(np, "atmel,pins", &size);
862 /* we do not check return since it's safe node passed down */
863 size /= sizeof(*list);
864 if (!size || size % 4) {
865 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
869 grp->npins = size / 4;
870 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
872 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
874 if (!grp->pins_conf || !grp->pins)
877 for (i = 0, j = 0; i < size; i += 4, j++) {
878 pin->bank = be32_to_cpu(*list++);
879 pin->pin = be32_to_cpu(*list++);
880 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
881 pin->mux = be32_to_cpu(*list++);
882 pin->conf = be32_to_cpu(*list++);
884 at91_pin_dbg(info->dev, pin);
891 static int at91_pinctrl_parse_functions(struct device_node *np,
892 struct at91_pinctrl *info, u32 index)
894 struct device_node *child;
895 struct at91_pmx_func *func;
896 struct at91_pin_group *grp;
898 static u32 grp_index;
901 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
903 func = &info->functions[index];
905 /* Initialise function */
906 func->name = np->name;
907 func->ngroups = of_get_child_count(np);
908 if (func->ngroups <= 0) {
909 dev_err(info->dev, "no groups defined\n");
912 func->groups = devm_kzalloc(info->dev,
913 func->ngroups * sizeof(char *), GFP_KERNEL);
917 for_each_child_of_node(np, child) {
918 func->groups[i] = child->name;
919 grp = &info->groups[grp_index++];
920 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
928 static struct of_device_id at91_pinctrl_of_match[] = {
929 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
930 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
934 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
935 struct at91_pinctrl *info)
940 struct device_node *np = pdev->dev.of_node;
941 struct device_node *child;
946 info->dev = &pdev->dev;
947 info->ops = (struct at91_pinctrl_mux_ops*)
948 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
949 at91_pinctrl_child_count(info, np);
951 if (info->nbanks < 1) {
952 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
956 ret = at91_pinctrl_mux_mask(info, np);
960 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
962 dev_dbg(&pdev->dev, "mux-mask\n");
963 tmp = info->mux_mask;
964 for (i = 0; i < info->nbanks; i++) {
965 for (j = 0; j < info->nmux; j++, tmp++) {
966 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
970 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
971 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
972 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
974 if (!info->functions)
977 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
982 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
983 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
984 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
988 for_each_child_of_node(np, child) {
989 if (of_device_is_compatible(child, gpio_compat))
991 ret = at91_pinctrl_parse_functions(child, info, i++);
993 dev_err(&pdev->dev, "failed to parse function\n");
1001 static int at91_pinctrl_probe(struct platform_device *pdev)
1003 struct at91_pinctrl *info;
1004 struct pinctrl_pin_desc *pdesc;
1007 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1011 ret = at91_pinctrl_probe_dt(pdev, info);
1016 * We need all the GPIO drivers to probe FIRST, or we will not be able
1017 * to obtain references to the struct gpio_chip * for them, and we
1018 * need this to proceed.
1020 for (i = 0; i < info->nbanks; i++) {
1021 if (!gpio_chips[i]) {
1022 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1023 devm_kfree(&pdev->dev, info);
1024 return -EPROBE_DEFER;
1028 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1029 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
1030 at91_pinctrl_desc.pins = pdesc =
1031 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1033 if (!at91_pinctrl_desc.pins)
1036 for (i = 0 , k = 0; i < info->nbanks; i++) {
1037 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1039 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1044 platform_set_drvdata(pdev, info);
1045 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1048 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1053 /* We will handle a range of GPIO pins */
1054 for (i = 0; i < info->nbanks; i++)
1055 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1057 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1065 static int at91_pinctrl_remove(struct platform_device *pdev)
1067 struct at91_pinctrl *info = platform_get_drvdata(pdev);
1069 pinctrl_unregister(info->pctl);
1074 static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
1077 * Map back to global GPIO space and request muxing, the direction
1078 * parameter does not matter for this controller.
1080 int gpio = chip->base + offset;
1081 int bank = chip->base / chip->ngpio;
1083 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
1084 'A' + bank, offset, gpio);
1086 return pinctrl_request_gpio(gpio);
1089 static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1091 int gpio = chip->base + offset;
1093 pinctrl_free_gpio(gpio);
1096 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1098 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1099 void __iomem *pio = at91_gpio->regbase;
1100 unsigned mask = 1 << offset;
1102 writel_relaxed(mask, pio + PIO_ODR);
1106 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1108 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1109 void __iomem *pio = at91_gpio->regbase;
1110 unsigned mask = 1 << offset;
1113 pdsr = readl_relaxed(pio + PIO_PDSR);
1114 return (pdsr & mask) != 0;
1117 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1120 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1121 void __iomem *pio = at91_gpio->regbase;
1122 unsigned mask = 1 << offset;
1124 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1127 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1130 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1131 void __iomem *pio = at91_gpio->regbase;
1132 unsigned mask = 1 << offset;
1134 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1135 writel_relaxed(mask, pio + PIO_OER);
1140 static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1142 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1145 if (offset < chip->ngpio)
1146 virq = irq_create_mapping(at91_gpio->domain, offset);
1150 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1151 chip->label, offset + chip->base, virq);
1155 #ifdef CONFIG_DEBUG_FS
1156 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1160 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1161 void __iomem *pio = at91_gpio->regbase;
1163 for (i = 0; i < chip->ngpio; i++) {
1164 unsigned pin = chip->base + i;
1165 unsigned mask = pin_to_mask(pin);
1166 const char *gpio_label;
1169 gpio_label = gpiochip_is_requested(chip, i);
1172 mode = at91_gpio->ops->get_periph(pio, mask);
1173 seq_printf(s, "[%s] GPIO%s%d: ",
1174 gpio_label, chip->label, i);
1175 if (mode == AT91_MUX_GPIO) {
1176 pdsr = readl_relaxed(pio + PIO_PDSR);
1178 seq_printf(s, "[gpio] %s\n",
1182 seq_printf(s, "[periph %c]\n",
1188 #define at91_gpio_dbg_show NULL
1191 /* Several AIC controller irqs are dispatched through this GPIO handler.
1192 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1193 * at91_set_gpio_input() then maybe enable its glitch filter.
1194 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1196 * First implementation always triggers on rising and falling edges
1197 * whereas the newer PIO3 can be additionally configured to trigger on
1198 * level, edge with any polarity.
1200 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1201 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1202 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1205 static void gpio_irq_mask(struct irq_data *d)
1207 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1208 void __iomem *pio = at91_gpio->regbase;
1209 unsigned mask = 1 << d->hwirq;
1212 writel_relaxed(mask, pio + PIO_IDR);
1215 static void gpio_irq_unmask(struct irq_data *d)
1217 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1218 void __iomem *pio = at91_gpio->regbase;
1219 unsigned mask = 1 << d->hwirq;
1222 writel_relaxed(mask, pio + PIO_IER);
1225 static int gpio_irq_type(struct irq_data *d, unsigned type)
1229 case IRQ_TYPE_EDGE_BOTH:
1236 /* Alternate irq type for PIO3 support */
1237 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1239 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1240 void __iomem *pio = at91_gpio->regbase;
1241 unsigned mask = 1 << d->hwirq;
1244 case IRQ_TYPE_EDGE_RISING:
1245 writel_relaxed(mask, pio + PIO_ESR);
1246 writel_relaxed(mask, pio + PIO_REHLSR);
1248 case IRQ_TYPE_EDGE_FALLING:
1249 writel_relaxed(mask, pio + PIO_ESR);
1250 writel_relaxed(mask, pio + PIO_FELLSR);
1252 case IRQ_TYPE_LEVEL_LOW:
1253 writel_relaxed(mask, pio + PIO_LSR);
1254 writel_relaxed(mask, pio + PIO_FELLSR);
1256 case IRQ_TYPE_LEVEL_HIGH:
1257 writel_relaxed(mask, pio + PIO_LSR);
1258 writel_relaxed(mask, pio + PIO_REHLSR);
1260 case IRQ_TYPE_EDGE_BOTH:
1262 * disable additional interrupt modes:
1263 * fall back to default behavior
1265 writel_relaxed(mask, pio + PIO_AIMDR);
1269 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1273 /* enable additional interrupt modes */
1274 writel_relaxed(mask, pio + PIO_AIMER);
1280 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1282 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1283 unsigned bank = at91_gpio->pioc_idx;
1285 if (unlikely(bank >= MAX_GPIO_BANKS))
1288 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1293 #define gpio_irq_set_wake NULL
1296 static struct irq_chip gpio_irqchip = {
1298 .irq_disable = gpio_irq_mask,
1299 .irq_mask = gpio_irq_mask,
1300 .irq_unmask = gpio_irq_unmask,
1301 /* .irq_set_type is set dynamically */
1302 .irq_set_wake = gpio_irq_set_wake,
1305 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1307 struct irq_chip *chip = irq_desc_get_chip(desc);
1308 struct irq_data *idata = irq_desc_get_irq_data(desc);
1309 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
1310 void __iomem *pio = at91_gpio->regbase;
1314 chained_irq_enter(chip, desc);
1316 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1317 * When there none are pending, we're finished unless we need
1318 * to process multiple banks (like ID_PIOCDE on sam9263).
1320 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1322 if (!at91_gpio->next)
1324 at91_gpio = at91_gpio->next;
1325 pio = at91_gpio->regbase;
1329 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1330 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
1333 chained_irq_exit(chip, desc);
1334 /* now it may re-trigger */
1338 * This lock class tells lockdep that GPIO irqs are in a different
1339 * category than their parents, so it won't report false recursion.
1341 static struct lock_class_key gpio_lock_class;
1343 static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1346 struct at91_gpio_chip *at91_gpio = h->host_data;
1348 irq_set_lockdep_class(virq, &gpio_lock_class);
1351 * Can use the "simple" and not "edge" handler since it's
1352 * shorter, and the AIC handles interrupts sanely.
1354 irq_set_chip_and_handler(virq, &gpio_irqchip,
1356 set_irq_flags(virq, IRQF_VALID);
1357 irq_set_chip_data(virq, at91_gpio);
1362 static int at91_gpio_irq_domain_xlate(struct irq_domain *d,
1363 struct device_node *ctrlr,
1364 const u32 *intspec, unsigned int intsize,
1365 irq_hw_number_t *out_hwirq,
1366 unsigned int *out_type)
1368 struct at91_gpio_chip *at91_gpio = d->host_data;
1370 int pin = at91_gpio->chip.base + intspec[0];
1372 if (WARN_ON(intsize < 2))
1374 *out_hwirq = intspec[0];
1375 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1377 ret = gpio_request(pin, ctrlr->full_name);
1381 ret = gpio_direction_input(pin);
1388 static struct irq_domain_ops at91_gpio_ops = {
1389 .map = at91_gpio_irq_map,
1390 .xlate = at91_gpio_irq_domain_xlate,
1393 static int at91_gpio_of_irq_setup(struct device_node *node,
1394 struct at91_gpio_chip *at91_gpio)
1396 struct at91_gpio_chip *prev = NULL;
1397 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1399 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1401 /* Setup proper .irq_set_type function */
1402 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1404 /* Disable irqs of this PIO controller */
1405 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1407 /* Setup irq domain */
1408 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
1409 &at91_gpio_ops, at91_gpio);
1410 if (!at91_gpio->domain)
1411 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1412 at91_gpio->pioc_idx);
1414 /* Setup chained handler */
1415 if (at91_gpio->pioc_idx)
1416 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1418 /* The toplevel handler handles one bank of GPIOs, except
1419 * on some SoC it can handles up to three...
1420 * We only set up the handler for the first of the list.
1422 if (prev && prev->next == at91_gpio)
1425 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
1426 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
1431 /* This structure is replicated for each GPIO block allocated at probe time */
1432 static struct gpio_chip at91_gpio_template = {
1433 .request = at91_gpio_request,
1434 .free = at91_gpio_free,
1435 .direction_input = at91_gpio_direction_input,
1436 .get = at91_gpio_get,
1437 .direction_output = at91_gpio_direction_output,
1438 .set = at91_gpio_set,
1439 .to_irq = at91_gpio_to_irq,
1440 .dbg_show = at91_gpio_dbg_show,
1442 .ngpio = MAX_NB_GPIO_PER_BANK,
1445 static void at91_gpio_probe_fixup(void)
1448 struct at91_gpio_chip *at91_gpio, *last = NULL;
1450 for (i = 0; i < gpio_banks; i++) {
1451 at91_gpio = gpio_chips[i];
1454 * GPIO controller are grouped on some SoC:
1455 * PIOC, PIOD and PIOE can share the same IRQ line
1457 if (last && last->pioc_virq == at91_gpio->pioc_virq)
1458 last->next = at91_gpio;
1463 static struct of_device_id at91_gpio_of_match[] = {
1464 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1465 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1469 static int at91_gpio_probe(struct platform_device *pdev)
1471 struct device_node *np = pdev->dev.of_node;
1472 struct resource *res;
1473 struct at91_gpio_chip *at91_chip = NULL;
1474 struct gpio_chip *chip;
1475 struct pinctrl_gpio_range *range;
1478 int alias_idx = of_alias_get_id(np, "gpio");
1482 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1483 if (gpio_chips[alias_idx]) {
1488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1494 irq = platform_get_irq(pdev, 0);
1500 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1506 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1507 if (IS_ERR(at91_chip->regbase)) {
1508 ret = PTR_ERR(at91_chip->regbase);
1512 at91_chip->ops = (struct at91_pinctrl_mux_ops*)
1513 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1514 at91_chip->pioc_virq = irq;
1515 at91_chip->pioc_idx = alias_idx;
1517 at91_chip->clock = clk_get(&pdev->dev, NULL);
1518 if (IS_ERR(at91_chip->clock)) {
1519 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1523 if (clk_prepare(at91_chip->clock))
1526 /* enable PIO controller's clock */
1527 if (clk_enable(at91_chip->clock)) {
1528 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1532 at91_chip->chip = at91_gpio_template;
1534 chip = &at91_chip->chip;
1536 chip->label = dev_name(&pdev->dev);
1537 chip->dev = &pdev->dev;
1538 chip->owner = THIS_MODULE;
1539 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1541 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1542 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1543 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1544 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1546 chip->ngpio = ngpio;
1549 names = devm_kzalloc(&pdev->dev, sizeof(char*) * chip->ngpio, GFP_KERNEL);
1556 for (i = 0; i < chip->ngpio; i++)
1557 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1559 chip->names = (const char*const*)names;
1561 range = &at91_chip->range;
1562 range->name = chip->label;
1563 range->id = alias_idx;
1564 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1566 range->npins = chip->ngpio;
1569 ret = gpiochip_add(chip);
1573 gpio_chips[alias_idx] = at91_chip;
1574 gpio_banks = max(gpio_banks, alias_idx + 1);
1576 at91_gpio_probe_fixup();
1578 at91_gpio_of_irq_setup(np, at91_chip);
1580 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1585 clk_unprepare(at91_chip->clock);
1587 clk_put(at91_chip->clock);
1589 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1594 static struct platform_driver at91_gpio_driver = {
1596 .name = "gpio-at91",
1597 .owner = THIS_MODULE,
1598 .of_match_table = of_match_ptr(at91_gpio_of_match),
1600 .probe = at91_gpio_probe,
1603 static struct platform_driver at91_pinctrl_driver = {
1605 .name = "pinctrl-at91",
1606 .owner = THIS_MODULE,
1607 .of_match_table = of_match_ptr(at91_pinctrl_of_match),
1609 .probe = at91_pinctrl_probe,
1610 .remove = at91_pinctrl_remove,
1613 static int __init at91_pinctrl_init(void)
1617 ret = platform_driver_register(&at91_gpio_driver);
1620 return platform_driver_register(&at91_pinctrl_driver);
1622 arch_initcall(at91_pinctrl_init);
1624 static void __exit at91_pinctrl_exit(void)
1626 platform_driver_unregister(&at91_pinctrl_driver);
1629 module_exit(at91_pinctrl_exit);
1630 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1631 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1632 MODULE_LICENSE("GPL v2");