2 * at91 pinctrl driver based on at91 pinmux core
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
20 #include <linux/gpio.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 /* Since we request GPIOs from ourself */
26 #include <linux/pinctrl/consumer.h>
28 #include <mach/hardware.h>
29 #include <mach/at91_pio.h>
33 #define MAX_GPIO_BANKS 5
34 #define MAX_NB_GPIO_PER_BANK 32
36 struct at91_pinctrl_mux_ops;
38 struct at91_gpio_chip {
39 struct gpio_chip chip;
40 struct pinctrl_gpio_range range;
41 struct at91_gpio_chip *next; /* Bank sharing same clock */
42 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
43 int pioc_virq; /* PIO bank Linux virtual interrupt */
44 int pioc_idx; /* PIO bank index */
45 void __iomem *regbase; /* PIO bank virtual address */
46 struct clk *clock; /* associated clock */
47 struct at91_pinctrl_mux_ops *ops; /* ops */
50 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
52 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
54 static int gpio_banks;
56 #define PULL_UP (1 << 0)
57 #define MULTI_DRIVE (1 << 1)
58 #define DEGLITCH (1 << 2)
59 #define PULL_DOWN (1 << 3)
60 #define DIS_SCHMIT (1 << 4)
61 #define DEBOUNCE (1 << 16)
62 #define DEBOUNCE_VAL_SHIFT 17
63 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
66 * struct at91_pmx_func - describes AT91 pinmux functions
67 * @name: the name of this specific function
68 * @groups: corresponding pin groups
69 * @ngroups: the number of groups
71 struct at91_pmx_func {
79 AT91_MUX_PERIPH_A = 1,
80 AT91_MUX_PERIPH_B = 2,
81 AT91_MUX_PERIPH_C = 3,
82 AT91_MUX_PERIPH_D = 4,
86 * struct at91_pmx_pin - describes an At91 pin mux
87 * @bank: the bank of the pin
88 * @pin: the pin number in the @bank
89 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
90 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
100 * struct at91_pin_group - describes an At91 pin group
101 * @name: the name of this specific pin group
102 * @pins_conf: the mux mode for each pin in this group. The size of this
103 * array is the same as pins.
104 * @pins: an array of discrete physical pins used in this group, taken
105 * from the driver-local pin enumeration space
106 * @npins: the number of pins in this group array, i.e. the number of
107 * elements in .pins so we can iterate over that array
109 struct at91_pin_group {
111 struct at91_pmx_pin *pins_conf;
117 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
118 * on new IP with support for periph C and D the way to mux in
119 * periph A and B has changed
120 * So provide the right call back
121 * if not present means the IP does not support it
122 * @get_periph: return the periph mode configured
123 * @mux_A_periph: mux as periph A
124 * @mux_B_periph: mux as periph B
125 * @mux_C_periph: mux as periph C
126 * @mux_D_periph: mux as periph D
127 * @get_deglitch: get deglitch status
128 * @set_deglitch: enable/disable deglitch
129 * @get_debounce: get debounce status
130 * @set_debounce: enable/disable debounce
131 * @get_pulldown: get pulldown status
132 * @set_pulldown: enable/disable pulldown
133 * @get_schmitt_trig: get schmitt trigger status
134 * @disable_schmitt_trig: disable schmitt trigger
135 * @irq_type: return irq type
137 struct at91_pinctrl_mux_ops {
138 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
139 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
140 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
141 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
142 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
143 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
144 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
145 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
146 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
147 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
148 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
149 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
150 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
152 int (*irq_type)(struct irq_data *d, unsigned type);
155 static int gpio_irq_type(struct irq_data *d, unsigned type);
156 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
158 struct at91_pinctrl {
160 struct pinctrl_dev *pctl;
167 struct at91_pmx_func *functions;
170 struct at91_pin_group *groups;
173 struct at91_pinctrl_mux_ops *ops;
176 static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
177 const struct at91_pinctrl *info,
180 const struct at91_pin_group *grp = NULL;
183 for (i = 0; i < info->ngroups; i++) {
184 if (strcmp(info->groups[i].name, name))
187 grp = &info->groups[i];
188 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
195 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
197 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
199 return info->ngroups;
202 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
205 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
207 return info->groups[selector].name;
210 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
211 const unsigned **pins,
214 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
216 if (selector >= info->ngroups)
219 *pins = info->groups[selector].pins;
220 *npins = info->groups[selector].npins;
225 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
228 seq_printf(s, "%s", dev_name(pctldev->dev));
231 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
232 struct device_node *np,
233 struct pinctrl_map **map, unsigned *num_maps)
235 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
236 const struct at91_pin_group *grp;
237 struct pinctrl_map *new_map;
238 struct device_node *parent;
243 * first find the group of this node and check if we need to create
244 * config maps for pins
246 grp = at91_pinctrl_find_group_by_name(info, np->name);
248 dev_err(info->dev, "unable to find group for node %s\n",
253 map_num += grp->npins;
254 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
262 parent = of_get_parent(np);
264 devm_kfree(pctldev->dev, new_map);
267 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
268 new_map[0].data.mux.function = parent->name;
269 new_map[0].data.mux.group = np->name;
272 /* create config map */
274 for (i = 0; i < grp->npins; i++) {
275 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
276 new_map[i].data.configs.group_or_pin =
277 pin_get_name(pctldev, grp->pins[i]);
278 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
279 new_map[i].data.configs.num_configs = 1;
282 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
283 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
288 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
289 struct pinctrl_map *map, unsigned num_maps)
293 static const struct pinctrl_ops at91_pctrl_ops = {
294 .get_groups_count = at91_get_groups_count,
295 .get_group_name = at91_get_group_name,
296 .get_group_pins = at91_get_group_pins,
297 .pin_dbg_show = at91_pin_dbg_show,
298 .dt_node_to_map = at91_dt_node_to_map,
299 .dt_free_map = at91_dt_free_map,
302 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
305 return gpio_chips[bank]->regbase;
308 static inline int pin_to_bank(unsigned pin)
310 return pin /= MAX_NB_GPIO_PER_BANK;
313 static unsigned pin_to_mask(unsigned int pin)
318 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
320 writel_relaxed(mask, pio + PIO_IDR);
323 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
325 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
328 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
330 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
333 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
335 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
338 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
340 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
343 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
345 writel_relaxed(mask, pio + PIO_ASR);
348 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
350 writel_relaxed(mask, pio + PIO_BSR);
353 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
356 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
358 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
362 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
364 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
366 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
370 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
372 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
373 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
376 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
378 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
379 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
382 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
386 if (readl_relaxed(pio + PIO_PSR) & mask)
387 return AT91_MUX_GPIO;
389 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
390 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
395 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
399 if (readl_relaxed(pio + PIO_PSR) & mask)
400 return AT91_MUX_GPIO;
402 select = readl_relaxed(pio + PIO_ABSR) & mask;
407 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
409 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
412 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
414 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
417 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
419 if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1)
420 return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
425 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
428 __raw_writel(mask, pio + PIO_IFSCDR);
429 at91_mux_set_deglitch(pio, mask, is_on);
432 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
434 *div = __raw_readl(pio + PIO_SCDR);
436 return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) &&
437 ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
440 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
444 __raw_writel(mask, pio + PIO_IFSCER);
445 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
446 __raw_writel(mask, pio + PIO_IFER);
448 __raw_writel(mask, pio + PIO_IFSCDR);
451 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
453 return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1);
456 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
458 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
461 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
463 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
466 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
468 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
471 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
472 .get_periph = at91_mux_get_periph,
473 .mux_A_periph = at91_mux_set_A_periph,
474 .mux_B_periph = at91_mux_set_B_periph,
475 .get_deglitch = at91_mux_get_deglitch,
476 .set_deglitch = at91_mux_set_deglitch,
477 .irq_type = gpio_irq_type,
480 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
481 .get_periph = at91_mux_pio3_get_periph,
482 .mux_A_periph = at91_mux_pio3_set_A_periph,
483 .mux_B_periph = at91_mux_pio3_set_B_periph,
484 .mux_C_periph = at91_mux_pio3_set_C_periph,
485 .mux_D_periph = at91_mux_pio3_set_D_periph,
486 .get_deglitch = at91_mux_pio3_get_deglitch,
487 .set_deglitch = at91_mux_pio3_set_deglitch,
488 .get_debounce = at91_mux_pio3_get_debounce,
489 .set_debounce = at91_mux_pio3_set_debounce,
490 .get_pulldown = at91_mux_pio3_get_pulldown,
491 .set_pulldown = at91_mux_pio3_set_pulldown,
492 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
493 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
494 .irq_type = alt_gpio_irq_type,
497 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
500 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
501 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
503 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
504 pin->bank + 'A', pin->pin, pin->conf);
508 static int pin_check_config(struct at91_pinctrl *info, const char *name,
509 int index, const struct at91_pmx_pin *pin)
513 /* check if it's a valid config */
514 if (pin->bank >= info->nbanks) {
515 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
516 name, index, pin->bank, info->nbanks);
520 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
521 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
522 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
531 if (mux >= info->nmux) {
532 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
533 name, index, mux, info->nmux);
537 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
538 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
539 name, index, mux, pin->bank + 'A', pin->pin);
546 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
548 writel_relaxed(mask, pio + PIO_PDR);
551 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
553 writel_relaxed(mask, pio + PIO_PER);
554 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
557 static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
560 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
561 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
562 const struct at91_pmx_pin *pin;
563 uint32_t npins = info->groups[group].npins;
568 dev_dbg(info->dev, "enable function %s group %s\n",
569 info->functions[selector].name, info->groups[group].name);
571 /* first check that all the pins of the group are valid with a valid
573 for (i = 0; i < npins; i++) {
575 ret = pin_check_config(info, info->groups[group].name, i, pin);
580 for (i = 0; i < npins; i++) {
582 at91_pin_dbg(info->dev, pin);
583 pio = pin_to_controller(info, pin->bank);
584 mask = pin_to_mask(pin->pin);
585 at91_mux_disable_interrupt(pio, mask);
588 at91_mux_gpio_enable(pio, mask, 1);
590 case AT91_MUX_PERIPH_A:
591 info->ops->mux_A_periph(pio, mask);
593 case AT91_MUX_PERIPH_B:
594 info->ops->mux_B_periph(pio, mask);
596 case AT91_MUX_PERIPH_C:
597 if (!info->ops->mux_C_periph)
599 info->ops->mux_C_periph(pio, mask);
601 case AT91_MUX_PERIPH_D:
602 if (!info->ops->mux_D_periph)
604 info->ops->mux_D_periph(pio, mask);
608 at91_mux_gpio_disable(pio, mask);
614 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
616 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
618 return info->nfunctions;
621 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
624 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
626 return info->functions[selector].name;
629 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
630 const char * const **groups,
631 unsigned * const num_groups)
633 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
635 *groups = info->functions[selector].groups;
636 *num_groups = info->functions[selector].ngroups;
641 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
642 struct pinctrl_gpio_range *range,
645 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
646 struct at91_gpio_chip *at91_chip;
647 struct gpio_chip *chip;
651 dev_err(npct->dev, "invalid range\n");
655 dev_err(npct->dev, "missing GPIO chip in range\n");
659 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
661 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
663 mask = 1 << (offset - chip->base);
665 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
666 offset, 'A' + range->id, offset - chip->base, mask);
668 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
673 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
674 struct pinctrl_gpio_range *range,
677 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
679 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
680 /* Set the pin to some default state, GPIO is usually default */
683 static const struct pinmux_ops at91_pmx_ops = {
684 .get_functions_count = at91_pmx_get_funcs_count,
685 .get_function_name = at91_pmx_get_func_name,
686 .get_function_groups = at91_pmx_get_groups,
687 .enable = at91_pmx_enable,
688 .gpio_request_enable = at91_gpio_request_enable,
689 .gpio_disable_free = at91_gpio_disable_free,
692 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
693 unsigned pin_id, unsigned long *config)
695 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
701 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
702 pio = pin_to_controller(info, pin_to_bank(pin_id));
703 pin = pin_id % MAX_NB_GPIO_PER_BANK;
705 if (at91_mux_get_multidrive(pio, pin))
706 *config |= MULTI_DRIVE;
708 if (at91_mux_get_pullup(pio, pin))
711 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
713 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
714 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
715 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
716 *config |= PULL_DOWN;
717 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
718 *config |= DIS_SCHMIT;
723 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
724 unsigned pin_id, unsigned long *configs,
725 unsigned num_configs)
727 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
731 unsigned long config;
733 for (i = 0; i < num_configs; i++) {
737 "%s:%d, pin_id=%d, config=0x%lx",
738 __func__, __LINE__, pin_id, config);
739 pio = pin_to_controller(info, pin_to_bank(pin_id));
740 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
742 if (config & PULL_UP && config & PULL_DOWN)
745 at91_mux_set_pullup(pio, mask, config & PULL_UP);
746 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
747 if (info->ops->set_deglitch)
748 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
749 if (info->ops->set_debounce)
750 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
751 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
752 if (info->ops->set_pulldown)
753 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
754 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
755 info->ops->disable_schmitt_trig(pio, mask);
757 } /* for each config */
762 #define DBG_SHOW_FLAG(flag) do { \
763 if (config & flag) { \
766 seq_puts(s, #flag); \
771 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
772 struct seq_file *s, unsigned pin_id)
774 unsigned long config;
775 int val, num_conf = 0;
777 at91_pinconf_get(pctldev, pin_id, &config);
779 DBG_SHOW_FLAG(MULTI_DRIVE);
780 DBG_SHOW_FLAG(PULL_UP);
781 DBG_SHOW_FLAG(PULL_DOWN);
782 DBG_SHOW_FLAG(DIS_SCHMIT);
783 DBG_SHOW_FLAG(DEGLITCH);
784 DBG_SHOW_FLAG(DEBOUNCE);
785 if (config & DEBOUNCE) {
786 val = config >> DEBOUNCE_VAL_SHIFT;
787 seq_printf(s, "(%d)", val);
793 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
794 struct seq_file *s, unsigned group)
798 static const struct pinconf_ops at91_pinconf_ops = {
799 .pin_config_get = at91_pinconf_get,
800 .pin_config_set = at91_pinconf_set,
801 .pin_config_dbg_show = at91_pinconf_dbg_show,
802 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
805 static struct pinctrl_desc at91_pinctrl_desc = {
806 .pctlops = &at91_pctrl_ops,
807 .pmxops = &at91_pmx_ops,
808 .confops = &at91_pinconf_ops,
809 .owner = THIS_MODULE,
812 static const char *gpio_compat = "atmel,at91rm9200-gpio";
814 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
815 struct device_node *np)
817 struct device_node *child;
819 for_each_child_of_node(np, child) {
820 if (of_device_is_compatible(child, gpio_compat)) {
824 info->ngroups += of_get_child_count(child);
829 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
830 struct device_node *np)
836 list = of_get_property(np, "atmel,mux-mask", &size);
838 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
842 size /= sizeof(*list);
843 if (!size || size % info->nbanks) {
844 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
847 info->nmux = size / info->nbanks;
849 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
850 if (!info->mux_mask) {
851 dev_err(info->dev, "could not alloc mux_mask\n");
855 ret = of_property_read_u32_array(np, "atmel,mux-mask",
856 info->mux_mask, size);
858 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
862 static int at91_pinctrl_parse_groups(struct device_node *np,
863 struct at91_pin_group *grp,
864 struct at91_pinctrl *info, u32 index)
866 struct at91_pmx_pin *pin;
871 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
873 /* Initialise group */
874 grp->name = np->name;
877 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
878 * do sanity check and calculate pins number
880 list = of_get_property(np, "atmel,pins", &size);
881 /* we do not check return since it's safe node passed down */
882 size /= sizeof(*list);
883 if (!size || size % 4) {
884 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
888 grp->npins = size / 4;
889 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
891 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
893 if (!grp->pins_conf || !grp->pins)
896 for (i = 0, j = 0; i < size; i += 4, j++) {
897 pin->bank = be32_to_cpu(*list++);
898 pin->pin = be32_to_cpu(*list++);
899 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
900 pin->mux = be32_to_cpu(*list++);
901 pin->conf = be32_to_cpu(*list++);
903 at91_pin_dbg(info->dev, pin);
910 static int at91_pinctrl_parse_functions(struct device_node *np,
911 struct at91_pinctrl *info, u32 index)
913 struct device_node *child;
914 struct at91_pmx_func *func;
915 struct at91_pin_group *grp;
917 static u32 grp_index;
920 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
922 func = &info->functions[index];
924 /* Initialise function */
925 func->name = np->name;
926 func->ngroups = of_get_child_count(np);
927 if (func->ngroups == 0) {
928 dev_err(info->dev, "no groups defined\n");
931 func->groups = devm_kzalloc(info->dev,
932 func->ngroups * sizeof(char *), GFP_KERNEL);
936 for_each_child_of_node(np, child) {
937 func->groups[i] = child->name;
938 grp = &info->groups[grp_index++];
939 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
947 static struct of_device_id at91_pinctrl_of_match[] = {
948 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
949 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
953 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
954 struct at91_pinctrl *info)
959 struct device_node *np = pdev->dev.of_node;
960 struct device_node *child;
965 info->dev = &pdev->dev;
966 info->ops = (struct at91_pinctrl_mux_ops *)
967 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
968 at91_pinctrl_child_count(info, np);
970 if (info->nbanks < 1) {
971 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
975 ret = at91_pinctrl_mux_mask(info, np);
979 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
981 dev_dbg(&pdev->dev, "mux-mask\n");
982 tmp = info->mux_mask;
983 for (i = 0; i < info->nbanks; i++) {
984 for (j = 0; j < info->nmux; j++, tmp++) {
985 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
989 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
990 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
991 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
993 if (!info->functions)
996 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
1001 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
1002 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1003 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1007 for_each_child_of_node(np, child) {
1008 if (of_device_is_compatible(child, gpio_compat))
1010 ret = at91_pinctrl_parse_functions(child, info, i++);
1012 dev_err(&pdev->dev, "failed to parse function\n");
1020 static int at91_pinctrl_probe(struct platform_device *pdev)
1022 struct at91_pinctrl *info;
1023 struct pinctrl_pin_desc *pdesc;
1026 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1030 ret = at91_pinctrl_probe_dt(pdev, info);
1035 * We need all the GPIO drivers to probe FIRST, or we will not be able
1036 * to obtain references to the struct gpio_chip * for them, and we
1037 * need this to proceed.
1039 for (i = 0; i < info->nbanks; i++) {
1040 if (!gpio_chips[i]) {
1041 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1042 devm_kfree(&pdev->dev, info);
1043 return -EPROBE_DEFER;
1047 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1048 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
1049 at91_pinctrl_desc.pins = pdesc =
1050 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1052 if (!at91_pinctrl_desc.pins)
1055 for (i = 0 , k = 0; i < info->nbanks; i++) {
1056 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1058 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1063 platform_set_drvdata(pdev, info);
1064 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1067 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1072 /* We will handle a range of GPIO pins */
1073 for (i = 0; i < info->nbanks; i++)
1074 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1076 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1084 static int at91_pinctrl_remove(struct platform_device *pdev)
1086 struct at91_pinctrl *info = platform_get_drvdata(pdev);
1088 pinctrl_unregister(info->pctl);
1093 static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
1096 * Map back to global GPIO space and request muxing, the direction
1097 * parameter does not matter for this controller.
1099 int gpio = chip->base + offset;
1100 int bank = chip->base / chip->ngpio;
1102 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
1103 'A' + bank, offset, gpio);
1105 return pinctrl_request_gpio(gpio);
1108 static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1110 int gpio = chip->base + offset;
1112 pinctrl_free_gpio(gpio);
1115 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1117 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1118 void __iomem *pio = at91_gpio->regbase;
1119 unsigned mask = 1 << offset;
1122 osr = readl_relaxed(pio + PIO_OSR);
1123 return !(osr & mask);
1126 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1128 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1129 void __iomem *pio = at91_gpio->regbase;
1130 unsigned mask = 1 << offset;
1132 writel_relaxed(mask, pio + PIO_ODR);
1136 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1138 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1139 void __iomem *pio = at91_gpio->regbase;
1140 unsigned mask = 1 << offset;
1143 pdsr = readl_relaxed(pio + PIO_PDSR);
1144 return (pdsr & mask) != 0;
1147 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1150 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1151 void __iomem *pio = at91_gpio->regbase;
1152 unsigned mask = 1 << offset;
1154 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1157 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1160 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1161 void __iomem *pio = at91_gpio->regbase;
1162 unsigned mask = 1 << offset;
1164 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1165 writel_relaxed(mask, pio + PIO_OER);
1170 #ifdef CONFIG_DEBUG_FS
1171 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1175 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1176 void __iomem *pio = at91_gpio->regbase;
1178 for (i = 0; i < chip->ngpio; i++) {
1179 unsigned mask = pin_to_mask(i);
1180 const char *gpio_label;
1183 gpio_label = gpiochip_is_requested(chip, i);
1186 mode = at91_gpio->ops->get_periph(pio, mask);
1187 seq_printf(s, "[%s] GPIO%s%d: ",
1188 gpio_label, chip->label, i);
1189 if (mode == AT91_MUX_GPIO) {
1190 pdsr = readl_relaxed(pio + PIO_PDSR);
1192 seq_printf(s, "[gpio] %s\n",
1196 seq_printf(s, "[periph %c]\n",
1202 #define at91_gpio_dbg_show NULL
1205 /* Several AIC controller irqs are dispatched through this GPIO handler.
1206 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1207 * at91_set_gpio_input() then maybe enable its glitch filter.
1208 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1210 * First implementation always triggers on rising and falling edges
1211 * whereas the newer PIO3 can be additionally configured to trigger on
1212 * level, edge with any polarity.
1214 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1215 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1216 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1219 static void gpio_irq_mask(struct irq_data *d)
1221 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1222 void __iomem *pio = at91_gpio->regbase;
1223 unsigned mask = 1 << d->hwirq;
1226 writel_relaxed(mask, pio + PIO_IDR);
1229 static void gpio_irq_unmask(struct irq_data *d)
1231 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1232 void __iomem *pio = at91_gpio->regbase;
1233 unsigned mask = 1 << d->hwirq;
1236 writel_relaxed(mask, pio + PIO_IER);
1239 static int gpio_irq_type(struct irq_data *d, unsigned type)
1243 case IRQ_TYPE_EDGE_BOTH:
1250 /* Alternate irq type for PIO3 support */
1251 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1253 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1254 void __iomem *pio = at91_gpio->regbase;
1255 unsigned mask = 1 << d->hwirq;
1258 case IRQ_TYPE_EDGE_RISING:
1259 __irq_set_handler_locked(d->irq, handle_simple_irq);
1260 writel_relaxed(mask, pio + PIO_ESR);
1261 writel_relaxed(mask, pio + PIO_REHLSR);
1263 case IRQ_TYPE_EDGE_FALLING:
1264 __irq_set_handler_locked(d->irq, handle_simple_irq);
1265 writel_relaxed(mask, pio + PIO_ESR);
1266 writel_relaxed(mask, pio + PIO_FELLSR);
1268 case IRQ_TYPE_LEVEL_LOW:
1269 __irq_set_handler_locked(d->irq, handle_level_irq);
1270 writel_relaxed(mask, pio + PIO_LSR);
1271 writel_relaxed(mask, pio + PIO_FELLSR);
1273 case IRQ_TYPE_LEVEL_HIGH:
1274 __irq_set_handler_locked(d->irq, handle_level_irq);
1275 writel_relaxed(mask, pio + PIO_LSR);
1276 writel_relaxed(mask, pio + PIO_REHLSR);
1278 case IRQ_TYPE_EDGE_BOTH:
1280 * disable additional interrupt modes:
1281 * fall back to default behavior
1283 __irq_set_handler_locked(d->irq, handle_simple_irq);
1284 writel_relaxed(mask, pio + PIO_AIMDR);
1288 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1292 /* enable additional interrupt modes */
1293 writel_relaxed(mask, pio + PIO_AIMER);
1298 static void gpio_irq_ack(struct irq_data *d)
1300 /* the interrupt is already cleared before by reading ISR */
1303 static unsigned int gpio_irq_startup(struct irq_data *d)
1305 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1306 unsigned pin = d->hwirq;
1309 ret = gpio_lock_as_irq(&at91_gpio->chip, pin);
1311 dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n",
1319 static void gpio_irq_shutdown(struct irq_data *d)
1321 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1322 unsigned pin = d->hwirq;
1325 gpio_unlock_as_irq(&at91_gpio->chip, pin);
1330 static u32 wakeups[MAX_GPIO_BANKS];
1331 static u32 backups[MAX_GPIO_BANKS];
1333 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1335 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1336 unsigned bank = at91_gpio->pioc_idx;
1337 unsigned mask = 1 << d->hwirq;
1339 if (unlikely(bank >= MAX_GPIO_BANKS))
1343 wakeups[bank] |= mask;
1345 wakeups[bank] &= ~mask;
1347 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1352 void at91_pinctrl_gpio_suspend(void)
1356 for (i = 0; i < gpio_banks; i++) {
1362 pio = gpio_chips[i]->regbase;
1364 backups[i] = __raw_readl(pio + PIO_IMR);
1365 __raw_writel(backups[i], pio + PIO_IDR);
1366 __raw_writel(wakeups[i], pio + PIO_IER);
1369 clk_disable_unprepare(gpio_chips[i]->clock);
1371 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1376 void at91_pinctrl_gpio_resume(void)
1380 for (i = 0; i < gpio_banks; i++) {
1386 pio = gpio_chips[i]->regbase;
1389 clk_prepare_enable(gpio_chips[i]->clock);
1391 __raw_writel(wakeups[i], pio + PIO_IDR);
1392 __raw_writel(backups[i], pio + PIO_IER);
1397 #define gpio_irq_set_wake NULL
1398 #endif /* CONFIG_PM */
1400 static struct irq_chip gpio_irqchip = {
1402 .irq_ack = gpio_irq_ack,
1403 .irq_startup = gpio_irq_startup,
1404 .irq_shutdown = gpio_irq_shutdown,
1405 .irq_disable = gpio_irq_mask,
1406 .irq_mask = gpio_irq_mask,
1407 .irq_unmask = gpio_irq_unmask,
1408 /* .irq_set_type is set dynamically */
1409 .irq_set_wake = gpio_irq_set_wake,
1412 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1414 struct irq_chip *chip = irq_get_chip(irq);
1415 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1416 struct at91_gpio_chip *at91_gpio = container_of(gpio_chip,
1417 struct at91_gpio_chip, chip);
1419 void __iomem *pio = at91_gpio->regbase;
1423 chained_irq_enter(chip, desc);
1425 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1426 * When there are none pending, we're finished unless we need
1427 * to process multiple banks (like ID_PIOCDE on sam9263).
1429 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1431 if (!at91_gpio->next)
1433 at91_gpio = at91_gpio->next;
1434 pio = at91_gpio->regbase;
1435 gpio_chip = &at91_gpio->chip;
1439 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1440 generic_handle_irq(irq_find_mapping(
1441 gpio_chip->irqdomain, n));
1444 chained_irq_exit(chip, desc);
1445 /* now it may re-trigger */
1448 static int at91_gpio_of_irq_setup(struct device_node *node,
1449 struct at91_gpio_chip *at91_gpio)
1451 struct at91_gpio_chip *prev = NULL;
1452 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1455 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1457 /* Setup proper .irq_set_type function */
1458 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1460 /* Disable irqs of this PIO controller */
1461 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1464 * Let the generic code handle this edge IRQ, the the chained
1465 * handler will perform the actual work of handling the parent
1468 ret = gpiochip_irqchip_add(&at91_gpio->chip,
1472 IRQ_TYPE_EDGE_BOTH);
1474 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1475 at91_gpio->pioc_idx);
1477 /* Setup chained handler */
1478 if (at91_gpio->pioc_idx)
1479 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1481 /* The top level handler handles one bank of GPIOs, except
1482 * on some SoC it can handle up to three...
1483 * We only set up the handler for the first of the list.
1485 if (prev && prev->next == at91_gpio)
1488 /* Then register the chain on the parent IRQ */
1489 gpiochip_set_chained_irqchip(&at91_gpio->chip,
1491 at91_gpio->pioc_virq,
1497 /* This structure is replicated for each GPIO block allocated at probe time */
1498 static struct gpio_chip at91_gpio_template = {
1499 .request = at91_gpio_request,
1500 .free = at91_gpio_free,
1501 .get_direction = at91_gpio_get_direction,
1502 .direction_input = at91_gpio_direction_input,
1503 .get = at91_gpio_get,
1504 .direction_output = at91_gpio_direction_output,
1505 .set = at91_gpio_set,
1506 .dbg_show = at91_gpio_dbg_show,
1508 .ngpio = MAX_NB_GPIO_PER_BANK,
1511 static void at91_gpio_probe_fixup(void)
1514 struct at91_gpio_chip *at91_gpio, *last = NULL;
1516 for (i = 0; i < gpio_banks; i++) {
1517 at91_gpio = gpio_chips[i];
1520 * GPIO controller are grouped on some SoC:
1521 * PIOC, PIOD and PIOE can share the same IRQ line
1523 if (last && last->pioc_virq == at91_gpio->pioc_virq)
1524 last->next = at91_gpio;
1529 static struct of_device_id at91_gpio_of_match[] = {
1530 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1531 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1535 static int at91_gpio_probe(struct platform_device *pdev)
1537 struct device_node *np = pdev->dev.of_node;
1538 struct resource *res;
1539 struct at91_gpio_chip *at91_chip = NULL;
1540 struct gpio_chip *chip;
1541 struct pinctrl_gpio_range *range;
1544 int alias_idx = of_alias_get_id(np, "gpio");
1548 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1549 if (gpio_chips[alias_idx]) {
1554 irq = platform_get_irq(pdev, 0);
1560 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1566 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1567 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1568 if (IS_ERR(at91_chip->regbase)) {
1569 ret = PTR_ERR(at91_chip->regbase);
1573 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1574 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1575 at91_chip->pioc_virq = irq;
1576 at91_chip->pioc_idx = alias_idx;
1578 at91_chip->clock = clk_get(&pdev->dev, NULL);
1579 if (IS_ERR(at91_chip->clock)) {
1580 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1584 if (clk_prepare(at91_chip->clock))
1587 /* enable PIO controller's clock */
1588 if (clk_enable(at91_chip->clock)) {
1589 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1593 at91_chip->chip = at91_gpio_template;
1595 chip = &at91_chip->chip;
1597 chip->label = dev_name(&pdev->dev);
1598 chip->dev = &pdev->dev;
1599 chip->owner = THIS_MODULE;
1600 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1602 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1603 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1604 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1605 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1607 chip->ngpio = ngpio;
1610 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1618 for (i = 0; i < chip->ngpio; i++)
1619 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1621 chip->names = (const char *const *)names;
1623 range = &at91_chip->range;
1624 range->name = chip->label;
1625 range->id = alias_idx;
1626 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1628 range->npins = chip->ngpio;
1631 ret = gpiochip_add(chip);
1635 gpio_chips[alias_idx] = at91_chip;
1636 gpio_banks = max(gpio_banks, alias_idx + 1);
1638 at91_gpio_probe_fixup();
1640 at91_gpio_of_irq_setup(np, at91_chip);
1642 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1647 clk_unprepare(at91_chip->clock);
1649 clk_put(at91_chip->clock);
1651 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1656 static struct platform_driver at91_gpio_driver = {
1658 .name = "gpio-at91",
1659 .owner = THIS_MODULE,
1660 .of_match_table = at91_gpio_of_match,
1662 .probe = at91_gpio_probe,
1665 static struct platform_driver at91_pinctrl_driver = {
1667 .name = "pinctrl-at91",
1668 .owner = THIS_MODULE,
1669 .of_match_table = at91_pinctrl_of_match,
1671 .probe = at91_pinctrl_probe,
1672 .remove = at91_pinctrl_remove,
1675 static int __init at91_pinctrl_init(void)
1679 ret = platform_driver_register(&at91_gpio_driver);
1682 return platform_driver_register(&at91_pinctrl_driver);
1684 arch_initcall(at91_pinctrl_init);
1686 static void __exit at91_pinctrl_exit(void)
1688 platform_driver_unregister(&at91_pinctrl_driver);
1691 module_exit(at91_pinctrl_exit);
1692 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1693 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1694 MODULE_LICENSE("GPL v2");