2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/bitops.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/gpio.h>
30 #include <linux/irqdomain.h>
31 #include <linux/acpi.h>
32 #include <linux/platform_device.h>
33 #include <linux/seq_file.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/pinctrl/pinctrl.h>
38 /* memory mapped register offsets */
39 #define BYT_CONF0_REG 0x000
40 #define BYT_CONF1_REG 0x004
41 #define BYT_VAL_REG 0x008
42 #define BYT_DFT_REG 0x00c
43 #define BYT_INT_STAT_REG 0x800
45 /* BYT_CONF0_REG register bits */
46 #define BYT_IODEN BIT(31)
47 #define BYT_TRIG_NEG BIT(26)
48 #define BYT_TRIG_POS BIT(25)
49 #define BYT_TRIG_LVL BIT(24)
50 #define BYT_PULL_STR_SHIFT 9
51 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
52 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
53 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
54 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
55 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
56 #define BYT_PULL_ASSIGN_SHIFT 7
57 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
58 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
59 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
60 #define BYT_PIN_MUX 0x07
62 /* BYT_VAL_REG register bits */
63 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
64 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
65 #define BYT_LEVEL BIT(0)
67 #define BYT_DIR_MASK (BIT(1) | BIT(2))
68 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
70 #define BYT_NGPIO_SCORE 102
71 #define BYT_NGPIO_NCORE 28
72 #define BYT_NGPIO_SUS 44
74 #define BYT_SCORE_ACPI_UID "1"
75 #define BYT_NCORE_ACPI_UID "2"
76 #define BYT_SUS_ACPI_UID "3"
79 * Baytrail gpio controller consist of three separate sub-controllers called
80 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
82 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
83 * _not_ correspond to the first gpio register at controller's gpio base.
84 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
85 * each sub-controller needs to have its own mapping table
88 /* score_pins[gpio_nr] = pad_nr */
90 static unsigned const score_pins[BYT_NGPIO_SCORE] = {
91 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
92 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
93 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
94 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
95 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
96 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
97 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
98 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
99 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
100 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
104 static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
105 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
106 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
107 3, 6, 10, 13, 2, 5, 9, 7,
110 static unsigned const sus_pins[BYT_NGPIO_SUS] = {
111 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
112 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
113 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
114 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
118 static struct pinctrl_gpio_range byt_ranges[] = {
120 .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
121 .npins = BYT_NGPIO_SCORE,
125 .name = BYT_NCORE_ACPI_UID,
126 .npins = BYT_NGPIO_NCORE,
130 .name = BYT_SUS_ACPI_UID,
131 .npins = BYT_NGPIO_SUS,
139 struct gpio_chip chip;
140 struct irq_domain *domain;
141 struct platform_device *pdev;
143 void __iomem *reg_base;
144 struct pinctrl_gpio_range *range;
147 #define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
149 static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
152 struct byt_gpio *vg = to_byt_gpio(chip);
155 if (reg == BYT_INT_STAT_REG)
156 reg_offset = (offset / 32) * 4;
158 reg_offset = vg->range->pins[offset] * 16;
160 return vg->reg_base + reg_offset + reg;
163 static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
165 /* SCORE pin 92-93 */
166 if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
167 offset >= 92 && offset <= 93)
171 if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
172 offset >= 11 && offset <= 21)
178 static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
180 struct byt_gpio *vg = to_byt_gpio(chip);
181 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
186 * In most cases, func pin mux 000 means GPIO function.
187 * But, some pins may have func pin mux 001 represents
188 * GPIO function. Only allow user to export pin with
189 * func pin mux preset as GPIO function by BIOS/FW.
191 value = readl(reg) & BYT_PIN_MUX;
192 special = is_special_pin(vg, offset);
193 if ((special && value != 1) || (!special && value)) {
194 dev_err(&vg->pdev->dev,
195 "pin %u cannot be used as GPIO.\n", offset);
199 pm_runtime_get(&vg->pdev->dev);
204 static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
206 struct byt_gpio *vg = to_byt_gpio(chip);
207 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
210 /* clear interrupt triggering */
212 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
215 pm_runtime_put(&vg->pdev->dev);
218 static int byt_irq_type(struct irq_data *d, unsigned type)
220 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
221 u32 offset = irqd_to_hwirq(d);
224 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
226 if (offset >= vg->chip.ngpio)
229 spin_lock_irqsave(&vg->lock, flags);
232 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
233 * are used to indicate high and low level triggering
235 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
238 case IRQ_TYPE_LEVEL_HIGH:
239 value |= BYT_TRIG_LVL;
240 case IRQ_TYPE_EDGE_RISING:
241 value |= BYT_TRIG_POS;
243 case IRQ_TYPE_LEVEL_LOW:
244 value |= BYT_TRIG_LVL;
245 case IRQ_TYPE_EDGE_FALLING:
246 value |= BYT_TRIG_NEG;
248 case IRQ_TYPE_EDGE_BOTH:
249 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
254 spin_unlock_irqrestore(&vg->lock, flags);
259 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
261 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
262 return readl(reg) & BYT_LEVEL;
265 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
267 struct byt_gpio *vg = to_byt_gpio(chip);
268 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
272 spin_lock_irqsave(&vg->lock, flags);
274 old_val = readl(reg);
277 writel(old_val | BYT_LEVEL, reg);
279 writel(old_val & ~BYT_LEVEL, reg);
281 spin_unlock_irqrestore(&vg->lock, flags);
284 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
286 struct byt_gpio *vg = to_byt_gpio(chip);
287 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
291 spin_lock_irqsave(&vg->lock, flags);
293 value = readl(reg) | BYT_DIR_MASK;
294 value &= ~BYT_INPUT_EN; /* active low */
297 spin_unlock_irqrestore(&vg->lock, flags);
302 static int byt_gpio_direction_output(struct gpio_chip *chip,
303 unsigned gpio, int value)
305 struct byt_gpio *vg = to_byt_gpio(chip);
306 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
310 spin_lock_irqsave(&vg->lock, flags);
312 reg_val = readl(reg) | BYT_DIR_MASK;
313 reg_val &= ~BYT_OUTPUT_EN;
316 writel(reg_val | BYT_LEVEL, reg);
318 writel(reg_val & ~BYT_LEVEL, reg);
320 spin_unlock_irqrestore(&vg->lock, flags);
325 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
327 struct byt_gpio *vg = to_byt_gpio(chip);
330 u32 conf0, val, offs;
332 spin_lock_irqsave(&vg->lock, flags);
334 for (i = 0; i < vg->chip.ngpio; i++) {
335 const char *pull_str = NULL;
336 const char *pull = NULL;
338 offs = vg->range->pins[i] * 16;
339 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
340 val = readl(vg->reg_base + offs + BYT_VAL_REG);
342 label = gpiochip_is_requested(chip, i);
344 label = "Unrequested";
346 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
347 case BYT_PULL_ASSIGN_UP:
350 case BYT_PULL_ASSIGN_DOWN:
355 switch (conf0 & BYT_PULL_STR_MASK) {
356 case BYT_PULL_STR_2K:
359 case BYT_PULL_STR_10K:
362 case BYT_PULL_STR_20K:
365 case BYT_PULL_STR_40K:
371 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
374 val & BYT_INPUT_EN ? " " : "in",
375 val & BYT_OUTPUT_EN ? " " : "out",
376 val & BYT_LEVEL ? "hi" : "lo",
377 vg->range->pins[i], offs,
379 conf0 & BYT_TRIG_NEG ? " fall" : " ",
380 conf0 & BYT_TRIG_POS ? " rise" : " ",
381 conf0 & BYT_TRIG_LVL ? " level" : " ");
383 if (pull && pull_str)
384 seq_printf(s, " %-4s %-3s", pull, pull_str);
388 if (conf0 & BYT_IODEN)
389 seq_puts(s, " open-drain");
393 spin_unlock_irqrestore(&vg->lock, flags);
396 static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
398 struct byt_gpio *vg = to_byt_gpio(chip);
399 return irq_create_mapping(vg->domain, offset);
402 static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
404 struct irq_data *data = irq_desc_get_irq_data(desc);
405 struct byt_gpio *vg = irq_data_get_irq_handler_data(data);
406 struct irq_chip *chip = irq_data_get_irq_chip(data);
413 /* check from GPIO controller which pin triggered the interrupt */
414 for (base = 0; base < vg->chip.ngpio; base += 32) {
416 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
418 while ((pending = readl(reg))) {
419 pin = __ffs(pending);
421 /* Clear before handling so we can't lose an edge */
424 virq = irq_find_mapping(vg->domain, base + pin);
425 generic_handle_irq(virq);
427 /* In case bios or user sets triggering incorretly a pin
428 * might remain in "interrupt triggered" state.
430 if (looplimit++ > 32) {
431 dev_err(&vg->pdev->dev,
432 "Gpio %d interrupt flood, disabling\n",
435 reg = byt_gpio_reg(&vg->chip, base + pin,
438 mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS |
441 mask = readl(reg); /* flush */
449 static void byt_irq_unmask(struct irq_data *d)
453 static void byt_irq_mask(struct irq_data *d)
457 static int byt_irq_reqres(struct irq_data *d)
459 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
461 if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) {
462 dev_err(vg->chip.dev,
463 "unable to lock HW IRQ %lu for IRQ\n",
470 static void byt_irq_relres(struct irq_data *d)
472 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
474 gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
477 static struct irq_chip byt_irqchip = {
479 .irq_mask = byt_irq_mask,
480 .irq_unmask = byt_irq_unmask,
481 .irq_set_type = byt_irq_type,
482 .irq_request_resources = byt_irq_reqres,
483 .irq_release_resources = byt_irq_relres,
486 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
491 /* clear interrupt status trigger registers */
492 for (base = 0; base < vg->chip.ngpio; base += 32) {
493 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
494 writel(0xffffffff, reg);
495 /* make sure trigger bits are cleared, if not then a pin
496 might be misconfigured in bios */
499 dev_err(&vg->pdev->dev,
500 "GPIO interrupt error, pins misconfigured\n");
504 static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
507 struct byt_gpio *vg = d->host_data;
509 irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
511 irq_set_chip_data(virq, vg);
512 irq_set_irq_type(virq, IRQ_TYPE_NONE);
517 static const struct irq_domain_ops byt_gpio_irq_ops = {
518 .map = byt_gpio_irq_map,
521 static int byt_gpio_probe(struct platform_device *pdev)
524 struct gpio_chip *gc;
525 struct resource *mem_rc, *irq_rc;
526 struct device *dev = &pdev->dev;
527 struct acpi_device *acpi_dev;
528 struct pinctrl_gpio_range *range;
529 acpi_handle handle = ACPI_HANDLE(dev);
533 if (acpi_bus_get_device(handle, &acpi_dev))
536 vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
538 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
542 for (range = byt_ranges; range->name; range++) {
543 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
544 vg->chip.ngpio = range->npins;
550 if (!vg->chip.ngpio || !vg->range)
554 platform_set_drvdata(pdev, vg);
556 mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
557 vg->reg_base = devm_ioremap_resource(dev, mem_rc);
558 if (IS_ERR(vg->reg_base))
559 return PTR_ERR(vg->reg_base);
561 spin_lock_init(&vg->lock);
564 gc->label = dev_name(&pdev->dev);
565 gc->owner = THIS_MODULE;
566 gc->request = byt_gpio_request;
567 gc->free = byt_gpio_free;
568 gc->direction_input = byt_gpio_direction_input;
569 gc->direction_output = byt_gpio_direction_output;
570 gc->get = byt_gpio_get;
571 gc->set = byt_gpio_set;
572 gc->dbg_show = byt_gpio_dbg_show;
574 gc->can_sleep = false;
577 /* set up interrupts */
578 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
579 if (irq_rc && irq_rc->start) {
580 hwirq = irq_rc->start;
581 gc->to_irq = byt_gpio_to_irq;
583 vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
584 &byt_gpio_irq_ops, vg);
588 byt_gpio_irq_init_hw(vg);
590 irq_set_handler_data(hwirq, vg);
591 irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
594 ret = gpiochip_add(gc);
596 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
600 pm_runtime_enable(dev);
605 static int byt_gpio_runtime_suspend(struct device *dev)
610 static int byt_gpio_runtime_resume(struct device *dev)
615 static const struct dev_pm_ops byt_gpio_pm_ops = {
616 .runtime_suspend = byt_gpio_runtime_suspend,
617 .runtime_resume = byt_gpio_runtime_resume,
620 static const struct acpi_device_id byt_gpio_acpi_match[] = {
625 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
627 static int byt_gpio_remove(struct platform_device *pdev)
629 struct byt_gpio *vg = platform_get_drvdata(pdev);
632 pm_runtime_disable(&pdev->dev);
633 err = gpiochip_remove(&vg->chip);
635 dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");
640 static struct platform_driver byt_gpio_driver = {
641 .probe = byt_gpio_probe,
642 .remove = byt_gpio_remove,
645 .owner = THIS_MODULE,
646 .pm = &byt_gpio_pm_ops,
647 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
651 static int __init byt_gpio_init(void)
653 return platform_driver_register(&byt_gpio_driver);
656 subsys_initcall(byt_gpio_init);