4 * Copyright (C) 2007-2012 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
7 * Author: Linus Walleij <linus.walleij@linaro.org>
8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
10 #include <linux/module.h>
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
16 #include <linux/irqdomain.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/platform_device.h>
20 #include <linux/gpio.h>
21 #include <linux/list.h>
22 #include <linux/slab.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/platform_data/pinctrl-coh901.h>
26 #include "pinctrl-coh901.h"
28 #define U300_GPIO_PORT_STRIDE (0x30)
30 * Control Register 32bit (R/W)
31 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
32 * gives the number of GPIO pins.
33 * bit 8-2 (mask 0x000001FC) contains the core version ID.
35 #define U300_GPIO_CR (0x00)
36 #define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
37 #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
38 #define U300_GPIO_PXPDIR (0x04)
39 #define U300_GPIO_PXPDOR (0x08)
40 #define U300_GPIO_PXPCR (0x0C)
41 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
42 #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
43 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
44 #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
45 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
46 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
47 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
48 #define U300_GPIO_PXPER (0x10)
49 #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
50 #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
51 #define U300_GPIO_PXIEV (0x14)
52 #define U300_GPIO_PXIEN (0x18)
53 #define U300_GPIO_PXIFR (0x1C)
54 #define U300_GPIO_PXICR (0x20)
55 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
56 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
57 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
58 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
60 /* 8 bits per port, no version has more than 7 ports */
61 #define U300_GPIO_PINS_PER_PORT 8
62 #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
65 struct gpio_chip chip;
66 struct list_head port_list;
71 /* Register offsets */
81 struct u300_gpio_port {
82 struct list_head node;
83 struct u300_gpio *gpio;
85 struct irq_domain *domain;
92 * Macro to expand to read a specific register found in the "gpio"
93 * struct. It requires the struct u300_gpio *gpio variable to exist in
94 * its context. It calculates the port offset from the given pin
95 * offset, muliplies by the port stride and adds the register offset
96 * so it provides a pointer to the desired register.
98 #define U300_PIN_REG(pin, reg) \
99 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
102 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
105 #define U300_PIN_BIT(pin) \
108 struct u300_gpio_confdata {
114 /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
115 #define BS335_GPIO_NUM_PORTS 7
117 #define U300_FLOATING_INPUT { \
118 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
122 #define U300_PULL_UP_INPUT { \
123 .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
127 #define U300_OUTPUT_LOW { \
132 #define U300_OUTPUT_HIGH { \
137 /* Initial configuration */
138 static const struct __initconst u300_gpio_confdata
139 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
140 /* Port 0, pins 0-7 */
151 /* Port 1, pins 0-7 */
162 /* Port 2, pins 0-7 */
173 /* Port 3, pins 0-7 */
184 /* Port 4, pins 0-7 */
195 /* Port 5, pins 0-7 */
206 /* Port 6, pind 0-7 */
220 * to_u300_gpio() - get the pointer to u300_gpio
221 * @chip: the gpio chip member of the structure u300_gpio
223 static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
225 return container_of(chip, struct u300_gpio, chip);
228 static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
231 * Map back to global GPIO space and request muxing, the direction
232 * parameter does not matter for this controller.
234 int gpio = chip->base + offset;
236 return pinctrl_request_gpio(gpio);
239 static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
241 int gpio = chip->base + offset;
243 pinctrl_free_gpio(gpio);
246 static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
248 struct u300_gpio *gpio = to_u300_gpio(chip);
250 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
253 static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
255 struct u300_gpio *gpio = to_u300_gpio(chip);
259 local_irq_save(flags);
261 val = readl(U300_PIN_REG(offset, dor));
263 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
265 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
267 local_irq_restore(flags);
270 static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
272 struct u300_gpio *gpio = to_u300_gpio(chip);
276 local_irq_save(flags);
277 val = readl(U300_PIN_REG(offset, pcr));
278 /* Mask out this pin, note 2 bits per setting */
279 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
280 writel(val, U300_PIN_REG(offset, pcr));
281 local_irq_restore(flags);
285 static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
288 struct u300_gpio *gpio = to_u300_gpio(chip);
293 local_irq_save(flags);
294 val = readl(U300_PIN_REG(offset, pcr));
296 * Drive mode must be set by the special mode set function, set
297 * push/pull mode by default if no mode has been selected.
299 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
300 ((offset & 0x07) << 1));
301 /* mode = 0 means input, else some mode is already set */
303 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
304 ((offset & 0x07) << 1));
305 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
306 << ((offset & 0x07) << 1));
307 writel(val, U300_PIN_REG(offset, pcr));
309 u300_gpio_set(chip, offset, value);
310 local_irq_restore(flags);
314 static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
316 struct u300_gpio *gpio = to_u300_gpio(chip);
317 int portno = offset >> 3;
318 struct u300_gpio_port *port = NULL;
323 list_for_each(p, &gpio->port_list) {
324 port = list_entry(p, struct u300_gpio_port, node);
325 if (port->number == portno) {
331 dev_err(gpio->dev, "could not locate port for GPIO %d IRQ\n",
337 * The local hwirqs on the port are the lower three bits, there
338 * are exactly 8 IRQs per port since they are 8-bit
340 retirq = irq_find_mapping(port->domain, (offset & 0x7));
342 dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d from port %d\n",
343 offset, retirq, port->number);
347 /* Returning -EINVAL means "supported but not available" */
348 int u300_gpio_config_get(struct gpio_chip *chip,
350 unsigned long *config)
352 struct u300_gpio *gpio = to_u300_gpio(chip);
353 enum pin_config_param param = (enum pin_config_param) *config;
357 /* One bit per pin, clamp to bool range */
358 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
360 /* Mask out the two bits for this pin and shift to bits 0,1 */
361 drmode = readl(U300_PIN_REG(offset, pcr));
362 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
363 drmode >>= ((offset & 0x07) << 1);
366 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
373 case PIN_CONFIG_BIAS_PULL_UP:
380 case PIN_CONFIG_DRIVE_PUSH_PULL:
382 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
387 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
389 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
394 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
396 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
407 int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
408 enum pin_config_param param)
410 struct u300_gpio *gpio = to_u300_gpio(chip);
414 local_irq_save(flags);
416 case PIN_CONFIG_BIAS_DISABLE:
417 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
418 val = readl(U300_PIN_REG(offset, per));
419 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
421 case PIN_CONFIG_BIAS_PULL_UP:
422 val = readl(U300_PIN_REG(offset, per));
423 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
425 case PIN_CONFIG_DRIVE_PUSH_PULL:
426 val = readl(U300_PIN_REG(offset, pcr));
427 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
428 << ((offset & 0x07) << 1));
429 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
430 << ((offset & 0x07) << 1));
431 writel(val, U300_PIN_REG(offset, pcr));
433 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
434 val = readl(U300_PIN_REG(offset, pcr));
435 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
436 << ((offset & 0x07) << 1));
437 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
438 << ((offset & 0x07) << 1));
439 writel(val, U300_PIN_REG(offset, pcr));
441 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
442 val = readl(U300_PIN_REG(offset, pcr));
443 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
444 << ((offset & 0x07) << 1));
445 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
446 << ((offset & 0x07) << 1));
447 writel(val, U300_PIN_REG(offset, pcr));
450 local_irq_restore(flags);
451 dev_err(gpio->dev, "illegal configuration requested\n");
454 local_irq_restore(flags);
458 static struct gpio_chip u300_gpio_chip = {
459 .label = "u300-gpio-chip",
460 .owner = THIS_MODULE,
461 .request = u300_gpio_request,
462 .free = u300_gpio_free,
463 .get = u300_gpio_get,
464 .set = u300_gpio_set,
465 .direction_input = u300_gpio_direction_input,
466 .direction_output = u300_gpio_direction_output,
467 .to_irq = u300_gpio_to_irq,
470 static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
474 val = readl(U300_PIN_REG(offset, icr));
475 /* Set mode depending on state */
476 if (u300_gpio_get(&gpio->chip, offset)) {
477 /* High now, let's trigger on falling edge next then */
478 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
479 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
482 /* Low now, let's trigger on rising edge next then */
483 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
484 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
489 static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
491 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
492 struct u300_gpio *gpio = port->gpio;
493 int offset = (port->number << 3) + d->hwirq;
496 if ((trigger & IRQF_TRIGGER_RISING) &&
497 (trigger & IRQF_TRIGGER_FALLING)) {
499 * The GPIO block can only trigger on falling OR rising edges,
500 * not both. So we need to toggle the mode whenever the pin
501 * goes from one state to the other with a special state flag
504 "trigger on both rising and falling edge on pin %d\n",
506 port->toggle_edge_mode |= U300_PIN_BIT(offset);
507 u300_toggle_trigger(gpio, offset);
508 } else if (trigger & IRQF_TRIGGER_RISING) {
509 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
511 val = readl(U300_PIN_REG(offset, icr));
512 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
513 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
514 } else if (trigger & IRQF_TRIGGER_FALLING) {
515 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
517 val = readl(U300_PIN_REG(offset, icr));
518 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
519 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
525 static void u300_gpio_irq_enable(struct irq_data *d)
527 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
528 struct u300_gpio *gpio = port->gpio;
529 int offset = (port->number << 3) + d->hwirq;
533 dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
534 d->hwirq, port->name, offset);
535 local_irq_save(flags);
536 val = readl(U300_PIN_REG(offset, ien));
537 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
538 local_irq_restore(flags);
541 static void u300_gpio_irq_disable(struct irq_data *d)
543 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
544 struct u300_gpio *gpio = port->gpio;
545 int offset = (port->number << 3) + d->hwirq;
549 local_irq_save(flags);
550 val = readl(U300_PIN_REG(offset, ien));
551 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
552 local_irq_restore(flags);
555 static struct irq_chip u300_gpio_irqchip = {
556 .name = "u300-gpio-irqchip",
557 .irq_enable = u300_gpio_irq_enable,
558 .irq_disable = u300_gpio_irq_disable,
559 .irq_set_type = u300_gpio_irq_type,
563 static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
565 struct u300_gpio_port *port = irq_get_handler_data(irq);
566 struct u300_gpio *gpio = port->gpio;
567 int pinoffset = port->number << 3; /* get the right stride */
570 desc->irq_data.chip->irq_ack(&desc->irq_data);
571 /* Read event register */
572 val = readl(U300_PIN_REG(pinoffset, iev));
573 /* Mask relevant bits */
574 val &= 0xFFU; /* 8 bits per port */
575 /* ACK IRQ (clear event) */
576 writel(val, U300_PIN_REG(pinoffset, iev));
578 /* Call IRQ handler */
582 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
583 int pin_irq = irq_find_mapping(port->domain, irqoffset);
584 int offset = pinoffset + irqoffset;
586 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
588 generic_handle_irq(pin_irq);
590 * Triggering IRQ on both rising and falling edge
593 if (port->toggle_edge_mode & U300_PIN_BIT(offset))
594 u300_toggle_trigger(gpio, offset);
598 desc->irq_data.chip->irq_unmask(&desc->irq_data);
601 static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
603 const struct u300_gpio_confdata *conf)
605 /* Set mode: input or output */
607 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
609 /* Deactivate bias mode for output */
610 u300_gpio_config_set(&gpio->chip, offset,
611 PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
613 /* Set drive mode for output */
614 u300_gpio_config_set(&gpio->chip, offset,
615 PIN_CONFIG_DRIVE_PUSH_PULL);
617 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
618 offset, conf->outval);
620 u300_gpio_direction_input(&gpio->chip, offset);
622 /* Always set output low on input pins */
623 u300_gpio_set(&gpio->chip, offset, 0);
625 /* Set bias mode for input */
626 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
628 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
629 offset, conf->bias_mode);
633 static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
634 struct u300_gpio_platform *plat)
638 /* Write default config and values to all pins */
639 for (i = 0; i < plat->ports; i++) {
640 for (j = 0; j < 8; j++) {
641 const struct u300_gpio_confdata *conf;
642 int offset = (i*8) + j;
644 conf = &bs335_gpio_config[i][j];
645 u300_gpio_init_pin(gpio, offset, conf);
650 static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
652 struct u300_gpio_port *port;
653 struct list_head *p, *n;
655 list_for_each_safe(p, n, &gpio->port_list) {
656 port = list_entry(p, struct u300_gpio_port, node);
657 list_del(&port->node);
659 irq_domain_remove(port->domain);
665 * Here we map a GPIO in the local gpio_chip pin space to a pin in
666 * the local pinctrl pin space. The pin controller used is
669 struct coh901_pinpair {
671 unsigned int pin_base;
674 #define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
676 static struct coh901_pinpair coh901_pintable[] = {
677 COH901_PINRANGE(10, 426),
678 COH901_PINRANGE(11, 180),
679 COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
680 COH901_PINRANGE(13, 179),
681 COH901_PINRANGE(14, 178),
682 COH901_PINRANGE(16, 194),
683 COH901_PINRANGE(17, 193),
684 COH901_PINRANGE(18, 192),
685 COH901_PINRANGE(19, 191),
686 COH901_PINRANGE(20, 186),
687 COH901_PINRANGE(21, 185),
688 COH901_PINRANGE(22, 184),
689 COH901_PINRANGE(23, 183),
690 COH901_PINRANGE(24, 182),
691 COH901_PINRANGE(25, 181),
694 static int __init u300_gpio_probe(struct platform_device *pdev)
696 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
697 struct u300_gpio *gpio;
698 struct resource *memres;
705 gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
709 gpio->chip = u300_gpio_chip;
710 gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
711 gpio->chip.dev = &pdev->dev;
712 gpio->chip.base = plat->gpio_base;
713 gpio->dev = &pdev->dev;
715 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
716 gpio->base = devm_ioremap_resource(&pdev->dev, memres);
717 if (IS_ERR(gpio->base))
718 return PTR_ERR(gpio->base);
720 gpio->clk = devm_clk_get(gpio->dev, NULL);
721 if (IS_ERR(gpio->clk)) {
722 err = PTR_ERR(gpio->clk);
723 dev_err(gpio->dev, "could not get GPIO clock\n");
727 err = clk_prepare_enable(gpio->clk);
729 dev_err(gpio->dev, "could not enable GPIO clock\n");
734 "initializing GPIO Controller COH 901 571/3\n");
735 gpio->stride = U300_GPIO_PORT_STRIDE;
736 gpio->pcr = U300_GPIO_PXPCR;
737 gpio->dor = U300_GPIO_PXPDOR;
738 gpio->dir = U300_GPIO_PXPDIR;
739 gpio->per = U300_GPIO_PXPER;
740 gpio->icr = U300_GPIO_PXICR;
741 gpio->ien = U300_GPIO_PXIEN;
742 gpio->iev = U300_GPIO_PXIEV;
743 ifr = U300_GPIO_PXIFR;
745 val = readl(gpio->base + U300_GPIO_CR);
746 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
747 "number of cores: %d totalling %d pins\n",
748 ((val & 0x000001FC) >> 2),
749 ((val & 0x0000FE00) >> 9),
750 ((val & 0x0000FE00) >> 9) * 8);
751 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
752 gpio->base + U300_GPIO_CR);
753 u300_gpio_init_coh901571(gpio, plat);
755 /* Add each port with its IRQ separately */
756 INIT_LIST_HEAD(&gpio->port_list);
757 for (portno = 0 ; portno < plat->ports; portno++) {
758 struct u300_gpio_port *port =
759 kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
762 dev_err(gpio->dev, "out of memory\n");
767 snprintf(port->name, 8, "gpio%d", portno);
768 port->number = portno;
771 port->irq = platform_get_irq_byname(pdev,
774 dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq,
777 port->domain = irq_domain_add_linear(pdev->dev.of_node,
778 U300_GPIO_PINS_PER_PORT,
779 &irq_domain_simple_ops,
786 irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
787 irq_set_handler_data(port->irq, port);
789 /* For each GPIO pin set the unique IRQ handler */
790 for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
791 int irqno = irq_create_mapping(port->domain, i);
793 dev_dbg(gpio->dev, "GPIO%d on port %s gets IRQ %d\n",
794 gpio->chip.base + (port->number << 3) + i,
796 irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
798 set_irq_flags(irqno, IRQF_VALID);
799 irq_set_chip_data(irqno, port);
802 /* Turns off irq force (test register) for this port */
803 writel(0x0, gpio->base + portno * gpio->stride + ifr);
805 list_add_tail(&port->node, &gpio->port_list);
807 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
809 err = gpiochip_add(&gpio->chip);
811 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
816 * Add pinctrl pin ranges, the pin controller must be registered
819 for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
820 struct coh901_pinpair *p = &coh901_pintable[i];
822 err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
823 p->offset, p->pin_base, 1);
828 platform_set_drvdata(pdev, gpio);
833 err = gpiochip_remove(&gpio->chip);
837 u300_gpio_free_ports(gpio);
838 clk_disable_unprepare(gpio->clk);
839 dev_err(&pdev->dev, "module ERROR:%d\n", err);
843 static int __exit u300_gpio_remove(struct platform_device *pdev)
845 struct u300_gpio *gpio = platform_get_drvdata(pdev);
848 /* Turn off the GPIO block */
849 writel(0x00000000U, gpio->base + U300_GPIO_CR);
851 err = gpiochip_remove(&gpio->chip);
853 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
856 u300_gpio_free_ports(gpio);
857 clk_disable_unprepare(gpio->clk);
858 platform_set_drvdata(pdev, NULL);
862 static struct platform_driver u300_gpio_driver = {
866 .remove = __exit_p(u300_gpio_remove),
869 static int __init u300_gpio_init(void)
871 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
874 static void __exit u300_gpio_exit(void)
876 platform_driver_unregister(&u300_gpio_driver);
879 arch_initcall(u300_gpio_init);
880 module_exit(u300_gpio_exit);
882 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
883 MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
884 MODULE_LICENSE("GPL");