2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/err.h>
18 #include <linux/gpio.h>
19 #include <linux/device.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_irq.h>
28 /* EXYNOS5440 GPIO and Pinctrl register offsets */
32 #define GPIO_TYPE 0x0C
42 #define EXYNOS5440_MAX_PINS 23
43 #define EXYNOS5440_MAX_GPIO_INT 8
44 #define PIN_NAME_LENGTH 10
46 #define GROUP_SUFFIX "-grp"
47 #define GSUFFIX_LEN sizeof(GROUP_SUFFIX)
48 #define FUNCTION_SUFFIX "-mux"
49 #define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX)
52 * pin configuration type and its value are packed together into a 16-bits.
53 * The upper 8-bits represent the configuration type and the lower 8-bits
54 * hold the value of the configuration type.
56 #define PINCFG_TYPE_MASK 0xFF
57 #define PINCFG_VALUE_SHIFT 8
58 #define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
59 #define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
60 #define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
61 #define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
65 * enum pincfg_type - possible pin configuration types supported.
66 * @PINCFG_TYPE_PUD: Pull up/down configuration.
67 * @PINCFG_TYPE_DRV: Drive strength configuration.
68 * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
69 * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
74 PINCFG_TYPE_SKEW_RATE,
75 PINCFG_TYPE_INPUT_TYPE
79 * struct exynos5440_pin_group: represent group of pins for pincfg setting.
80 * @name: name of the pin group, used to lookup the group.
81 * @pins: the pins included in this group.
82 * @num_pins: number of pins included in this group.
84 struct exynos5440_pin_group {
86 const unsigned int *pins;
91 * struct exynos5440_pmx_func: represent a pin function.
92 * @name: name of the pin function, used to lookup the function.
93 * @groups: one or more names of pin groups that provide this function.
94 * @num_groups: number of groups included in @groups.
95 * @function: the function number to be programmed when selected.
97 struct exynos5440_pmx_func {
101 unsigned long function;
105 * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
106 * @reg_base: ioremapped based address of the register space.
107 * @gc: gpio chip registered with gpiolib.
108 * @pin_groups: list of pin groups parsed from device tree.
109 * @nr_groups: number of pin groups available.
110 * @pmx_functions: list of pin functions parsed from device tree.
111 * @nr_functions: number of pin functions available.
113 struct exynos5440_pinctrl_priv_data {
114 void __iomem *reg_base;
115 struct gpio_chip *gc;
116 struct irq_domain *irq_domain;
118 const struct exynos5440_pin_group *pin_groups;
119 unsigned int nr_groups;
120 const struct exynos5440_pmx_func *pmx_functions;
121 unsigned int nr_functions;
125 * struct exynos5440_gpio_intr_data: private data for gpio interrupts.
126 * @priv: driver's private runtime data.
127 * @gpio_int: gpio interrupt number.
129 struct exynos5440_gpio_intr_data {
130 struct exynos5440_pinctrl_priv_data *priv;
131 unsigned int gpio_int;
134 /* list of all possible config options supported */
135 static struct pin_config {
137 unsigned int cfg_type;
139 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
140 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
141 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
142 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
145 /* check if the selector is a valid pin group selector */
146 static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
148 struct exynos5440_pinctrl_priv_data *priv;
150 priv = pinctrl_dev_get_drvdata(pctldev);
151 return priv->nr_groups;
154 /* return the name of the group selected by the group selector */
155 static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
158 struct exynos5440_pinctrl_priv_data *priv;
160 priv = pinctrl_dev_get_drvdata(pctldev);
161 return priv->pin_groups[selector].name;
164 /* return the pin numbers associated with the specified group */
165 static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
166 unsigned selector, const unsigned **pins, unsigned *num_pins)
168 struct exynos5440_pinctrl_priv_data *priv;
170 priv = pinctrl_dev_get_drvdata(pctldev);
171 *pins = priv->pin_groups[selector].pins;
172 *num_pins = priv->pin_groups[selector].num_pins;
176 /* create pinctrl_map entries by parsing device tree nodes */
177 static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
178 struct device_node *np, struct pinctrl_map **maps,
181 struct device *dev = pctldev->dev;
182 struct pinctrl_map *map;
183 unsigned long *cfg = NULL;
185 int cfg_cnt = 0, map_cnt = 0, idx = 0;
187 /* count the number of config options specfied in the node */
188 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
189 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
193 * Find out the number of map entries to create. All the config options
194 * can be accomadated into a single config map entry.
198 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
201 dev_err(dev, "node %s does not have either config or function "
202 "configurations\n", np->name);
206 /* Allocate memory for pin-map entries */
207 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
209 dev_err(dev, "could not alloc memory for pin-maps\n");
215 * Allocate memory for pin group name. The pin group name is derived
216 * from the node name from which these map entries are be created.
218 gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL);
220 dev_err(dev, "failed to alloc memory for group name\n");
223 sprintf(gname, "%s%s", np->name, GROUP_SUFFIX);
226 * don't have config options? then skip over to creating function
232 /* Allocate memory for config entries */
233 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
235 dev_err(dev, "failed to alloc memory for configs\n");
239 /* Prepare a list of config settings */
240 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
242 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
244 PINCFG_PACK(pcfgs[idx].cfg_type, value);
247 /* create the config map entry */
248 map[*nmaps].data.configs.group_or_pin = gname;
249 map[*nmaps].data.configs.configs = cfg;
250 map[*nmaps].data.configs.num_configs = cfg_cnt;
251 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
255 /* create the function map entry */
256 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
257 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL);
259 dev_err(dev, "failed to alloc memory for func name\n");
262 sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX);
264 map[*nmaps].data.mux.group = gname;
265 map[*nmaps].data.mux.function = fname;
266 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
282 /* free the memory allocated to hold the pin-map table */
283 static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
284 struct pinctrl_map *map, unsigned num_maps)
288 for (idx = 0; idx < num_maps; idx++) {
289 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
290 kfree(map[idx].data.mux.function);
292 kfree(map[idx].data.mux.group);
293 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
294 kfree(map[idx].data.configs.configs);
296 kfree(map[idx].data.configs.group_or_pin);
303 /* list of pinctrl callbacks for the pinctrl core */
304 static const struct pinctrl_ops exynos5440_pctrl_ops = {
305 .get_groups_count = exynos5440_get_group_count,
306 .get_group_name = exynos5440_get_group_name,
307 .get_group_pins = exynos5440_get_group_pins,
308 .dt_node_to_map = exynos5440_dt_node_to_map,
309 .dt_free_map = exynos5440_dt_free_map,
312 /* check if the selector is a valid pin function selector */
313 static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
315 struct exynos5440_pinctrl_priv_data *priv;
317 priv = pinctrl_dev_get_drvdata(pctldev);
318 return priv->nr_functions;
321 /* return the name of the pin function specified */
322 static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
325 struct exynos5440_pinctrl_priv_data *priv;
327 priv = pinctrl_dev_get_drvdata(pctldev);
328 return priv->pmx_functions[selector].name;
331 /* return the groups associated for the specified function selector */
332 static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
333 unsigned selector, const char * const **groups,
334 unsigned * const num_groups)
336 struct exynos5440_pinctrl_priv_data *priv;
338 priv = pinctrl_dev_get_drvdata(pctldev);
339 *groups = priv->pmx_functions[selector].groups;
340 *num_groups = priv->pmx_functions[selector].num_groups;
344 /* enable or disable a pinmux function */
345 static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
346 unsigned group, bool enable)
348 struct exynos5440_pinctrl_priv_data *priv;
353 priv = pinctrl_dev_get_drvdata(pctldev);
354 base = priv->reg_base;
355 function = priv->pmx_functions[selector].function;
357 data = readl(base + GPIO_MUX);
359 data |= (1 << function);
361 data &= ~(1 << function);
362 writel(data, base + GPIO_MUX);
365 /* enable a specified pinmux by writing to registers */
366 static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
369 exynos5440_pinmux_setup(pctldev, selector, group, true);
373 /* disable a specified pinmux by writing to registers */
374 static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
375 unsigned selector, unsigned group)
377 exynos5440_pinmux_setup(pctldev, selector, group, false);
381 * The calls to gpio_direction_output() and gpio_direction_input()
382 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
383 * function called from the gpiolib interface).
385 static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
386 struct pinctrl_gpio_range *range, unsigned offset, bool input)
391 /* list of pinmux callbacks for the pinmux vertical in pinctrl core */
392 static const struct pinmux_ops exynos5440_pinmux_ops = {
393 .get_functions_count = exynos5440_get_functions_count,
394 .get_function_name = exynos5440_pinmux_get_fname,
395 .get_function_groups = exynos5440_pinmux_get_groups,
396 .enable = exynos5440_pinmux_enable,
397 .disable = exynos5440_pinmux_disable,
398 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
401 /* set the pin config settings for a specified pin */
402 static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
403 unsigned long config)
405 struct exynos5440_pinctrl_priv_data *priv;
407 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config);
408 u32 cfg_value = PINCFG_UNPACK_VALUE(config);
411 priv = pinctrl_dev_get_drvdata(pctldev);
412 base = priv->reg_base;
415 case PINCFG_TYPE_PUD:
416 /* first set pull enable/disable bit */
417 data = readl(base + GPIO_PE);
421 writel(data, base + GPIO_PE);
423 /* then set pull up/down bit */
424 data = readl(base + GPIO_PS);
428 writel(data, base + GPIO_PS);
431 case PINCFG_TYPE_DRV:
432 /* set the first bit of the drive strength */
433 data = readl(base + GPIO_DS0);
435 data |= ((cfg_value & 1) << pin);
436 writel(data, base + GPIO_DS0);
439 /* set the second bit of the driver strength */
440 data = readl(base + GPIO_DS1);
442 data |= ((cfg_value & 1) << pin);
443 writel(data, base + GPIO_DS1);
445 case PINCFG_TYPE_SKEW_RATE:
446 data = readl(base + GPIO_SR);
448 data |= ((cfg_value & 1) << pin);
449 writel(data, base + GPIO_SR);
451 case PINCFG_TYPE_INPUT_TYPE:
452 data = readl(base + GPIO_TYPE);
454 data |= ((cfg_value & 1) << pin);
455 writel(data, base + GPIO_TYPE);
465 /* get the pin config settings for a specified pin */
466 static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
467 unsigned long *config)
469 struct exynos5440_pinctrl_priv_data *priv;
471 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
474 priv = pinctrl_dev_get_drvdata(pctldev);
475 base = priv->reg_base;
478 case PINCFG_TYPE_PUD:
479 data = readl(base + GPIO_PE);
480 data = (data >> pin) & 1;
484 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
486 case PINCFG_TYPE_DRV:
487 data = readl(base + GPIO_DS0);
488 data = (data >> pin) & 1;
490 data = readl(base + GPIO_DS1);
491 data = (data >> pin) & 1;
492 *config |= (data << 1);
494 case PINCFG_TYPE_SKEW_RATE:
495 data = readl(base + GPIO_SR);
496 *config = (data >> pin) & 1;
498 case PINCFG_TYPE_INPUT_TYPE:
499 data = readl(base + GPIO_TYPE);
500 *config = (data >> pin) & 1;
510 /* set the pin config settings for a specified pin group */
511 static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
512 unsigned group, unsigned long config)
514 struct exynos5440_pinctrl_priv_data *priv;
515 const unsigned int *pins;
518 priv = pinctrl_dev_get_drvdata(pctldev);
519 pins = priv->pin_groups[group].pins;
521 for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
522 exynos5440_pinconf_set(pctldev, pins[cnt], config);
527 /* get the pin config settings for a specified pin group */
528 static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
529 unsigned int group, unsigned long *config)
531 struct exynos5440_pinctrl_priv_data *priv;
532 const unsigned int *pins;
534 priv = pinctrl_dev_get_drvdata(pctldev);
535 pins = priv->pin_groups[group].pins;
536 exynos5440_pinconf_get(pctldev, pins[0], config);
540 /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
541 static const struct pinconf_ops exynos5440_pinconf_ops = {
542 .pin_config_get = exynos5440_pinconf_get,
543 .pin_config_set = exynos5440_pinconf_set,
544 .pin_config_group_get = exynos5440_pinconf_group_get,
545 .pin_config_group_set = exynos5440_pinconf_group_set,
548 /* gpiolib gpio_set callback function */
549 static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
551 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
552 void __iomem *base = priv->reg_base;
555 data = readl(base + GPIO_VAL);
556 data &= ~(1 << offset);
559 writel(data, base + GPIO_VAL);
562 /* gpiolib gpio_get callback function */
563 static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
565 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
566 void __iomem *base = priv->reg_base;
569 data = readl(base + GPIO_IN);
575 /* gpiolib gpio_direction_input callback function */
576 static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
578 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
579 void __iomem *base = priv->reg_base;
582 /* first disable the data output enable on this pin */
583 data = readl(base + GPIO_OE);
584 data &= ~(1 << offset);
585 writel(data, base + GPIO_OE);
587 /* now enable input on this pin */
588 data = readl(base + GPIO_IE);
590 writel(data, base + GPIO_IE);
594 /* gpiolib gpio_direction_output callback function */
595 static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
598 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
599 void __iomem *base = priv->reg_base;
602 exynos5440_gpio_set(gc, offset, value);
604 /* first disable the data input enable on this pin */
605 data = readl(base + GPIO_IE);
606 data &= ~(1 << offset);
607 writel(data, base + GPIO_IE);
609 /* now enable output on this pin */
610 data = readl(base + GPIO_OE);
612 writel(data, base + GPIO_OE);
616 /* gpiolib gpio_to_irq callback function */
617 static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
619 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
622 if (offset < 16 || offset > 23)
625 if (!priv->irq_domain)
628 virq = irq_create_mapping(priv->irq_domain, offset - 16);
629 return virq ? : -ENXIO;
632 /* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
633 static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
634 struct device_node *cfg_np, unsigned int **pin_list,
637 struct device *dev = &pdev->dev;
638 struct property *prop;
640 prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
644 *npins = prop->length / sizeof(unsigned long);
646 dev_err(dev, "invalid pin list in %s node", cfg_np->name);
650 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
652 dev_err(dev, "failed to allocate memory for pin list\n");
656 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
661 * Parse the information about all the available pin groups and pin functions
662 * from device node of the pin-controller.
664 static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
665 struct exynos5440_pinctrl_priv_data *priv)
667 struct device *dev = &pdev->dev;
668 struct device_node *dev_np = dev->of_node;
669 struct device_node *cfg_np;
670 struct exynos5440_pin_group *groups, *grp;
671 struct exynos5440_pmx_func *functions, *func;
673 unsigned int npins, grp_cnt, func_idx = 0;
677 grp_cnt = of_get_child_count(dev_np);
681 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
683 dev_err(dev, "failed allocate memory for ping group list\n");
688 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
690 dev_err(dev, "failed to allocate memory for function list\n");
696 * Iterate over all the child nodes of the pin controller node
697 * and create pin groups and pin function lists.
699 for_each_child_of_node(dev_np, cfg_np) {
702 ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
706 goto skip_to_pin_function;
709 /* derive pin group name from the node name */
710 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN,
713 dev_err(dev, "failed to alloc memory for group name\n");
716 sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX);
719 grp->pins = pin_list;
720 grp->num_pins = npins;
723 skip_to_pin_function:
724 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
729 /* derive function name from the node name */
730 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN,
733 dev_err(dev, "failed to alloc memory for func name\n");
736 sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX);
739 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
741 dev_err(dev, "failed to alloc memory for group list "
745 func->groups[0] = gname;
746 func->num_groups = gname ? 1 : 0;
747 func->function = function;
752 priv->pin_groups = groups;
753 priv->nr_groups = grp_cnt;
754 priv->pmx_functions = functions;
755 priv->nr_functions = func_idx;
759 /* register the pinctrl interface with the pinctrl subsystem */
760 static int exynos5440_pinctrl_register(struct platform_device *pdev,
761 struct exynos5440_pinctrl_priv_data *priv)
763 struct device *dev = &pdev->dev;
764 struct pinctrl_desc *ctrldesc;
765 struct pinctrl_dev *pctl_dev;
766 struct pinctrl_pin_desc *pindesc, *pdesc;
767 struct pinctrl_gpio_range grange;
771 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
773 dev_err(dev, "could not allocate memory for pinctrl desc\n");
777 ctrldesc->name = "exynos5440-pinctrl";
778 ctrldesc->owner = THIS_MODULE;
779 ctrldesc->pctlops = &exynos5440_pctrl_ops;
780 ctrldesc->pmxops = &exynos5440_pinmux_ops;
781 ctrldesc->confops = &exynos5440_pinconf_ops;
783 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
784 EXYNOS5440_MAX_PINS, GFP_KERNEL);
786 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
789 ctrldesc->pins = pindesc;
790 ctrldesc->npins = EXYNOS5440_MAX_PINS;
792 /* dynamically populate the pin number and pin name for pindesc */
793 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
797 * allocate space for storing the dynamically generated names for all
798 * the pins which belong to this pin-controller.
800 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
801 ctrldesc->npins, GFP_KERNEL);
803 dev_err(&pdev->dev, "mem alloc for pin names failed\n");
807 /* for each pin, set the name of the pin */
808 for (pin = 0; pin < ctrldesc->npins; pin++) {
809 sprintf(pin_names, "gpio%02d", pin);
810 pdesc = pindesc + pin;
811 pdesc->name = pin_names;
812 pin_names += PIN_NAME_LENGTH;
815 ret = exynos5440_pinctrl_parse_dt(pdev, priv);
819 pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
821 dev_err(&pdev->dev, "could not register pinctrl driver\n");
825 grange.name = "exynos5440-pctrl-gpio-range";
828 grange.npins = EXYNOS5440_MAX_PINS;
829 grange.gc = priv->gc;
830 pinctrl_add_gpio_range(pctl_dev, &grange);
834 /* register the gpiolib interface with the gpiolib subsystem */
835 static int exynos5440_gpiolib_register(struct platform_device *pdev,
836 struct exynos5440_pinctrl_priv_data *priv)
838 struct gpio_chip *gc;
841 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
843 dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
849 gc->ngpio = EXYNOS5440_MAX_PINS;
850 gc->dev = &pdev->dev;
851 gc->set = exynos5440_gpio_set;
852 gc->get = exynos5440_gpio_get;
853 gc->direction_input = exynos5440_gpio_direction_input;
854 gc->direction_output = exynos5440_gpio_direction_output;
855 gc->to_irq = exynos5440_gpio_to_irq;
856 gc->label = "gpiolib-exynos5440";
857 gc->owner = THIS_MODULE;
858 ret = gpiochip_add(gc);
860 dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
861 "code: %d\n", gc->label, ret);
868 /* unregister the gpiolib interface with the gpiolib subsystem */
869 static int exynos5440_gpiolib_unregister(struct platform_device *pdev,
870 struct exynos5440_pinctrl_priv_data *priv)
872 int ret = gpiochip_remove(priv->gc);
874 dev_err(&pdev->dev, "gpio chip remove failed\n");
880 static void exynos5440_gpio_irq_unmask(struct irq_data *irqd)
882 struct exynos5440_pinctrl_priv_data *d;
883 unsigned long gpio_int;
885 d = irq_data_get_irq_chip_data(irqd);
886 gpio_int = readl(d->reg_base + GPIO_INT);
887 gpio_int |= 1 << irqd->hwirq;
888 writel(gpio_int, d->reg_base + GPIO_INT);
891 static void exynos5440_gpio_irq_mask(struct irq_data *irqd)
893 struct exynos5440_pinctrl_priv_data *d;
894 unsigned long gpio_int;
896 d = irq_data_get_irq_chip_data(irqd);
897 gpio_int = readl(d->reg_base + GPIO_INT);
898 gpio_int &= ~(1 << irqd->hwirq);
899 writel(gpio_int, d->reg_base + GPIO_INT);
902 /* irq_chip for gpio interrupts */
903 static struct irq_chip exynos5440_gpio_irq_chip = {
904 .name = "exynos5440_gpio_irq_chip",
905 .irq_unmask = exynos5440_gpio_irq_unmask,
906 .irq_mask = exynos5440_gpio_irq_mask,
909 /* interrupt handler for GPIO interrupts 0..7 */
910 static irqreturn_t exynos5440_gpio_irq(int irq, void *data)
912 struct exynos5440_gpio_intr_data *intd = data;
913 struct exynos5440_pinctrl_priv_data *d = intd->priv;
916 virq = irq_linear_revmap(d->irq_domain, intd->gpio_int);
919 generic_handle_irq(virq);
923 static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq,
926 struct exynos5440_pinctrl_priv_data *d = h->host_data;
928 irq_set_chip_data(virq, d);
929 irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip,
931 set_irq_flags(virq, IRQF_VALID);
935 /* irq domain callbacks for gpio interrupt controller */
936 static const struct irq_domain_ops exynos5440_gpio_irqd_ops = {
937 .map = exynos5440_gpio_irq_map,
938 .xlate = irq_domain_xlate_twocell,
941 /* setup handling of gpio interrupts */
942 static int exynos5440_gpio_irq_init(struct platform_device *pdev,
943 struct exynos5440_pinctrl_priv_data *priv)
945 struct device *dev = &pdev->dev;
946 struct exynos5440_gpio_intr_data *intd;
949 intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT,
952 dev_err(dev, "failed to allocate memory for gpio intr data\n");
956 for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) {
957 irq = irq_of_parse_and_map(dev->of_node, i);
959 dev_err(dev, "irq parsing failed\n");
965 ret = devm_request_irq(dev, irq, exynos5440_gpio_irq,
966 0, dev_name(dev), intd++);
968 dev_err(dev, "irq request failed\n");
973 priv->irq_domain = irq_domain_add_linear(dev->of_node,
974 EXYNOS5440_MAX_GPIO_INT,
975 &exynos5440_gpio_irqd_ops, priv);
976 if (!priv->irq_domain) {
977 dev_err(dev, "failed to create irq domain\n");
984 static int exynos5440_pinctrl_probe(struct platform_device *pdev)
986 struct device *dev = &pdev->dev;
987 struct exynos5440_pinctrl_priv_data *priv;
988 struct resource *res;
992 dev_err(dev, "device tree node not found\n");
996 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
998 dev_err(dev, "could not allocate memory for private data\n");
1002 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1004 dev_err(dev, "cannot find IO resource\n");
1008 priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
1009 if (IS_ERR(priv->reg_base))
1010 return PTR_ERR(priv->reg_base);
1012 ret = exynos5440_gpiolib_register(pdev, priv);
1016 ret = exynos5440_pinctrl_register(pdev, priv);
1018 exynos5440_gpiolib_unregister(pdev, priv);
1022 ret = exynos5440_gpio_irq_init(pdev, priv);
1024 dev_err(dev, "failed to setup gpio interrupts\n");
1028 platform_set_drvdata(pdev, priv);
1029 dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
1033 static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
1034 { .compatible = "samsung,exynos5440-pinctrl" },
1037 MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match);
1039 static struct platform_driver exynos5440_pinctrl_driver = {
1040 .probe = exynos5440_pinctrl_probe,
1042 .name = "exynos5440-pinctrl",
1043 .owner = THIS_MODULE,
1044 .of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match),
1048 static int __init exynos5440_pinctrl_drv_register(void)
1050 return platform_driver_register(&exynos5440_pinctrl_driver);
1052 postcore_initcall(exynos5440_pinctrl_drv_register);
1054 static void __exit exynos5440_pinctrl_drv_unregister(void)
1056 platform_driver_unregister(&exynos5440_pinctrl_driver);
1058 module_exit(exynos5440_pinctrl_drv_unregister);
1060 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1061 MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
1062 MODULE_LICENSE("GPL v2");