drivers/pinctrl/pinctrl-msm.c

   1 /*
   2  * Copyright (c) 2013, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/pinctrl/pinctrl.h>
  23 #include <linux/pinctrl/pinmux.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26 #include <linux/slab.h>
  27 #include <linux/gpio.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/irq.h>
  30 #include <linux/irqchip/chained_irq.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/spinlock.h>
  33
  34 #include "core.h"
  35 #include "pinconf.h"
  36 #include "pinctrl-msm.h"
  37 #include "pinctrl-utils.h"
  38
  39 #define MAX_NR_GPIO 300
  40
  41 /**
  42  * struct msm_pinctrl - state for a pinctrl-msm device
  43  * @dev:            device handle.
  44  * @pctrl:          pinctrl handle.
  45  * @domain:         irqdomain handle.
  46  * @chip:           gpiochip handle.
  47  * @irq:            parent irq for the TLMM irq_chip.
  48  * @lock:           Spinlock to protect register resources as well
  49  *                  as msm_pinctrl data structures.
  50  * @enabled_irqs:   Bitmap of currently enabled irqs.
  51  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
  52  *                  detection.
  53  * @wake_irqs:      Bitmap of irqs with requested as wakeup source.
  54  * @soc;            Reference to soc_data of platform specific data.
  55  * @regs:           Base address for the TLMM register map.
  56  */
  57 struct msm_pinctrl {
  58         struct device *dev;
  59         struct pinctrl_dev *pctrl;
  60         struct irq_domain *domain;
  61         struct gpio_chip chip;
  62         int irq;
  63
  64         spinlock_t lock;
  65
  66         DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
  67         DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
  68         DECLARE_BITMAP(wake_irqs, MAX_NR_GPIO);
  69
  70         const struct msm_pinctrl_soc_data *soc;
  71         void __iomem *regs;
  72 };
  73
  74 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
  75 {
  76         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  77
  78         return pctrl->soc->ngroups;
  79 }
  80
  81 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
  82                                       unsigned group)
  83 {
  84         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  85
  86         return pctrl->soc->groups[group].name;
  87 }
  88
  89 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
  90                               unsigned group,
  91                               const unsigned **pins,
  92                               unsigned *num_pins)
  93 {
  94         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  95
  96         *pins = pctrl->soc->groups[group].pins;
  97         *num_pins = pctrl->soc->groups[group].npins;
  98         return 0;
  99 }
 100
 101 static const struct pinctrl_ops msm_pinctrl_ops = {
 102         .get_groups_count       = msm_get_groups_count,
 103         .get_group_name         = msm_get_group_name,
 104         .get_group_pins         = msm_get_group_pins,
 105         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 106         .dt_free_map            = pinctrl_utils_dt_free_map,
 107 };
 108
 109 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
 110 {
 111         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 112
 113         return pctrl->soc->nfunctions;
 114 }
 115
 116 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
 117                                          unsigned function)
 118 {
 119         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 120
 121         return pctrl->soc->functions[function].name;
 122 }
 123
 124 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
 125                                    unsigned function,
 126                                    const char * const **groups,
 127                                    unsigned * const num_groups)
 128 {
 129         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 130
 131         *groups = pctrl->soc->functions[function].groups;
 132         *num_groups = pctrl->soc->functions[function].ngroups;
 133         return 0;
 134 }
 135
 136 static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
 137                              unsigned function,
 138                              unsigned group)
 139 {
 140         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 141         const struct msm_pingroup *g;
 142         unsigned long flags;
 143         u32 val;
 144         int i;
 145
 146         g = &pctrl->soc->groups[group];
 147
 148         if (WARN_ON(g->mux_bit < 0))
 149                 return -EINVAL;
 150
 151         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 152                 if (g->funcs[i] == function)
 153                         break;
 154         }
 155
 156         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 157                 return -EINVAL;
 158
 159         spin_lock_irqsave(&pctrl->lock, flags);
 160
 161         val = readl(pctrl->regs + g->ctl_reg);
 162         val &= ~(0x7 << g->mux_bit);
 163         val |= i << g->mux_bit;
 164         writel(val, pctrl->regs + g->ctl_reg);
 165
 166         spin_unlock_irqrestore(&pctrl->lock, flags);
 167
 168         return 0;
 169 }
 170
 171 static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
 172                                unsigned function,
 173                                unsigned group)
 174 {
 175         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 176         const struct msm_pingroup *g;
 177         unsigned long flags;
 178         u32 val;
 179
 180         g = &pctrl->soc->groups[group];
 181
 182         if (WARN_ON(g->mux_bit < 0))
 183                 return;
 184
 185         spin_lock_irqsave(&pctrl->lock, flags);
 186
 187         /* Clear the mux bits to select gpio mode */
 188         val = readl(pctrl->regs + g->ctl_reg);
 189         val &= ~(0x7 << g->mux_bit);
 190         writel(val, pctrl->regs + g->ctl_reg);
 191
 192         spin_unlock_irqrestore(&pctrl->lock, flags);
 193 }
 194
 195 static const struct pinmux_ops msm_pinmux_ops = {
 196         .get_functions_count    = msm_get_functions_count,
 197         .get_function_name      = msm_get_function_name,
 198         .get_function_groups    = msm_get_function_groups,
 199         .enable                 = msm_pinmux_enable,
 200         .disable                = msm_pinmux_disable,
 201 };
 202
 203 static int msm_config_reg(struct msm_pinctrl *pctrl,
 204                           const struct msm_pingroup *g,
 205                           unsigned param,
 206                           s16 *reg,
 207                           unsigned *mask,
 208                           unsigned *bit)
 209 {
 210         switch (param) {
 211         case PIN_CONFIG_BIAS_DISABLE:
 212                 *reg = g->ctl_reg;
 213                 *bit = g->pull_bit;
 214                 *mask = 3;
 215                 break;
 216         case PIN_CONFIG_BIAS_PULL_DOWN:
 217                 *reg = g->ctl_reg;
 218                 *bit = g->pull_bit;
 219                 *mask = 3;
 220                 break;
 221         case PIN_CONFIG_BIAS_PULL_UP:
 222                 *reg = g->ctl_reg;
 223                 *bit = g->pull_bit;
 224                 *mask = 3;
 225                 break;
 226         case PIN_CONFIG_DRIVE_STRENGTH:
 227                 *reg = g->ctl_reg;
 228                 *bit = g->drv_bit;
 229                 *mask = 7;
 230                 break;
 231         default:
 232                 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
 233                 return -ENOTSUPP;
 234         }
 235
 236         if (*reg < 0) {
 237                 dev_err(pctrl->dev, "Config param %04x not supported on group %s\n",
 238                         param, g->name);
 239                 return -ENOTSUPP;
 240         }
 241
 242         return 0;
 243 }
 244
 245 static int msm_config_get(struct pinctrl_dev *pctldev,
 246                           unsigned int pin,
 247                           unsigned long *config)
 248 {
 249         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 250         return -ENOTSUPP;
 251 }
 252
 253 static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 254                                 unsigned long *configs, unsigned num_configs)
 255 {
 256         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 257         return -ENOTSUPP;
 258 }
 259
 260 #define MSM_NO_PULL     0
 261 #define MSM_PULL_DOWN   1
 262 #define MSM_PULL_UP     3
 263
 264 static const unsigned msm_regval_to_drive[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
 265 static const unsigned msm_drive_to_regval[] = { -1, -1, 0, -1, 1, -1, 2, -1, 3, -1, 4, -1, 5, -1, 6, -1, 7 };
 266
 267 static int msm_config_group_get(struct pinctrl_dev *pctldev,
 268                                 unsigned int group,
 269                                 unsigned long *config)
 270 {
 271         const struct msm_pingroup *g;
 272         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 273         unsigned param = pinconf_to_config_param(*config);
 274         unsigned mask;
 275         unsigned arg;
 276         unsigned bit;
 277         s16 reg;
 278         int ret;
 279         u32 val;
 280
 281         g = &pctrl->soc->groups[group];
 282
 283         ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
 284         if (ret < 0)
 285                 return ret;
 286
 287         val = readl(pctrl->regs + reg);
 288         arg = (val >> bit) & mask;
 289
 290         /* Convert register value to pinconf value */
 291         switch (param) {
 292         case PIN_CONFIG_BIAS_DISABLE:
 293                 arg = arg == MSM_NO_PULL;
 294                 break;
 295         case PIN_CONFIG_BIAS_PULL_DOWN:
 296                 arg = arg == MSM_PULL_DOWN;
 297                 break;
 298         case PIN_CONFIG_BIAS_PULL_UP:
 299                 arg = arg == MSM_PULL_UP;
 300                 break;
 301         case PIN_CONFIG_DRIVE_STRENGTH:
 302                 arg = msm_regval_to_drive[arg];
 303                 break;
 304         default:
 305                 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 306                         param);
 307                 return -EINVAL;
 308         }
 309
 310         *config = pinconf_to_config_packed(param, arg);
 311
 312         return 0;
 313 }
 314
 315 static int msm_config_group_set(struct pinctrl_dev *pctldev,
 316                                 unsigned group,
 317                                 unsigned long *configs,
 318                                 unsigned num_configs)
 319 {
 320         const struct msm_pingroup *g;
 321         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 322         unsigned long flags;
 323         unsigned param;
 324         unsigned mask;
 325         unsigned arg;
 326         unsigned bit;
 327         s16 reg;
 328         int ret;
 329         u32 val;
 330         int i;
 331
 332         g = &pctrl->soc->groups[group];
 333
 334         for (i = 0; i < num_configs; i++) {
 335                 param = pinconf_to_config_param(configs[i]);
 336                 arg = pinconf_to_config_argument(configs[i]);
 337
 338                 ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
 339                 if (ret < 0)
 340                         return ret;
 341
 342                 /* Convert pinconf values to register values */
 343                 switch (param) {
 344                 case PIN_CONFIG_BIAS_DISABLE:
 345                         arg = MSM_NO_PULL;
 346                         break;
 347                 case PIN_CONFIG_BIAS_PULL_DOWN:
 348                         arg = MSM_PULL_DOWN;
 349                         break;
 350                 case PIN_CONFIG_BIAS_PULL_UP:
 351                         arg = MSM_PULL_UP;
 352                         break;
 353                 case PIN_CONFIG_DRIVE_STRENGTH:
 354                         /* Check for invalid values */
 355                         if (arg >= ARRAY_SIZE(msm_drive_to_regval))
 356                                 arg = -1;
 357                         else
 358                                 arg = msm_drive_to_regval[arg];
 359                         break;
 360                 default:
 361                         dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 362                                 param);
 363                         return -EINVAL;
 364                 }
 365
 366                 /* Range-check user-supplied value */
 367                 if (arg & ~mask) {
 368                         dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
 369                         return -EINVAL;
 370                 }
 371
 372                 spin_lock_irqsave(&pctrl->lock, flags);
 373                 val = readl(pctrl->regs + reg);
 374                 val &= ~(mask << bit);
 375                 val |= arg << bit;
 376                 writel(val, pctrl->regs + reg);
 377                 spin_unlock_irqrestore(&pctrl->lock, flags);
 378         }
 379
 380         return 0;
 381 }
 382
 383 static const struct pinconf_ops msm_pinconf_ops = {
 384         .pin_config_get         = msm_config_get,
 385         .pin_config_set         = msm_config_set,
 386         .pin_config_group_get   = msm_config_group_get,
 387         .pin_config_group_set   = msm_config_group_set,
 388 };
 389
 390 static struct pinctrl_desc msm_pinctrl_desc = {
 391         .pctlops = &msm_pinctrl_ops,
 392         .pmxops = &msm_pinmux_ops,
 393         .confops = &msm_pinconf_ops,
 394         .owner = THIS_MODULE,
 395 };
 396
 397 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 398 {
 399         const struct msm_pingroup *g;
 400         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 401         unsigned long flags;
 402         u32 val;
 403
 404         g = &pctrl->soc->groups[offset];
 405         if (WARN_ON(g->io_reg < 0))
 406                 return -EINVAL;
 407
 408         spin_lock_irqsave(&pctrl->lock, flags);
 409
 410         val = readl(pctrl->regs + g->ctl_reg);
 411         val &= ~BIT(g->oe_bit);
 412         writel(val, pctrl->regs + g->ctl_reg);
 413
 414         spin_unlock_irqrestore(&pctrl->lock, flags);
 415
 416         return 0;
 417 }
 418
 419 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 420 {
 421         const struct msm_pingroup *g;
 422         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 423         unsigned long flags;
 424         u32 val;
 425
 426         g = &pctrl->soc->groups[offset];
 427         if (WARN_ON(g->io_reg < 0))
 428                 return -EINVAL;
 429
 430         spin_lock_irqsave(&pctrl->lock, flags);
 431
 432         writel(value ? BIT(g->out_bit) : 0, pctrl->regs + g->io_reg);
 433
 434         val = readl(pctrl->regs + g->ctl_reg);
 435         val |= BIT(g->oe_bit);
 436         writel(val, pctrl->regs + g->ctl_reg);
 437
 438         spin_unlock_irqrestore(&pctrl->lock, flags);
 439
 440         return 0;
 441 }
 442
 443 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
 444 {
 445         const struct msm_pingroup *g;
 446         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 447         u32 val;
 448
 449         g = &pctrl->soc->groups[offset];
 450         if (WARN_ON(g->io_reg < 0))
 451                 return -EINVAL;
 452
 453         val = readl(pctrl->regs + g->io_reg);
 454         return !!(val & BIT(g->in_bit));
 455 }
 456
 457 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 458 {
 459         const struct msm_pingroup *g;
 460         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 461         unsigned long flags;
 462         u32 val;
 463
 464         g = &pctrl->soc->groups[offset];
 465         if (WARN_ON(g->io_reg < 0))
 466                 return;
 467
 468         spin_lock_irqsave(&pctrl->lock, flags);
 469
 470         val = readl(pctrl->regs + g->io_reg);
 471         val |= BIT(g->out_bit);
 472         writel(val, pctrl->regs + g->io_reg);
 473
 474         spin_unlock_irqrestore(&pctrl->lock, flags);
 475 }
 476
 477 static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 478 {
 479         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 480
 481         return irq_find_mapping(pctrl->domain, offset);
 482 }
 483
 484 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
 485 {
 486         int gpio = chip->base + offset;
 487         return pinctrl_request_gpio(gpio);
 488 }
 489
 490 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
 491 {
 492         int gpio = chip->base + offset;
 493         return pinctrl_free_gpio(gpio);
 494 }
 495
 496 #ifdef CONFIG_DEBUG_FS
 497 #include <linux/seq_file.h>
 498
 499 static void msm_gpio_dbg_show_one(struct seq_file *s,
 500                                   struct pinctrl_dev *pctldev,
 501                                   struct gpio_chip *chip,
 502                                   unsigned offset,
 503                                   unsigned gpio)
 504 {
 505         const struct msm_pingroup *g;
 506         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 507         unsigned func;
 508         int is_out;
 509         int drive;
 510         int pull;
 511         u32 ctl_reg;
 512
 513         static const char * const pulls[] = {
 514                 "no pull",
 515                 "pull down",
 516                 "keeper",
 517                 "pull up"
 518         };
 519
 520         g = &pctrl->soc->groups[offset];
 521         ctl_reg = readl(pctrl->regs + g->ctl_reg);
 522
 523         is_out = !!(ctl_reg & BIT(g->oe_bit));
 524         func = (ctl_reg >> g->mux_bit) & 7;
 525         drive = (ctl_reg >> g->drv_bit) & 7;
 526         pull = (ctl_reg >> g->pull_bit) & 3;
 527
 528         seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 529         seq_printf(s, " %dmA", msm_regval_to_drive[drive]);
 530         seq_printf(s, " %s", pulls[pull]);
 531 }
 532
 533 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 534 {
 535         unsigned gpio = chip->base;
 536         unsigned i;
 537
 538         for (i = 0; i < chip->ngpio; i++, gpio++) {
 539                 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 540                 seq_puts(s, "\n");
 541         }
 542 }
 543
 544 #else
 545 #define msm_gpio_dbg_show NULL
 546 #endif
 547
 548 static struct gpio_chip msm_gpio_template = {
 549         .direction_input  = msm_gpio_direction_input,
 550         .direction_output = msm_gpio_direction_output,
 551         .get              = msm_gpio_get,
 552         .set              = msm_gpio_set,
 553         .to_irq           = msm_gpio_to_irq,
 554         .request          = msm_gpio_request,
 555         .free             = msm_gpio_free,
 556         .dbg_show         = msm_gpio_dbg_show,
 557 };
 558
 559 /* For dual-edge interrupts in software, since some hardware has no
 560  * such support:
 561  *
 562  * At appropriate moments, this function may be called to flip the polarity
 563  * settings of both-edge irq lines to try and catch the next edge.
 564  *
 565  * The attempt is considered successful if:
 566  * - the status bit goes high, indicating that an edge was caught, or
 567  * - the input value of the gpio doesn't change during the attempt.
 568  * If the value changes twice during the process, that would cause the first
 569  * test to fail but would force the second, as two opposite
 570  * transitions would cause a detection no matter the polarity setting.
 571  *
 572  * The do-loop tries to sledge-hammer closed the timing hole between
 573  * the initial value-read and the polarity-write - if the line value changes
 574  * during that window, an interrupt is lost, the new polarity setting is
 575  * incorrect, and the first success test will fail, causing a retry.
 576  *
 577  * Algorithm comes from Google's msmgpio driver.
 578  */
 579 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
 580                                           const struct msm_pingroup *g,
 581                                           struct irq_data *d)
 582 {
 583         int loop_limit = 100;
 584         unsigned val, val2, intstat;
 585         unsigned pol;
 586
 587         do {
 588                 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 589
 590                 pol = readl(pctrl->regs + g->intr_cfg_reg);
 591                 pol ^= BIT(g->intr_polarity_bit);
 592                 writel(pol, pctrl->regs + g->intr_cfg_reg);
 593
 594                 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 595                 intstat = readl(pctrl->regs + g->intr_status_reg);
 596                 if (intstat || (val == val2))
 597                         return;
 598         } while (loop_limit-- > 0);
 599         dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
 600                 val, val2);
 601 }
 602
 603 static void msm_gpio_irq_mask(struct irq_data *d)
 604 {
 605         const struct msm_pingroup *g;
 606         struct msm_pinctrl *pctrl;
 607         unsigned long flags;
 608         u32 val;
 609
 610         pctrl = irq_data_get_irq_chip_data(d);
 611         g = &pctrl->soc->groups[d->hwirq];
 612         if (WARN_ON(g->intr_cfg_reg < 0))
 613                 return;
 614
 615         spin_lock_irqsave(&pctrl->lock, flags);
 616
 617         val = readl(pctrl->regs + g->intr_cfg_reg);
 618         val &= ~BIT(g->intr_enable_bit);
 619         writel(val, pctrl->regs + g->intr_cfg_reg);
 620
 621         clear_bit(d->hwirq, pctrl->enabled_irqs);
 622
 623         spin_unlock_irqrestore(&pctrl->lock, flags);
 624 }
 625
 626 static void msm_gpio_irq_unmask(struct irq_data *d)
 627 {
 628         const struct msm_pingroup *g;
 629         struct msm_pinctrl *pctrl;
 630         unsigned long flags;
 631         u32 val;
 632
 633         pctrl = irq_data_get_irq_chip_data(d);
 634         g = &pctrl->soc->groups[d->hwirq];
 635         if (WARN_ON(g->intr_status_reg < 0))
 636                 return;
 637
 638         spin_lock_irqsave(&pctrl->lock, flags);
 639
 640         val = readl(pctrl->regs + g->intr_status_reg);
 641         val &= ~BIT(g->intr_status_bit);
 642         writel(val, pctrl->regs + g->intr_status_reg);
 643
 644         val = readl(pctrl->regs + g->intr_cfg_reg);
 645         val |= BIT(g->intr_enable_bit);
 646         writel(val, pctrl->regs + g->intr_cfg_reg);
 647
 648         set_bit(d->hwirq, pctrl->enabled_irqs);
 649
 650         spin_unlock_irqrestore(&pctrl->lock, flags);
 651 }
 652
 653 static void msm_gpio_irq_ack(struct irq_data *d)
 654 {
 655         const struct msm_pingroup *g;
 656         struct msm_pinctrl *pctrl;
 657         unsigned long flags;
 658         u32 val;
 659
 660         pctrl = irq_data_get_irq_chip_data(d);
 661         g = &pctrl->soc->groups[d->hwirq];
 662         if (WARN_ON(g->intr_status_reg < 0))
 663                 return;
 664
 665         spin_lock_irqsave(&pctrl->lock, flags);
 666
 667         val = readl(pctrl->regs + g->intr_status_reg);
 668         val &= ~BIT(g->intr_status_bit);
 669         writel(val, pctrl->regs + g->intr_status_reg);
 670
 671         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 672                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 673
 674         spin_unlock_irqrestore(&pctrl->lock, flags);
 675 }
 676
 677 #define INTR_TARGET_PROC_APPS    4
 678
 679 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 680 {
 681         const struct msm_pingroup *g;
 682         struct msm_pinctrl *pctrl;
 683         unsigned long flags;
 684         u32 val;
 685
 686         pctrl = irq_data_get_irq_chip_data(d);
 687         g = &pctrl->soc->groups[d->hwirq];
 688         if (WARN_ON(g->intr_cfg_reg < 0))
 689                 return -EINVAL;
 690
 691         spin_lock_irqsave(&pctrl->lock, flags);
 692
 693         /*
 694          * For hw without possibility of detecting both edges
 695          */
 696         if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
 697                 set_bit(d->hwirq, pctrl->dual_edge_irqs);
 698         else
 699                 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 700
 701         /* Route interrupts to application cpu */
 702         val = readl(pctrl->regs + g->intr_target_reg);
 703         val &= ~(7 << g->intr_target_bit);
 704         val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
 705         writel(val, pctrl->regs + g->intr_target_reg);
 706
 707         /* Update configuration for gpio.
 708          * RAW_STATUS_EN is left on for all gpio irqs. Due to the
 709          * internal circuitry of TLMM, toggling the RAW_STATUS
 710          * could cause the INTR_STATUS to be set for EDGE interrupts.
 711          */
 712         val = readl(pctrl->regs + g->intr_cfg_reg);
 713         val |= BIT(g->intr_raw_status_bit);
 714         if (g->intr_detection_width == 2) {
 715                 val &= ~(3 << g->intr_detection_bit);
 716                 val &= ~(1 << g->intr_polarity_bit);
 717                 switch (type) {
 718                 case IRQ_TYPE_EDGE_RISING:
 719                         val |= 1 << g->intr_detection_bit;
 720                         val |= BIT(g->intr_polarity_bit);
 721                         break;
 722                 case IRQ_TYPE_EDGE_FALLING:
 723                         val |= 2 << g->intr_detection_bit;
 724                         val |= BIT(g->intr_polarity_bit);
 725                         break;
 726                 case IRQ_TYPE_EDGE_BOTH:
 727                         val |= 3 << g->intr_detection_bit;
 728                         val |= BIT(g->intr_polarity_bit);
 729                         break;
 730                 case IRQ_TYPE_LEVEL_LOW:
 731                         break;
 732                 case IRQ_TYPE_LEVEL_HIGH:
 733                         val |= BIT(g->intr_polarity_bit);
 734                         break;
 735                 }
 736         } else if (g->intr_detection_width == 1) {
 737                 val &= ~(1 << g->intr_detection_bit);
 738                 val &= ~(1 << g->intr_polarity_bit);
 739                 switch (type) {
 740                 case IRQ_TYPE_EDGE_RISING:
 741                         val |= BIT(g->intr_detection_bit);
 742                         val |= BIT(g->intr_polarity_bit);
 743                         break;
 744                 case IRQ_TYPE_EDGE_FALLING:
 745                         val |= BIT(g->intr_detection_bit);
 746                         break;
 747                 case IRQ_TYPE_EDGE_BOTH:
 748                         val |= BIT(g->intr_detection_bit);
 749                         break;
 750                 case IRQ_TYPE_LEVEL_LOW:
 751                         break;
 752                 case IRQ_TYPE_LEVEL_HIGH:
 753                         val |= BIT(g->intr_polarity_bit);
 754                         break;
 755                 }
 756         } else {
 757                 BUG();
 758         }
 759         writel(val, pctrl->regs + g->intr_cfg_reg);
 760
 761         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 762                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 763
 764         spin_unlock_irqrestore(&pctrl->lock, flags);
 765
 766         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 767                 __irq_set_handler_locked(d->irq, handle_level_irq);
 768         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 769                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 770
 771         return 0;
 772 }
 773
 774 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 775 {
 776         struct msm_pinctrl *pctrl;
 777         unsigned long flags;
 778         unsigned ngpio;
 779
 780         pctrl = irq_data_get_irq_chip_data(d);
 781         ngpio = pctrl->chip.ngpio;
 782
 783         spin_lock_irqsave(&pctrl->lock, flags);
 784
 785         if (on) {
 786                 if (bitmap_empty(pctrl->wake_irqs, ngpio))
 787                         enable_irq_wake(pctrl->irq);
 788                 set_bit(d->hwirq, pctrl->wake_irqs);
 789         } else {
 790                 clear_bit(d->hwirq, pctrl->wake_irqs);
 791                 if (bitmap_empty(pctrl->wake_irqs, ngpio))
 792                         disable_irq_wake(pctrl->irq);
 793         }
 794
 795         spin_unlock_irqrestore(&pctrl->lock, flags);
 796
 797         return 0;
 798 }
 799
 800 static unsigned int msm_gpio_irq_startup(struct irq_data *d)
 801 {
 802         struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
 803
 804         if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) {
 805                 dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n",
 806                         d->hwirq);
 807         }
 808         msm_gpio_irq_unmask(d);
 809         return 0;
 810 }
 811
 812 static void msm_gpio_irq_shutdown(struct irq_data *d)
 813 {
 814         struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
 815
 816         msm_gpio_irq_mask(d);
 817         gpio_unlock_as_irq(&pctrl->chip, d->hwirq);
 818 }
 819
 820 static struct irq_chip msm_gpio_irq_chip = {
 821         .name           = "msmgpio",
 822         .irq_mask       = msm_gpio_irq_mask,
 823         .irq_unmask     = msm_gpio_irq_unmask,
 824         .irq_ack        = msm_gpio_irq_ack,
 825         .irq_set_type   = msm_gpio_irq_set_type,
 826         .irq_set_wake   = msm_gpio_irq_set_wake,
 827         .irq_startup    = msm_gpio_irq_startup,
 828         .irq_shutdown   = msm_gpio_irq_shutdown,
 829 };
 830
 831 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 832 {
 833         const struct msm_pingroup *g;
 834         struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc);
 835         struct irq_chip *chip = irq_get_chip(irq);
 836         int irq_pin;
 837         int handled = 0;
 838         u32 val;
 839         int i;
 840
 841         chained_irq_enter(chip, desc);
 842
 843         /*
 844          * Each pin has it's own IRQ status register, so use
 845          * enabled_irq bitmap to limit the number of reads.
 846          */
 847         for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
 848                 g = &pctrl->soc->groups[i];
 849                 val = readl(pctrl->regs + g->intr_status_reg);
 850                 if (val & BIT(g->intr_status_bit)) {
 851                         irq_pin = irq_find_mapping(pctrl->domain, i);
 852                         generic_handle_irq(irq_pin);
 853                         handled++;
 854                 }
 855         }
 856
 857         /* No interrupts were flagged */
 858         if (handled == 0)
 859                 handle_bad_irq(irq, desc);
 860
 861         chained_irq_exit(chip, desc);
 862 }
 863
 864 static int msm_gpio_init(struct msm_pinctrl *pctrl)
 865 {
 866         struct gpio_chip *chip;
 867         int irq;
 868         int ret;
 869         int i;
 870         int r;
 871
 872         chip = &pctrl->chip;
 873         chip->base = 0;
 874         chip->ngpio = pctrl->soc->ngpios;
 875         chip->label = dev_name(pctrl->dev);
 876         chip->dev = pctrl->dev;
 877         chip->owner = THIS_MODULE;
 878         chip->of_node = pctrl->dev->of_node;
 879
 880         ret = gpiochip_add(&pctrl->chip);
 881         if (ret) {
 882                 dev_err(pctrl->dev, "Failed register gpiochip\n");
 883                 return ret;
 884         }
 885
 886         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
 887         if (ret) {
 888                 dev_err(pctrl->dev, "Failed to add pin range\n");
 889                 return ret;
 890         }
 891
 892         pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio,
 893                                               &irq_domain_simple_ops, NULL);
 894         if (!pctrl->domain) {
 895                 dev_err(pctrl->dev, "Failed to register irq domain\n");
 896                 r = gpiochip_remove(&pctrl->chip);
 897                 return -ENOSYS;
 898         }
 899
 900         for (i = 0; i < chip->ngpio; i++) {
 901                 irq = irq_create_mapping(pctrl->domain, i);
 902                 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq);
 903                 irq_set_chip_data(irq, pctrl);
 904         }
 905
 906         irq_set_handler_data(pctrl->irq, pctrl);
 907         irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler);
 908
 909         return 0;
 910 }
 911
 912 int msm_pinctrl_probe(struct platform_device *pdev,
 913                       const struct msm_pinctrl_soc_data *soc_data)
 914 {
 915         struct msm_pinctrl *pctrl;
 916         struct resource *res;
 917         int ret;
 918
 919         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 920         if (!pctrl) {
 921                 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
 922                 return -ENOMEM;
 923         }
 924         pctrl->dev = &pdev->dev;
 925         pctrl->soc = soc_data;
 926         pctrl->chip = msm_gpio_template;
 927
 928         spin_lock_init(&pctrl->lock);
 929
 930         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 931         pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
 932         if (IS_ERR(pctrl->regs))
 933                 return PTR_ERR(pctrl->regs);
 934
 935         pctrl->irq = platform_get_irq(pdev, 0);
 936         if (pctrl->irq < 0) {
 937                 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
 938                 return pctrl->irq;
 939         }
 940
 941         msm_pinctrl_desc.name = dev_name(&pdev->dev);
 942         msm_pinctrl_desc.pins = pctrl->soc->pins;
 943         msm_pinctrl_desc.npins = pctrl->soc->npins;
 944         pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
 945         if (!pctrl->pctrl) {
 946                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 947                 return -ENODEV;
 948         }
 949
 950         ret = msm_gpio_init(pctrl);
 951         if (ret) {
 952                 pinctrl_unregister(pctrl->pctrl);
 953                 return ret;
 954         }
 955
 956         platform_set_drvdata(pdev, pctrl);
 957
 958         dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
 959
 960         return 0;
 961 }
 962 EXPORT_SYMBOL(msm_pinctrl_probe);
 963
 964 int msm_pinctrl_remove(struct platform_device *pdev)
 965 {
 966         struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
 967         int ret;
 968
 969         ret = gpiochip_remove(&pctrl->chip);
 970         if (ret) {
 971                 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
 972                 return ret;
 973         }
 974
 975         irq_set_chained_handler(pctrl->irq, NULL);
 976         irq_domain_remove(pctrl->domain);
 977         pinctrl_unregister(pctrl->pctrl);
 978
 979         return 0;
 980 }
 981 EXPORT_SYMBOL(msm_pinctrl_remove);
 982