drivers/pinctrl/pinctrl-msm.c

   1 /*
   2  * Copyright (c) 2013, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/pinctrl/pinctrl.h>
  23 #include <linux/pinctrl/pinmux.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26 #include <linux/slab.h>
  27 #include <linux/gpio.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/irq.h>
  30 #include <linux/irqchip/chained_irq.h>
  31 #include <linux/spinlock.h>
  32
  33 #include "core.h"
  34 #include "pinconf.h"
  35 #include "pinctrl-msm.h"
  36 #include "pinctrl-utils.h"
  37
  38 #define MAX_NR_GPIO 300
  39
  40 /**
  41  * struct msm_pinctrl - state for a pinctrl-msm device
  42  * @dev:            device handle.
  43  * @pctrl:          pinctrl handle.
  44  * @domain:         irqdomain handle.
  45  * @chip:           gpiochip handle.
  46  * @irq:            parent irq for the TLMM irq_chip.
  47  * @lock:           Spinlock to protect register resources as well
  48  *                  as msm_pinctrl data structures.
  49  * @enabled_irqs:   Bitmap of currently enabled irqs.
  50  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
  51  *                  detection.
  52  * @soc;            Reference to soc_data of platform specific data.
  53  * @regs:           Base address for the TLMM register map.
  54  */
  55 struct msm_pinctrl {
  56         struct device *dev;
  57         struct pinctrl_dev *pctrl;
  58         struct irq_domain *domain;
  59         struct gpio_chip chip;
  60         int irq;
  61
  62         spinlock_t lock;
  63
  64         DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
  65         DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
  66
  67         const struct msm_pinctrl_soc_data *soc;
  68         void __iomem *regs;
  69 };
  70
  71 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
  72 {
  73         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  74
  75         return pctrl->soc->ngroups;
  76 }
  77
  78 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
  79                                       unsigned group)
  80 {
  81         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  82
  83         return pctrl->soc->groups[group].name;
  84 }
  85
  86 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
  87                               unsigned group,
  88                               const unsigned **pins,
  89                               unsigned *num_pins)
  90 {
  91         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  92
  93         *pins = pctrl->soc->groups[group].pins;
  94         *num_pins = pctrl->soc->groups[group].npins;
  95         return 0;
  96 }
  97
  98 static const struct pinctrl_ops msm_pinctrl_ops = {
  99         .get_groups_count       = msm_get_groups_count,
 100         .get_group_name         = msm_get_group_name,
 101         .get_group_pins         = msm_get_group_pins,
 102         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 103         .dt_free_map            = pinctrl_utils_dt_free_map,
 104 };
 105
 106 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
 107 {
 108         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 109
 110         return pctrl->soc->nfunctions;
 111 }
 112
 113 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
 114                                          unsigned function)
 115 {
 116         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 117
 118         return pctrl->soc->functions[function].name;
 119 }
 120
 121 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
 122                                    unsigned function,
 123                                    const char * const **groups,
 124                                    unsigned * const num_groups)
 125 {
 126         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 127
 128         *groups = pctrl->soc->functions[function].groups;
 129         *num_groups = pctrl->soc->functions[function].ngroups;
 130         return 0;
 131 }
 132
 133 static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
 134                              unsigned function,
 135                              unsigned group)
 136 {
 137         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 138         const struct msm_pingroup *g;
 139         unsigned long flags;
 140         u32 val;
 141         int i;
 142
 143         g = &pctrl->soc->groups[group];
 144
 145         if (WARN_ON(g->mux_bit < 0))
 146                 return -EINVAL;
 147
 148         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 149                 if (g->funcs[i] == function)
 150                         break;
 151         }
 152
 153         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 154                 return -EINVAL;
 155
 156         spin_lock_irqsave(&pctrl->lock, flags);
 157
 158         val = readl(pctrl->regs + g->ctl_reg);
 159         val &= ~(0x7 << g->mux_bit);
 160         val |= i << g->mux_bit;
 161         writel(val, pctrl->regs + g->ctl_reg);
 162
 163         spin_unlock_irqrestore(&pctrl->lock, flags);
 164
 165         return 0;
 166 }
 167
 168 static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
 169                                unsigned function,
 170                                unsigned group)
 171 {
 172         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 173         const struct msm_pingroup *g;
 174         unsigned long flags;
 175         u32 val;
 176
 177         g = &pctrl->soc->groups[group];
 178
 179         if (WARN_ON(g->mux_bit < 0))
 180                 return;
 181
 182         spin_lock_irqsave(&pctrl->lock, flags);
 183
 184         /* Clear the mux bits to select gpio mode */
 185         val = readl(pctrl->regs + g->ctl_reg);
 186         val &= ~(0x7 << g->mux_bit);
 187         writel(val, pctrl->regs + g->ctl_reg);
 188
 189         spin_unlock_irqrestore(&pctrl->lock, flags);
 190 }
 191
 192 static const struct pinmux_ops msm_pinmux_ops = {
 193         .get_functions_count    = msm_get_functions_count,
 194         .get_function_name      = msm_get_function_name,
 195         .get_function_groups    = msm_get_function_groups,
 196         .enable                 = msm_pinmux_enable,
 197         .disable                = msm_pinmux_disable,
 198 };
 199
 200 static int msm_config_reg(struct msm_pinctrl *pctrl,
 201                           const struct msm_pingroup *g,
 202                           unsigned param,
 203                           unsigned *mask,
 204                           unsigned *bit)
 205 {
 206         switch (param) {
 207         case PIN_CONFIG_BIAS_DISABLE:
 208         case PIN_CONFIG_BIAS_PULL_DOWN:
 209         case PIN_CONFIG_BIAS_PULL_UP:
 210                 *bit = g->pull_bit;
 211                 *mask = 3;
 212                 break;
 213         case PIN_CONFIG_DRIVE_STRENGTH:
 214                 *bit = g->drv_bit;
 215                 *mask = 7;
 216                 break;
 217         case PIN_CONFIG_OUTPUT:
 218                 *reg = g->ctl_reg;
 219                 *bit = g->oe_bit;
 220                 *mask = 1;
 221                 break;
 222         default:
 223                 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
 224                 return -ENOTSUPP;
 225         }
 226
 227         return 0;
 228 }
 229
 230 static int msm_config_get(struct pinctrl_dev *pctldev,
 231                           unsigned int pin,
 232                           unsigned long *config)
 233 {
 234         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 235         return -ENOTSUPP;
 236 }
 237
 238 static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 239                                 unsigned long *configs, unsigned num_configs)
 240 {
 241         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 242         return -ENOTSUPP;
 243 }
 244
 245 #define MSM_NO_PULL     0
 246 #define MSM_PULL_DOWN   1
 247 #define MSM_PULL_UP     3
 248
 249 static unsigned msm_regval_to_drive(u32 val)
 250 {
 251         return (val + 1) * 2;
 252 }
 253
 254 static int msm_config_group_get(struct pinctrl_dev *pctldev,
 255                                 unsigned int group,
 256                                 unsigned long *config)
 257 {
 258         const struct msm_pingroup *g;
 259         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 260         unsigned param = pinconf_to_config_param(*config);
 261         unsigned mask;
 262         unsigned arg;
 263         unsigned bit;
 264         int ret;
 265         u32 val;
 266
 267         g = &pctrl->soc->groups[group];
 268
 269         ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 270         if (ret < 0)
 271                 return ret;
 272
 273         val = readl(pctrl->regs + g->ctl_reg);
 274         arg = (val >> bit) & mask;
 275
 276         /* Convert register value to pinconf value */
 277         switch (param) {
 278         case PIN_CONFIG_BIAS_DISABLE:
 279                 arg = arg == MSM_NO_PULL;
 280                 break;
 281         case PIN_CONFIG_BIAS_PULL_DOWN:
 282                 arg = arg == MSM_PULL_DOWN;
 283                 break;
 284         case PIN_CONFIG_BIAS_PULL_UP:
 285                 arg = arg == MSM_PULL_UP;
 286                 break;
 287         case PIN_CONFIG_DRIVE_STRENGTH:
 288                 arg = msm_regval_to_drive(arg);
 289                 break;
 290         case PIN_CONFIG_OUTPUT:
 291                 /* Pin is not output */
 292                 if (!arg)
 293                         return -EINVAL;
 294
 295                 val = readl(pctrl->regs + g->io_reg);
 296                 arg = !!(val & BIT(g->in_bit));
 297                 break;
 298         default:
 299                 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 300                         param);
 301                 return -EINVAL;
 302         }
 303
 304         *config = pinconf_to_config_packed(param, arg);
 305
 306         return 0;
 307 }
 308
 309 static int msm_config_group_set(struct pinctrl_dev *pctldev,
 310                                 unsigned group,
 311                                 unsigned long *configs,
 312                                 unsigned num_configs)
 313 {
 314         const struct msm_pingroup *g;
 315         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 316         unsigned long flags;
 317         unsigned param;
 318         unsigned mask;
 319         unsigned arg;
 320         unsigned bit;
 321         int ret;
 322         u32 val;
 323         int i;
 324
 325         g = &pctrl->soc->groups[group];
 326
 327         for (i = 0; i < num_configs; i++) {
 328                 param = pinconf_to_config_param(configs[i]);
 329                 arg = pinconf_to_config_argument(configs[i]);
 330
 331                 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 332                 if (ret < 0)
 333                         return ret;
 334
 335                 /* Convert pinconf values to register values */
 336                 switch (param) {
 337                 case PIN_CONFIG_BIAS_DISABLE:
 338                         arg = MSM_NO_PULL;
 339                         break;
 340                 case PIN_CONFIG_BIAS_PULL_DOWN:
 341                         arg = MSM_PULL_DOWN;
 342                         break;
 343                 case PIN_CONFIG_BIAS_PULL_UP:
 344                         arg = MSM_PULL_UP;
 345                         break;
 346                 case PIN_CONFIG_DRIVE_STRENGTH:
 347                         /* Check for invalid values */
 348                         if (arg > 16 || arg < 2 || (arg % 2) != 0)
 349                                 arg = -1;
 350                         else
 351                                 arg = (arg / 2) - 1;
 352                         break;
 353                 case PIN_CONFIG_OUTPUT:
 354                         /* set output value */
 355                         spin_lock_irqsave(&pctrl->lock, flags);
 356                         val = readl(pctrl->regs + g->io_reg);
 357                         if (arg)
 358                                 val |= BIT(g->out_bit);
 359                         else
 360                                 val &= ~BIT(g->out_bit);
 361                         writel(val, pctrl->regs + g->io_reg);
 362                         spin_unlock_irqrestore(&pctrl->lock, flags);
 363
 364                         /* enable output */
 365                         arg = 1;
 366                         break;
 367                 default:
 368                         dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 369                                 param);
 370                         return -EINVAL;
 371                 }
 372
 373                 /* Range-check user-supplied value */
 374                 if (arg & ~mask) {
 375                         dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
 376                         return -EINVAL;
 377                 }
 378
 379                 spin_lock_irqsave(&pctrl->lock, flags);
 380                 val = readl(pctrl->regs + g->ctl_reg);
 381                 val &= ~(mask << bit);
 382                 val |= arg << bit;
 383                 writel(val, pctrl->regs + g->ctl_reg);
 384                 spin_unlock_irqrestore(&pctrl->lock, flags);
 385         }
 386
 387         return 0;
 388 }
 389
 390 static const struct pinconf_ops msm_pinconf_ops = {
 391         .pin_config_get         = msm_config_get,
 392         .pin_config_set         = msm_config_set,
 393         .pin_config_group_get   = msm_config_group_get,
 394         .pin_config_group_set   = msm_config_group_set,
 395 };
 396
 397 static struct pinctrl_desc msm_pinctrl_desc = {
 398         .pctlops = &msm_pinctrl_ops,
 399         .pmxops = &msm_pinmux_ops,
 400         .confops = &msm_pinconf_ops,
 401         .owner = THIS_MODULE,
 402 };
 403
 404 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 405 {
 406         const struct msm_pingroup *g;
 407         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 408         unsigned long flags;
 409         u32 val;
 410
 411         g = &pctrl->soc->groups[offset];
 412
 413         spin_lock_irqsave(&pctrl->lock, flags);
 414
 415         val = readl(pctrl->regs + g->ctl_reg);
 416         val &= ~BIT(g->oe_bit);
 417         writel(val, pctrl->regs + g->ctl_reg);
 418
 419         spin_unlock_irqrestore(&pctrl->lock, flags);
 420
 421         return 0;
 422 }
 423
 424 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 425 {
 426         const struct msm_pingroup *g;
 427         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 428         unsigned long flags;
 429         u32 val;
 430
 431         g = &pctrl->soc->groups[offset];
 432
 433         spin_lock_irqsave(&pctrl->lock, flags);
 434
 435         val = readl(pctrl->regs + g->io_reg);
 436         if (value)
 437                 val |= BIT(g->out_bit);
 438         else
 439                 val &= ~BIT(g->out_bit);
 440         writel(val, pctrl->regs + g->io_reg);
 441
 442         val = readl(pctrl->regs + g->ctl_reg);
 443         val |= BIT(g->oe_bit);
 444         writel(val, pctrl->regs + g->ctl_reg);
 445
 446         spin_unlock_irqrestore(&pctrl->lock, flags);
 447
 448         return 0;
 449 }
 450
 451 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
 452 {
 453         const struct msm_pingroup *g;
 454         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 455         u32 val;
 456
 457         g = &pctrl->soc->groups[offset];
 458
 459         val = readl(pctrl->regs + g->io_reg);
 460         return !!(val & BIT(g->in_bit));
 461 }
 462
 463 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 464 {
 465         const struct msm_pingroup *g;
 466         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 467         unsigned long flags;
 468         u32 val;
 469
 470         g = &pctrl->soc->groups[offset];
 471
 472         spin_lock_irqsave(&pctrl->lock, flags);
 473
 474         val = readl(pctrl->regs + g->io_reg);
 475         if (value)
 476                 val |= BIT(g->out_bit);
 477         else
 478                 val &= ~BIT(g->out_bit);
 479         writel(val, pctrl->regs + g->io_reg);
 480
 481         spin_unlock_irqrestore(&pctrl->lock, flags);
 482 }
 483
 484 static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 485 {
 486         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 487
 488         return irq_find_mapping(pctrl->domain, offset);
 489 }
 490
 491 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
 492 {
 493         int gpio = chip->base + offset;
 494         return pinctrl_request_gpio(gpio);
 495 }
 496
 497 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
 498 {
 499         int gpio = chip->base + offset;
 500         return pinctrl_free_gpio(gpio);
 501 }
 502
 503 #ifdef CONFIG_DEBUG_FS
 504 #include <linux/seq_file.h>
 505
 506 static void msm_gpio_dbg_show_one(struct seq_file *s,
 507                                   struct pinctrl_dev *pctldev,
 508                                   struct gpio_chip *chip,
 509                                   unsigned offset,
 510                                   unsigned gpio)
 511 {
 512         const struct msm_pingroup *g;
 513         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 514         unsigned func;
 515         int is_out;
 516         int drive;
 517         int pull;
 518         u32 ctl_reg;
 519
 520         static const char * const pulls[] = {
 521                 "no pull",
 522                 "pull down",
 523                 "keeper",
 524                 "pull up"
 525         };
 526
 527         g = &pctrl->soc->groups[offset];
 528         ctl_reg = readl(pctrl->regs + g->ctl_reg);
 529
 530         is_out = !!(ctl_reg & BIT(g->oe_bit));
 531         func = (ctl_reg >> g->mux_bit) & 7;
 532         drive = (ctl_reg >> g->drv_bit) & 7;
 533         pull = (ctl_reg >> g->pull_bit) & 3;
 534
 535         seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 536         seq_printf(s, " %dmA", msm_regval_to_drive(drive));
 537         seq_printf(s, " %s", pulls[pull]);
 538 }
 539
 540 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 541 {
 542         unsigned gpio = chip->base;
 543         unsigned i;
 544
 545         for (i = 0; i < chip->ngpio; i++, gpio++) {
 546                 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 547                 seq_puts(s, "\n");
 548         }
 549 }
 550
 551 #else
 552 #define msm_gpio_dbg_show NULL
 553 #endif
 554
 555 static struct gpio_chip msm_gpio_template = {
 556         .direction_input  = msm_gpio_direction_input,
 557         .direction_output = msm_gpio_direction_output,
 558         .get              = msm_gpio_get,
 559         .set              = msm_gpio_set,
 560         .to_irq           = msm_gpio_to_irq,
 561         .request          = msm_gpio_request,
 562         .free             = msm_gpio_free,
 563         .dbg_show         = msm_gpio_dbg_show,
 564 };
 565
 566 /* For dual-edge interrupts in software, since some hardware has no
 567  * such support:
 568  *
 569  * At appropriate moments, this function may be called to flip the polarity
 570  * settings of both-edge irq lines to try and catch the next edge.
 571  *
 572  * The attempt is considered successful if:
 573  * - the status bit goes high, indicating that an edge was caught, or
 574  * - the input value of the gpio doesn't change during the attempt.
 575  * If the value changes twice during the process, that would cause the first
 576  * test to fail but would force the second, as two opposite
 577  * transitions would cause a detection no matter the polarity setting.
 578  *
 579  * The do-loop tries to sledge-hammer closed the timing hole between
 580  * the initial value-read and the polarity-write - if the line value changes
 581  * during that window, an interrupt is lost, the new polarity setting is
 582  * incorrect, and the first success test will fail, causing a retry.
 583  *
 584  * Algorithm comes from Google's msmgpio driver.
 585  */
 586 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
 587                                           const struct msm_pingroup *g,
 588                                           struct irq_data *d)
 589 {
 590         int loop_limit = 100;
 591         unsigned val, val2, intstat;
 592         unsigned pol;
 593
 594         do {
 595                 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 596
 597                 pol = readl(pctrl->regs + g->intr_cfg_reg);
 598                 pol ^= BIT(g->intr_polarity_bit);
 599                 writel(pol, pctrl->regs + g->intr_cfg_reg);
 600
 601                 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 602                 intstat = readl(pctrl->regs + g->intr_status_reg);
 603                 if (intstat || (val == val2))
 604                         return;
 605         } while (loop_limit-- > 0);
 606         dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
 607                 val, val2);
 608 }
 609
 610 static void msm_gpio_irq_mask(struct irq_data *d)
 611 {
 612         const struct msm_pingroup *g;
 613         struct msm_pinctrl *pctrl;
 614         unsigned long flags;
 615         u32 val;
 616
 617         pctrl = irq_data_get_irq_chip_data(d);
 618         g = &pctrl->soc->groups[d->hwirq];
 619
 620         spin_lock_irqsave(&pctrl->lock, flags);
 621
 622         val = readl(pctrl->regs + g->intr_cfg_reg);
 623         val &= ~BIT(g->intr_enable_bit);
 624         writel(val, pctrl->regs + g->intr_cfg_reg);
 625
 626         clear_bit(d->hwirq, pctrl->enabled_irqs);
 627
 628         spin_unlock_irqrestore(&pctrl->lock, flags);
 629 }
 630
 631 static void msm_gpio_irq_unmask(struct irq_data *d)
 632 {
 633         const struct msm_pingroup *g;
 634         struct msm_pinctrl *pctrl;
 635         unsigned long flags;
 636         u32 val;
 637
 638         pctrl = irq_data_get_irq_chip_data(d);
 639         g = &pctrl->soc->groups[d->hwirq];
 640
 641         spin_lock_irqsave(&pctrl->lock, flags);
 642
 643         val = readl(pctrl->regs + g->intr_status_reg);
 644         val &= ~BIT(g->intr_status_bit);
 645         writel(val, pctrl->regs + g->intr_status_reg);
 646
 647         val = readl(pctrl->regs + g->intr_cfg_reg);
 648         val |= BIT(g->intr_enable_bit);
 649         writel(val, pctrl->regs + g->intr_cfg_reg);
 650
 651         set_bit(d->hwirq, pctrl->enabled_irqs);
 652
 653         spin_unlock_irqrestore(&pctrl->lock, flags);
 654 }
 655
 656 static void msm_gpio_irq_ack(struct irq_data *d)
 657 {
 658         const struct msm_pingroup *g;
 659         struct msm_pinctrl *pctrl;
 660         unsigned long flags;
 661         u32 val;
 662
 663         pctrl = irq_data_get_irq_chip_data(d);
 664         g = &pctrl->soc->groups[d->hwirq];
 665
 666         spin_lock_irqsave(&pctrl->lock, flags);
 667
 668         val = readl(pctrl->regs + g->intr_status_reg);
 669         val &= ~BIT(g->intr_status_bit);
 670         writel(val, pctrl->regs + g->intr_status_reg);
 671
 672         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 673                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 674
 675         spin_unlock_irqrestore(&pctrl->lock, flags);
 676 }
 677
 678 #define INTR_TARGET_PROC_APPS    4
 679
 680 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 681 {
 682         const struct msm_pingroup *g;
 683         struct msm_pinctrl *pctrl;
 684         unsigned long flags;
 685         u32 val;
 686
 687         pctrl = irq_data_get_irq_chip_data(d);
 688         g = &pctrl->soc->groups[d->hwirq];
 689
 690         spin_lock_irqsave(&pctrl->lock, flags);
 691
 692         /*
 693          * For hw without possibility of detecting both edges
 694          */
 695         if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
 696                 set_bit(d->hwirq, pctrl->dual_edge_irqs);
 697         else
 698                 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 699
 700         /* Route interrupts to application cpu */
 701         val = readl(pctrl->regs + g->intr_target_reg);
 702         val &= ~(7 << g->intr_target_bit);
 703         val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
 704         writel(val, pctrl->regs + g->intr_target_reg);
 705
 706         /* Update configuration for gpio.
 707          * RAW_STATUS_EN is left on for all gpio irqs. Due to the
 708          * internal circuitry of TLMM, toggling the RAW_STATUS
 709          * could cause the INTR_STATUS to be set for EDGE interrupts.
 710          */
 711         val = readl(pctrl->regs + g->intr_cfg_reg);
 712         val |= BIT(g->intr_raw_status_bit);
 713         if (g->intr_detection_width == 2) {
 714                 val &= ~(3 << g->intr_detection_bit);
 715                 val &= ~(1 << g->intr_polarity_bit);
 716                 switch (type) {
 717                 case IRQ_TYPE_EDGE_RISING:
 718                         val |= 1 << g->intr_detection_bit;
 719                         val |= BIT(g->intr_polarity_bit);
 720                         break;
 721                 case IRQ_TYPE_EDGE_FALLING:
 722                         val |= 2 << g->intr_detection_bit;
 723                         val |= BIT(g->intr_polarity_bit);
 724                         break;
 725                 case IRQ_TYPE_EDGE_BOTH:
 726                         val |= 3 << g->intr_detection_bit;
 727                         val |= BIT(g->intr_polarity_bit);
 728                         break;
 729                 case IRQ_TYPE_LEVEL_LOW:
 730                         break;
 731                 case IRQ_TYPE_LEVEL_HIGH:
 732                         val |= BIT(g->intr_polarity_bit);
 733                         break;
 734                 }
 735         } else if (g->intr_detection_width == 1) {
 736                 val &= ~(1 << g->intr_detection_bit);
 737                 val &= ~(1 << g->intr_polarity_bit);
 738                 switch (type) {
 739                 case IRQ_TYPE_EDGE_RISING:
 740                         val |= BIT(g->intr_detection_bit);
 741                         val |= BIT(g->intr_polarity_bit);
 742                         break;
 743                 case IRQ_TYPE_EDGE_FALLING:
 744                         val |= BIT(g->intr_detection_bit);
 745                         break;
 746                 case IRQ_TYPE_EDGE_BOTH:
 747                         val |= BIT(g->intr_detection_bit);
 748                         break;
 749                 case IRQ_TYPE_LEVEL_LOW:
 750                         break;
 751                 case IRQ_TYPE_LEVEL_HIGH:
 752                         val |= BIT(g->intr_polarity_bit);
 753                         break;
 754                 }
 755         } else {
 756                 BUG();
 757         }
 758         writel(val, pctrl->regs + g->intr_cfg_reg);
 759
 760         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 761                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 762
 763         spin_unlock_irqrestore(&pctrl->lock, flags);
 764
 765         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 766                 __irq_set_handler_locked(d->irq, handle_level_irq);
 767         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 768                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 769
 770         return 0;
 771 }
 772
 773 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 774 {
 775         struct msm_pinctrl *pctrl;
 776         unsigned long flags;
 777
 778         pctrl = irq_data_get_irq_chip_data(d);
 779
 780         spin_lock_irqsave(&pctrl->lock, flags);
 781
 782         irq_set_irq_wake(pctrl->irq, on);
 783
 784         spin_unlock_irqrestore(&pctrl->lock, flags);
 785
 786         return 0;
 787 }
 788
 789 static unsigned int msm_gpio_irq_startup(struct irq_data *d)
 790 {
 791         struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
 792
 793         if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) {
 794                 dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n",
 795                         d->hwirq);
 796         }
 797         msm_gpio_irq_unmask(d);
 798         return 0;
 799 }
 800
 801 static void msm_gpio_irq_shutdown(struct irq_data *d)
 802 {
 803         struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
 804
 805         msm_gpio_irq_mask(d);
 806         gpio_unlock_as_irq(&pctrl->chip, d->hwirq);
 807 }
 808
 809 static struct irq_chip msm_gpio_irq_chip = {
 810         .name           = "msmgpio",
 811         .irq_mask       = msm_gpio_irq_mask,
 812         .irq_unmask     = msm_gpio_irq_unmask,
 813         .irq_ack        = msm_gpio_irq_ack,
 814         .irq_set_type   = msm_gpio_irq_set_type,
 815         .irq_set_wake   = msm_gpio_irq_set_wake,
 816         .irq_startup    = msm_gpio_irq_startup,
 817         .irq_shutdown   = msm_gpio_irq_shutdown,
 818 };
 819
 820 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 821 {
 822         const struct msm_pingroup *g;
 823         struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc);
 824         struct irq_chip *chip = irq_get_chip(irq);
 825         int irq_pin;
 826         int handled = 0;
 827         u32 val;
 828         int i;
 829
 830         chained_irq_enter(chip, desc);
 831
 832         /*
 833          * Each pin has it's own IRQ status register, so use
 834          * enabled_irq bitmap to limit the number of reads.
 835          */
 836         for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
 837                 g = &pctrl->soc->groups[i];
 838                 val = readl(pctrl->regs + g->intr_status_reg);
 839                 if (val & BIT(g->intr_status_bit)) {
 840                         irq_pin = irq_find_mapping(pctrl->domain, i);
 841                         generic_handle_irq(irq_pin);
 842                         handled++;
 843                 }
 844         }
 845
 846         /* No interrupts were flagged */
 847         if (handled == 0)
 848                 handle_bad_irq(irq, desc);
 849
 850         chained_irq_exit(chip, desc);
 851 }
 852
 853 /*
 854  * This lock class tells lockdep that GPIO irqs are in a different
 855  * category than their parents, so it won't report false recursion.
 856  */
 857 static struct lock_class_key gpio_lock_class;
 858
 859 static int msm_gpio_init(struct msm_pinctrl *pctrl)
 860 {
 861         struct gpio_chip *chip;
 862         int irq;
 863         int ret;
 864         int i;
 865         int r;
 866         unsigned ngpio = pctrl->soc->ngpios;
 867
 868         if (WARN_ON(ngpio > MAX_NR_GPIO))
 869                 return -EINVAL;
 870
 871         chip = &pctrl->chip;
 872         chip->base = 0;
 873         chip->ngpio = ngpio;
 874         chip->label = dev_name(pctrl->dev);
 875         chip->dev = pctrl->dev;
 876         chip->owner = THIS_MODULE;
 877         chip->of_node = pctrl->dev->of_node;
 878
 879         ret = gpiochip_add(&pctrl->chip);
 880         if (ret) {
 881                 dev_err(pctrl->dev, "Failed register gpiochip\n");
 882                 return ret;
 883         }
 884
 885         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
 886         if (ret) {
 887                 dev_err(pctrl->dev, "Failed to add pin range\n");
 888                 return ret;
 889         }
 890
 891         pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio,
 892                                               &irq_domain_simple_ops, NULL);
 893         if (!pctrl->domain) {
 894                 dev_err(pctrl->dev, "Failed to register irq domain\n");
 895                 r = gpiochip_remove(&pctrl->chip);
 896                 return -ENOSYS;
 897         }
 898
 899         for (i = 0; i < chip->ngpio; i++) {
 900                 irq = irq_create_mapping(pctrl->domain, i);
 901                 irq_set_lockdep_class(irq, &gpio_lock_class);
 902                 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq);
 903                 irq_set_chip_data(irq, pctrl);
 904         }
 905
 906         irq_set_handler_data(pctrl->irq, pctrl);
 907         irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler);
 908
 909         return 0;
 910 }
 911
 912 int msm_pinctrl_probe(struct platform_device *pdev,
 913                       const struct msm_pinctrl_soc_data *soc_data)
 914 {
 915         struct msm_pinctrl *pctrl;
 916         struct resource *res;
 917         int ret;
 918
 919         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 920         if (!pctrl) {
 921                 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
 922                 return -ENOMEM;
 923         }
 924         pctrl->dev = &pdev->dev;
 925         pctrl->soc = soc_data;
 926         pctrl->chip = msm_gpio_template;
 927
 928         spin_lock_init(&pctrl->lock);
 929
 930         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 931         pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
 932         if (IS_ERR(pctrl->regs))
 933                 return PTR_ERR(pctrl->regs);
 934
 935         pctrl->irq = platform_get_irq(pdev, 0);
 936         if (pctrl->irq < 0) {
 937                 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
 938                 return pctrl->irq;
 939         }
 940
 941         msm_pinctrl_desc.name = dev_name(&pdev->dev);
 942         msm_pinctrl_desc.pins = pctrl->soc->pins;
 943         msm_pinctrl_desc.npins = pctrl->soc->npins;
 944         pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
 945         if (!pctrl->pctrl) {
 946                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 947                 return -ENODEV;
 948         }
 949
 950         ret = msm_gpio_init(pctrl);
 951         if (ret) {
 952                 pinctrl_unregister(pctrl->pctrl);
 953                 return ret;
 954         }
 955
 956         platform_set_drvdata(pdev, pctrl);
 957
 958         dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
 959
 960         return 0;
 961 }
 962 EXPORT_SYMBOL(msm_pinctrl_probe);
 963
 964 int msm_pinctrl_remove(struct platform_device *pdev)
 965 {
 966         struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
 967         int ret;
 968
 969         ret = gpiochip_remove(&pctrl->chip);
 970         if (ret) {
 971                 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
 972                 return ret;
 973         }
 974
 975         irq_set_chained_handler(pctrl->irq, NULL);
 976         irq_domain_remove(pctrl->domain);
 977         pinctrl_unregister(pctrl->pctrl);
 978
 979         return 0;
 980 }
 981 EXPORT_SYMBOL(msm_pinctrl_remove);
 982