2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/err.h>
16 #include <linux/irqdomain.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/slab.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/irq.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/spinlock.h>
35 #include "pinctrl-msm.h"
36 #include "pinctrl-utils.h"
38 #define MAX_NR_GPIO 300
41 * struct msm_pinctrl - state for a pinctrl-msm device
42 * @dev: device handle.
43 * @pctrl: pinctrl handle.
44 * @domain: irqdomain handle.
45 * @chip: gpiochip handle.
46 * @irq: parent irq for the TLMM irq_chip.
47 * @lock: Spinlock to protect register resources as well
48 * as msm_pinctrl data structures.
49 * @enabled_irqs: Bitmap of currently enabled irqs.
50 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
52 * @soc; Reference to soc_data of platform specific data.
53 * @regs: Base address for the TLMM register map.
57 struct pinctrl_dev *pctrl;
58 struct irq_domain *domain;
59 struct gpio_chip chip;
64 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
65 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
67 const struct msm_pinctrl_soc_data *soc;
71 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
73 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
75 return pctrl->soc->ngroups;
78 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
81 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
83 return pctrl->soc->groups[group].name;
86 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
88 const unsigned **pins,
91 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
93 *pins = pctrl->soc->groups[group].pins;
94 *num_pins = pctrl->soc->groups[group].npins;
98 static const struct pinctrl_ops msm_pinctrl_ops = {
99 .get_groups_count = msm_get_groups_count,
100 .get_group_name = msm_get_group_name,
101 .get_group_pins = msm_get_group_pins,
102 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
103 .dt_free_map = pinctrl_utils_dt_free_map,
106 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
108 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
110 return pctrl->soc->nfunctions;
113 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
116 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
118 return pctrl->soc->functions[function].name;
121 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
123 const char * const **groups,
124 unsigned * const num_groups)
126 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
128 *groups = pctrl->soc->functions[function].groups;
129 *num_groups = pctrl->soc->functions[function].ngroups;
133 static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
137 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
138 const struct msm_pingroup *g;
143 g = &pctrl->soc->groups[group];
145 if (WARN_ON(g->mux_bit < 0))
148 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
149 if (g->funcs[i] == function)
153 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
156 spin_lock_irqsave(&pctrl->lock, flags);
158 val = readl(pctrl->regs + g->ctl_reg);
159 val &= ~(0x7 << g->mux_bit);
160 val |= i << g->mux_bit;
161 writel(val, pctrl->regs + g->ctl_reg);
163 spin_unlock_irqrestore(&pctrl->lock, flags);
168 static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
172 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
173 const struct msm_pingroup *g;
177 g = &pctrl->soc->groups[group];
179 if (WARN_ON(g->mux_bit < 0))
182 spin_lock_irqsave(&pctrl->lock, flags);
184 /* Clear the mux bits to select gpio mode */
185 val = readl(pctrl->regs + g->ctl_reg);
186 val &= ~(0x7 << g->mux_bit);
187 writel(val, pctrl->regs + g->ctl_reg);
189 spin_unlock_irqrestore(&pctrl->lock, flags);
192 static const struct pinmux_ops msm_pinmux_ops = {
193 .get_functions_count = msm_get_functions_count,
194 .get_function_name = msm_get_function_name,
195 .get_function_groups = msm_get_function_groups,
196 .enable = msm_pinmux_enable,
197 .disable = msm_pinmux_disable,
200 static int msm_config_reg(struct msm_pinctrl *pctrl,
201 const struct msm_pingroup *g,
207 case PIN_CONFIG_BIAS_DISABLE:
208 case PIN_CONFIG_BIAS_PULL_DOWN:
209 case PIN_CONFIG_BIAS_PULL_UP:
213 case PIN_CONFIG_DRIVE_STRENGTH:
217 case PIN_CONFIG_OUTPUT:
223 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
230 static int msm_config_get(struct pinctrl_dev *pctldev,
232 unsigned long *config)
234 dev_err(pctldev->dev, "pin_config_set op not supported\n");
238 static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
239 unsigned long *configs, unsigned num_configs)
241 dev_err(pctldev->dev, "pin_config_set op not supported\n");
245 #define MSM_NO_PULL 0
246 #define MSM_PULL_DOWN 1
247 #define MSM_PULL_UP 3
249 static unsigned msm_regval_to_drive(u32 val)
251 return (val + 1) * 2;
254 static int msm_config_group_get(struct pinctrl_dev *pctldev,
256 unsigned long *config)
258 const struct msm_pingroup *g;
259 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
260 unsigned param = pinconf_to_config_param(*config);
267 g = &pctrl->soc->groups[group];
269 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
273 val = readl(pctrl->regs + g->ctl_reg);
274 arg = (val >> bit) & mask;
276 /* Convert register value to pinconf value */
278 case PIN_CONFIG_BIAS_DISABLE:
279 arg = arg == MSM_NO_PULL;
281 case PIN_CONFIG_BIAS_PULL_DOWN:
282 arg = arg == MSM_PULL_DOWN;
284 case PIN_CONFIG_BIAS_PULL_UP:
285 arg = arg == MSM_PULL_UP;
287 case PIN_CONFIG_DRIVE_STRENGTH:
288 arg = msm_regval_to_drive(arg);
290 case PIN_CONFIG_OUTPUT:
291 /* Pin is not output */
295 val = readl(pctrl->regs + g->io_reg);
296 arg = !!(val & BIT(g->in_bit));
299 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
304 *config = pinconf_to_config_packed(param, arg);
309 static int msm_config_group_set(struct pinctrl_dev *pctldev,
311 unsigned long *configs,
312 unsigned num_configs)
314 const struct msm_pingroup *g;
315 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
325 g = &pctrl->soc->groups[group];
327 for (i = 0; i < num_configs; i++) {
328 param = pinconf_to_config_param(configs[i]);
329 arg = pinconf_to_config_argument(configs[i]);
331 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
335 /* Convert pinconf values to register values */
337 case PIN_CONFIG_BIAS_DISABLE:
340 case PIN_CONFIG_BIAS_PULL_DOWN:
343 case PIN_CONFIG_BIAS_PULL_UP:
346 case PIN_CONFIG_DRIVE_STRENGTH:
347 /* Check for invalid values */
348 if (arg > 16 || arg < 2 || (arg % 2) != 0)
353 case PIN_CONFIG_OUTPUT:
354 /* set output value */
355 spin_lock_irqsave(&pctrl->lock, flags);
356 val = readl(pctrl->regs + g->io_reg);
358 val |= BIT(g->out_bit);
360 val &= ~BIT(g->out_bit);
361 writel(val, pctrl->regs + g->io_reg);
362 spin_unlock_irqrestore(&pctrl->lock, flags);
368 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
373 /* Range-check user-supplied value */
375 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
379 spin_lock_irqsave(&pctrl->lock, flags);
380 val = readl(pctrl->regs + g->ctl_reg);
381 val &= ~(mask << bit);
383 writel(val, pctrl->regs + g->ctl_reg);
384 spin_unlock_irqrestore(&pctrl->lock, flags);
390 static const struct pinconf_ops msm_pinconf_ops = {
391 .pin_config_get = msm_config_get,
392 .pin_config_set = msm_config_set,
393 .pin_config_group_get = msm_config_group_get,
394 .pin_config_group_set = msm_config_group_set,
397 static struct pinctrl_desc msm_pinctrl_desc = {
398 .pctlops = &msm_pinctrl_ops,
399 .pmxops = &msm_pinmux_ops,
400 .confops = &msm_pinconf_ops,
401 .owner = THIS_MODULE,
404 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
406 const struct msm_pingroup *g;
407 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
411 g = &pctrl->soc->groups[offset];
413 spin_lock_irqsave(&pctrl->lock, flags);
415 val = readl(pctrl->regs + g->ctl_reg);
416 val &= ~BIT(g->oe_bit);
417 writel(val, pctrl->regs + g->ctl_reg);
419 spin_unlock_irqrestore(&pctrl->lock, flags);
424 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
426 const struct msm_pingroup *g;
427 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
431 g = &pctrl->soc->groups[offset];
433 spin_lock_irqsave(&pctrl->lock, flags);
435 val = readl(pctrl->regs + g->io_reg);
437 val |= BIT(g->out_bit);
439 val &= ~BIT(g->out_bit);
440 writel(val, pctrl->regs + g->io_reg);
442 val = readl(pctrl->regs + g->ctl_reg);
443 val |= BIT(g->oe_bit);
444 writel(val, pctrl->regs + g->ctl_reg);
446 spin_unlock_irqrestore(&pctrl->lock, flags);
451 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
453 const struct msm_pingroup *g;
454 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
457 g = &pctrl->soc->groups[offset];
459 val = readl(pctrl->regs + g->io_reg);
460 return !!(val & BIT(g->in_bit));
463 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
465 const struct msm_pingroup *g;
466 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
470 g = &pctrl->soc->groups[offset];
472 spin_lock_irqsave(&pctrl->lock, flags);
474 val = readl(pctrl->regs + g->io_reg);
476 val |= BIT(g->out_bit);
478 val &= ~BIT(g->out_bit);
479 writel(val, pctrl->regs + g->io_reg);
481 spin_unlock_irqrestore(&pctrl->lock, flags);
484 static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
486 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
488 return irq_find_mapping(pctrl->domain, offset);
491 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
493 int gpio = chip->base + offset;
494 return pinctrl_request_gpio(gpio);
497 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
499 int gpio = chip->base + offset;
500 return pinctrl_free_gpio(gpio);
503 #ifdef CONFIG_DEBUG_FS
504 #include <linux/seq_file.h>
506 static void msm_gpio_dbg_show_one(struct seq_file *s,
507 struct pinctrl_dev *pctldev,
508 struct gpio_chip *chip,
512 const struct msm_pingroup *g;
513 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
520 static const char * const pulls[] = {
527 g = &pctrl->soc->groups[offset];
528 ctl_reg = readl(pctrl->regs + g->ctl_reg);
530 is_out = !!(ctl_reg & BIT(g->oe_bit));
531 func = (ctl_reg >> g->mux_bit) & 7;
532 drive = (ctl_reg >> g->drv_bit) & 7;
533 pull = (ctl_reg >> g->pull_bit) & 3;
535 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
536 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
537 seq_printf(s, " %s", pulls[pull]);
540 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
542 unsigned gpio = chip->base;
545 for (i = 0; i < chip->ngpio; i++, gpio++) {
546 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
552 #define msm_gpio_dbg_show NULL
555 static struct gpio_chip msm_gpio_template = {
556 .direction_input = msm_gpio_direction_input,
557 .direction_output = msm_gpio_direction_output,
560 .to_irq = msm_gpio_to_irq,
561 .request = msm_gpio_request,
562 .free = msm_gpio_free,
563 .dbg_show = msm_gpio_dbg_show,
566 /* For dual-edge interrupts in software, since some hardware has no
569 * At appropriate moments, this function may be called to flip the polarity
570 * settings of both-edge irq lines to try and catch the next edge.
572 * The attempt is considered successful if:
573 * - the status bit goes high, indicating that an edge was caught, or
574 * - the input value of the gpio doesn't change during the attempt.
575 * If the value changes twice during the process, that would cause the first
576 * test to fail but would force the second, as two opposite
577 * transitions would cause a detection no matter the polarity setting.
579 * The do-loop tries to sledge-hammer closed the timing hole between
580 * the initial value-read and the polarity-write - if the line value changes
581 * during that window, an interrupt is lost, the new polarity setting is
582 * incorrect, and the first success test will fail, causing a retry.
584 * Algorithm comes from Google's msmgpio driver.
586 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
587 const struct msm_pingroup *g,
590 int loop_limit = 100;
591 unsigned val, val2, intstat;
595 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
597 pol = readl(pctrl->regs + g->intr_cfg_reg);
598 pol ^= BIT(g->intr_polarity_bit);
599 writel(pol, pctrl->regs + g->intr_cfg_reg);
601 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
602 intstat = readl(pctrl->regs + g->intr_status_reg);
603 if (intstat || (val == val2))
605 } while (loop_limit-- > 0);
606 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
610 static void msm_gpio_irq_mask(struct irq_data *d)
612 const struct msm_pingroup *g;
613 struct msm_pinctrl *pctrl;
617 pctrl = irq_data_get_irq_chip_data(d);
618 g = &pctrl->soc->groups[d->hwirq];
620 spin_lock_irqsave(&pctrl->lock, flags);
622 val = readl(pctrl->regs + g->intr_cfg_reg);
623 val &= ~BIT(g->intr_enable_bit);
624 writel(val, pctrl->regs + g->intr_cfg_reg);
626 clear_bit(d->hwirq, pctrl->enabled_irqs);
628 spin_unlock_irqrestore(&pctrl->lock, flags);
631 static void msm_gpio_irq_unmask(struct irq_data *d)
633 const struct msm_pingroup *g;
634 struct msm_pinctrl *pctrl;
638 pctrl = irq_data_get_irq_chip_data(d);
639 g = &pctrl->soc->groups[d->hwirq];
641 spin_lock_irqsave(&pctrl->lock, flags);
643 val = readl(pctrl->regs + g->intr_status_reg);
644 val &= ~BIT(g->intr_status_bit);
645 writel(val, pctrl->regs + g->intr_status_reg);
647 val = readl(pctrl->regs + g->intr_cfg_reg);
648 val |= BIT(g->intr_enable_bit);
649 writel(val, pctrl->regs + g->intr_cfg_reg);
651 set_bit(d->hwirq, pctrl->enabled_irqs);
653 spin_unlock_irqrestore(&pctrl->lock, flags);
656 static void msm_gpio_irq_ack(struct irq_data *d)
658 const struct msm_pingroup *g;
659 struct msm_pinctrl *pctrl;
663 pctrl = irq_data_get_irq_chip_data(d);
664 g = &pctrl->soc->groups[d->hwirq];
666 spin_lock_irqsave(&pctrl->lock, flags);
668 val = readl(pctrl->regs + g->intr_status_reg);
669 val &= ~BIT(g->intr_status_bit);
670 writel(val, pctrl->regs + g->intr_status_reg);
672 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
673 msm_gpio_update_dual_edge_pos(pctrl, g, d);
675 spin_unlock_irqrestore(&pctrl->lock, flags);
678 #define INTR_TARGET_PROC_APPS 4
680 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
682 const struct msm_pingroup *g;
683 struct msm_pinctrl *pctrl;
687 pctrl = irq_data_get_irq_chip_data(d);
688 g = &pctrl->soc->groups[d->hwirq];
690 spin_lock_irqsave(&pctrl->lock, flags);
693 * For hw without possibility of detecting both edges
695 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
696 set_bit(d->hwirq, pctrl->dual_edge_irqs);
698 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
700 /* Route interrupts to application cpu */
701 val = readl(pctrl->regs + g->intr_target_reg);
702 val &= ~(7 << g->intr_target_bit);
703 val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
704 writel(val, pctrl->regs + g->intr_target_reg);
706 /* Update configuration for gpio.
707 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
708 * internal circuitry of TLMM, toggling the RAW_STATUS
709 * could cause the INTR_STATUS to be set for EDGE interrupts.
711 val = readl(pctrl->regs + g->intr_cfg_reg);
712 val |= BIT(g->intr_raw_status_bit);
713 if (g->intr_detection_width == 2) {
714 val &= ~(3 << g->intr_detection_bit);
715 val &= ~(1 << g->intr_polarity_bit);
717 case IRQ_TYPE_EDGE_RISING:
718 val |= 1 << g->intr_detection_bit;
719 val |= BIT(g->intr_polarity_bit);
721 case IRQ_TYPE_EDGE_FALLING:
722 val |= 2 << g->intr_detection_bit;
723 val |= BIT(g->intr_polarity_bit);
725 case IRQ_TYPE_EDGE_BOTH:
726 val |= 3 << g->intr_detection_bit;
727 val |= BIT(g->intr_polarity_bit);
729 case IRQ_TYPE_LEVEL_LOW:
731 case IRQ_TYPE_LEVEL_HIGH:
732 val |= BIT(g->intr_polarity_bit);
735 } else if (g->intr_detection_width == 1) {
736 val &= ~(1 << g->intr_detection_bit);
737 val &= ~(1 << g->intr_polarity_bit);
739 case IRQ_TYPE_EDGE_RISING:
740 val |= BIT(g->intr_detection_bit);
741 val |= BIT(g->intr_polarity_bit);
743 case IRQ_TYPE_EDGE_FALLING:
744 val |= BIT(g->intr_detection_bit);
746 case IRQ_TYPE_EDGE_BOTH:
747 val |= BIT(g->intr_detection_bit);
749 case IRQ_TYPE_LEVEL_LOW:
751 case IRQ_TYPE_LEVEL_HIGH:
752 val |= BIT(g->intr_polarity_bit);
758 writel(val, pctrl->regs + g->intr_cfg_reg);
760 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
761 msm_gpio_update_dual_edge_pos(pctrl, g, d);
763 spin_unlock_irqrestore(&pctrl->lock, flags);
765 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
766 __irq_set_handler_locked(d->irq, handle_level_irq);
767 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
768 __irq_set_handler_locked(d->irq, handle_edge_irq);
773 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
775 struct msm_pinctrl *pctrl;
778 pctrl = irq_data_get_irq_chip_data(d);
780 spin_lock_irqsave(&pctrl->lock, flags);
782 irq_set_irq_wake(pctrl->irq, on);
784 spin_unlock_irqrestore(&pctrl->lock, flags);
789 static unsigned int msm_gpio_irq_startup(struct irq_data *d)
791 struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
793 if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) {
794 dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n",
797 msm_gpio_irq_unmask(d);
801 static void msm_gpio_irq_shutdown(struct irq_data *d)
803 struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
805 msm_gpio_irq_mask(d);
806 gpio_unlock_as_irq(&pctrl->chip, d->hwirq);
809 static struct irq_chip msm_gpio_irq_chip = {
811 .irq_mask = msm_gpio_irq_mask,
812 .irq_unmask = msm_gpio_irq_unmask,
813 .irq_ack = msm_gpio_irq_ack,
814 .irq_set_type = msm_gpio_irq_set_type,
815 .irq_set_wake = msm_gpio_irq_set_wake,
816 .irq_startup = msm_gpio_irq_startup,
817 .irq_shutdown = msm_gpio_irq_shutdown,
820 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
822 const struct msm_pingroup *g;
823 struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc);
824 struct irq_chip *chip = irq_get_chip(irq);
830 chained_irq_enter(chip, desc);
833 * Each pin has it's own IRQ status register, so use
834 * enabled_irq bitmap to limit the number of reads.
836 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
837 g = &pctrl->soc->groups[i];
838 val = readl(pctrl->regs + g->intr_status_reg);
839 if (val & BIT(g->intr_status_bit)) {
840 irq_pin = irq_find_mapping(pctrl->domain, i);
841 generic_handle_irq(irq_pin);
846 /* No interrupts were flagged */
848 handle_bad_irq(irq, desc);
850 chained_irq_exit(chip, desc);
854 * This lock class tells lockdep that GPIO irqs are in a different
855 * category than their parents, so it won't report false recursion.
857 static struct lock_class_key gpio_lock_class;
859 static int msm_gpio_init(struct msm_pinctrl *pctrl)
861 struct gpio_chip *chip;
866 unsigned ngpio = pctrl->soc->ngpios;
868 if (WARN_ON(ngpio > MAX_NR_GPIO))
874 chip->label = dev_name(pctrl->dev);
875 chip->dev = pctrl->dev;
876 chip->owner = THIS_MODULE;
877 chip->of_node = pctrl->dev->of_node;
879 ret = gpiochip_add(&pctrl->chip);
881 dev_err(pctrl->dev, "Failed register gpiochip\n");
885 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
887 dev_err(pctrl->dev, "Failed to add pin range\n");
891 pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio,
892 &irq_domain_simple_ops, NULL);
893 if (!pctrl->domain) {
894 dev_err(pctrl->dev, "Failed to register irq domain\n");
895 r = gpiochip_remove(&pctrl->chip);
899 for (i = 0; i < chip->ngpio; i++) {
900 irq = irq_create_mapping(pctrl->domain, i);
901 irq_set_lockdep_class(irq, &gpio_lock_class);
902 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq);
903 irq_set_chip_data(irq, pctrl);
906 irq_set_handler_data(pctrl->irq, pctrl);
907 irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler);
912 int msm_pinctrl_probe(struct platform_device *pdev,
913 const struct msm_pinctrl_soc_data *soc_data)
915 struct msm_pinctrl *pctrl;
916 struct resource *res;
919 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
921 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
924 pctrl->dev = &pdev->dev;
925 pctrl->soc = soc_data;
926 pctrl->chip = msm_gpio_template;
928 spin_lock_init(&pctrl->lock);
930 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
931 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
932 if (IS_ERR(pctrl->regs))
933 return PTR_ERR(pctrl->regs);
935 pctrl->irq = platform_get_irq(pdev, 0);
936 if (pctrl->irq < 0) {
937 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
941 msm_pinctrl_desc.name = dev_name(&pdev->dev);
942 msm_pinctrl_desc.pins = pctrl->soc->pins;
943 msm_pinctrl_desc.npins = pctrl->soc->npins;
944 pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
946 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
950 ret = msm_gpio_init(pctrl);
952 pinctrl_unregister(pctrl->pctrl);
956 platform_set_drvdata(pdev, pctrl);
958 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
962 EXPORT_SYMBOL(msm_pinctrl_probe);
964 int msm_pinctrl_remove(struct platform_device *pdev)
966 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
969 ret = gpiochip_remove(&pctrl->chip);
971 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
975 irq_set_chained_handler(pctrl->irq, NULL);
976 irq_domain_remove(pctrl->domain);
977 pinctrl_unregister(pctrl->pctrl);
981 EXPORT_SYMBOL(msm_pinctrl_remove);