drivers/pinctrl/pinctrl-msm.c

   1 /*
   2  * Copyright (c) 2013, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/pinctrl/pinctrl.h>
  23 #include <linux/pinctrl/pinmux.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26 #include <linux/slab.h>
  27 #include <linux/gpio.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/irq.h>
  30 #include <linux/irqchip/chained_irq.h>
  31 #include <linux/spinlock.h>
  32
  33 #include "core.h"
  34 #include "pinconf.h"
  35 #include "pinctrl-msm.h"
  36 #include "pinctrl-utils.h"
  37
  38 #define MAX_NR_GPIO 300
  39
  40 /**
  41  * struct msm_pinctrl - state for a pinctrl-msm device
  42  * @dev:            device handle.
  43  * @pctrl:          pinctrl handle.
  44  * @domain:         irqdomain handle.
  45  * @chip:           gpiochip handle.
  46  * @irq:            parent irq for the TLMM irq_chip.
  47  * @lock:           Spinlock to protect register resources as well
  48  *                  as msm_pinctrl data structures.
  49  * @enabled_irqs:   Bitmap of currently enabled irqs.
  50  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
  51  *                  detection.
  52  * @soc;            Reference to soc_data of platform specific data.
  53  * @regs:           Base address for the TLMM register map.
  54  */
  55 struct msm_pinctrl {
  56         struct device *dev;
  57         struct pinctrl_dev *pctrl;
  58         struct irq_domain *domain;
  59         struct gpio_chip chip;
  60         int irq;
  61
  62         spinlock_t lock;
  63
  64         DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
  65         DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
  66
  67         const struct msm_pinctrl_soc_data *soc;
  68         void __iomem *regs;
  69 };
  70
  71 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
  72 {
  73         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  74
  75         return pctrl->soc->ngroups;
  76 }
  77
  78 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
  79                                       unsigned group)
  80 {
  81         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  82
  83         return pctrl->soc->groups[group].name;
  84 }
  85
  86 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
  87                               unsigned group,
  88                               const unsigned **pins,
  89                               unsigned *num_pins)
  90 {
  91         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  92
  93         *pins = pctrl->soc->groups[group].pins;
  94         *num_pins = pctrl->soc->groups[group].npins;
  95         return 0;
  96 }
  97
  98 static const struct pinctrl_ops msm_pinctrl_ops = {
  99         .get_groups_count       = msm_get_groups_count,
 100         .get_group_name         = msm_get_group_name,
 101         .get_group_pins         = msm_get_group_pins,
 102         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 103         .dt_free_map            = pinctrl_utils_dt_free_map,
 104 };
 105
 106 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
 107 {
 108         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 109
 110         return pctrl->soc->nfunctions;
 111 }
 112
 113 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
 114                                          unsigned function)
 115 {
 116         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 117
 118         return pctrl->soc->functions[function].name;
 119 }
 120
 121 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
 122                                    unsigned function,
 123                                    const char * const **groups,
 124                                    unsigned * const num_groups)
 125 {
 126         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 127
 128         *groups = pctrl->soc->functions[function].groups;
 129         *num_groups = pctrl->soc->functions[function].ngroups;
 130         return 0;
 131 }
 132
 133 static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
 134                              unsigned function,
 135                              unsigned group)
 136 {
 137         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 138         const struct msm_pingroup *g;
 139         unsigned long flags;
 140         u32 val;
 141         int i;
 142
 143         g = &pctrl->soc->groups[group];
 144
 145         if (WARN_ON(g->mux_bit < 0))
 146                 return -EINVAL;
 147
 148         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 149                 if (g->funcs[i] == function)
 150                         break;
 151         }
 152
 153         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 154                 return -EINVAL;
 155
 156         spin_lock_irqsave(&pctrl->lock, flags);
 157
 158         val = readl(pctrl->regs + g->ctl_reg);
 159         val &= ~(0x7 << g->mux_bit);
 160         val |= i << g->mux_bit;
 161         writel(val, pctrl->regs + g->ctl_reg);
 162
 163         spin_unlock_irqrestore(&pctrl->lock, flags);
 164
 165         return 0;
 166 }
 167
 168 static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
 169                                unsigned function,
 170                                unsigned group)
 171 {
 172         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 173         const struct msm_pingroup *g;
 174         unsigned long flags;
 175         u32 val;
 176
 177         g = &pctrl->soc->groups[group];
 178
 179         if (WARN_ON(g->mux_bit < 0))
 180                 return;
 181
 182         spin_lock_irqsave(&pctrl->lock, flags);
 183
 184         /* Clear the mux bits to select gpio mode */
 185         val = readl(pctrl->regs + g->ctl_reg);
 186         val &= ~(0x7 << g->mux_bit);
 187         writel(val, pctrl->regs + g->ctl_reg);
 188
 189         spin_unlock_irqrestore(&pctrl->lock, flags);
 190 }
 191
 192 static const struct pinmux_ops msm_pinmux_ops = {
 193         .get_functions_count    = msm_get_functions_count,
 194         .get_function_name      = msm_get_function_name,
 195         .get_function_groups    = msm_get_function_groups,
 196         .enable                 = msm_pinmux_enable,
 197         .disable                = msm_pinmux_disable,
 198 };
 199
 200 static int msm_config_reg(struct msm_pinctrl *pctrl,
 201                           const struct msm_pingroup *g,
 202                           unsigned param,
 203                           s16 *reg,
 204                           unsigned *mask,
 205                           unsigned *bit)
 206 {
 207         switch (param) {
 208         case PIN_CONFIG_BIAS_DISABLE:
 209                 *reg = g->ctl_reg;
 210                 *bit = g->pull_bit;
 211                 *mask = 3;
 212                 break;
 213         case PIN_CONFIG_BIAS_PULL_DOWN:
 214                 *reg = g->ctl_reg;
 215                 *bit = g->pull_bit;
 216                 *mask = 3;
 217                 break;
 218         case PIN_CONFIG_BIAS_PULL_UP:
 219                 *reg = g->ctl_reg;
 220                 *bit = g->pull_bit;
 221                 *mask = 3;
 222                 break;
 223         case PIN_CONFIG_DRIVE_STRENGTH:
 224                 *reg = g->ctl_reg;
 225                 *bit = g->drv_bit;
 226                 *mask = 7;
 227                 break;
 228         case PIN_CONFIG_OUTPUT:
 229                 *reg = g->ctl_reg;
 230                 *bit = g->oe_bit;
 231                 *mask = 1;
 232                 break;
 233         default:
 234                 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
 235                 return -ENOTSUPP;
 236         }
 237
 238         if (*reg < 0) {
 239                 dev_err(pctrl->dev, "Config param %04x not supported on group %s\n",
 240                         param, g->name);
 241                 return -ENOTSUPP;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int msm_config_get(struct pinctrl_dev *pctldev,
 248                           unsigned int pin,
 249                           unsigned long *config)
 250 {
 251         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 252         return -ENOTSUPP;
 253 }
 254
 255 static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 256                                 unsigned long *configs, unsigned num_configs)
 257 {
 258         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 259         return -ENOTSUPP;
 260 }
 261
 262 #define MSM_NO_PULL     0
 263 #define MSM_PULL_DOWN   1
 264 #define MSM_PULL_UP     3
 265
 266 static unsigned msm_regval_to_drive(u32 val)
 267 {
 268         return (val + 1) * 2;
 269 }
 270
 271 static int msm_config_group_get(struct pinctrl_dev *pctldev,
 272                                 unsigned int group,
 273                                 unsigned long *config)
 274 {
 275         const struct msm_pingroup *g;
 276         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 277         unsigned param = pinconf_to_config_param(*config);
 278         unsigned mask;
 279         unsigned arg;
 280         unsigned bit;
 281         s16 reg;
 282         int ret;
 283         u32 val;
 284
 285         g = &pctrl->soc->groups[group];
 286
 287         ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
 288         if (ret < 0)
 289                 return ret;
 290
 291         val = readl(pctrl->regs + reg);
 292         arg = (val >> bit) & mask;
 293
 294         /* Convert register value to pinconf value */
 295         switch (param) {
 296         case PIN_CONFIG_BIAS_DISABLE:
 297                 arg = arg == MSM_NO_PULL;
 298                 break;
 299         case PIN_CONFIG_BIAS_PULL_DOWN:
 300                 arg = arg == MSM_PULL_DOWN;
 301                 break;
 302         case PIN_CONFIG_BIAS_PULL_UP:
 303                 arg = arg == MSM_PULL_UP;
 304                 break;
 305         case PIN_CONFIG_DRIVE_STRENGTH:
 306                 arg = msm_regval_to_drive(arg);
 307                 break;
 308         case PIN_CONFIG_OUTPUT:
 309                 /* Pin is not output */
 310                 if (!arg)
 311                         return -EINVAL;
 312
 313                 val = readl(pctrl->regs + g->io_reg);
 314                 arg = !!(val & BIT(g->in_bit));
 315                 break;
 316         default:
 317                 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 318                         param);
 319                 return -EINVAL;
 320         }
 321
 322         *config = pinconf_to_config_packed(param, arg);
 323
 324         return 0;
 325 }
 326
 327 static int msm_config_group_set(struct pinctrl_dev *pctldev,
 328                                 unsigned group,
 329                                 unsigned long *configs,
 330                                 unsigned num_configs)
 331 {
 332         const struct msm_pingroup *g;
 333         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 334         unsigned long flags;
 335         unsigned param;
 336         unsigned mask;
 337         unsigned arg;
 338         unsigned bit;
 339         s16 reg;
 340         int ret;
 341         u32 val;
 342         int i;
 343
 344         g = &pctrl->soc->groups[group];
 345
 346         for (i = 0; i < num_configs; i++) {
 347                 param = pinconf_to_config_param(configs[i]);
 348                 arg = pinconf_to_config_argument(configs[i]);
 349
 350                 ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
 351                 if (ret < 0)
 352                         return ret;
 353
 354                 /* Convert pinconf values to register values */
 355                 switch (param) {
 356                 case PIN_CONFIG_BIAS_DISABLE:
 357                         arg = MSM_NO_PULL;
 358                         break;
 359                 case PIN_CONFIG_BIAS_PULL_DOWN:
 360                         arg = MSM_PULL_DOWN;
 361                         break;
 362                 case PIN_CONFIG_BIAS_PULL_UP:
 363                         arg = MSM_PULL_UP;
 364                         break;
 365                 case PIN_CONFIG_DRIVE_STRENGTH:
 366                         /* Check for invalid values */
 367                         if (arg > 16 || arg < 2 || (arg % 2) != 0)
 368                                 arg = -1;
 369                         else
 370                                 arg = (arg / 2) - 1;
 371                         break;
 372                 case PIN_CONFIG_OUTPUT:
 373                         /* set output value */
 374                         spin_lock_irqsave(&pctrl->lock, flags);
 375                         val = readl(pctrl->regs + g->io_reg);
 376                         if (arg)
 377                                 val |= BIT(g->out_bit);
 378                         else
 379                                 val &= ~BIT(g->out_bit);
 380                         writel(val, pctrl->regs + g->io_reg);
 381                         spin_unlock_irqrestore(&pctrl->lock, flags);
 382
 383                         /* enable output */
 384                         arg = 1;
 385                         break;
 386                 default:
 387                         dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 388                                 param);
 389                         return -EINVAL;
 390                 }
 391
 392                 /* Range-check user-supplied value */
 393                 if (arg & ~mask) {
 394                         dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
 395                         return -EINVAL;
 396                 }
 397
 398                 spin_lock_irqsave(&pctrl->lock, flags);
 399                 val = readl(pctrl->regs + reg);
 400                 val &= ~(mask << bit);
 401                 val |= arg << bit;
 402                 writel(val, pctrl->regs + reg);
 403                 spin_unlock_irqrestore(&pctrl->lock, flags);
 404         }
 405
 406         return 0;
 407 }
 408
 409 static const struct pinconf_ops msm_pinconf_ops = {
 410         .pin_config_get         = msm_config_get,
 411         .pin_config_set         = msm_config_set,
 412         .pin_config_group_get   = msm_config_group_get,
 413         .pin_config_group_set   = msm_config_group_set,
 414 };
 415
 416 static struct pinctrl_desc msm_pinctrl_desc = {
 417         .pctlops = &msm_pinctrl_ops,
 418         .pmxops = &msm_pinmux_ops,
 419         .confops = &msm_pinconf_ops,
 420         .owner = THIS_MODULE,
 421 };
 422
 423 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 424 {
 425         const struct msm_pingroup *g;
 426         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 427         unsigned long flags;
 428         u32 val;
 429
 430         g = &pctrl->soc->groups[offset];
 431         if (WARN_ON(g->io_reg < 0))
 432                 return -EINVAL;
 433
 434         spin_lock_irqsave(&pctrl->lock, flags);
 435
 436         val = readl(pctrl->regs + g->ctl_reg);
 437         val &= ~BIT(g->oe_bit);
 438         writel(val, pctrl->regs + g->ctl_reg);
 439
 440         spin_unlock_irqrestore(&pctrl->lock, flags);
 441
 442         return 0;
 443 }
 444
 445 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 446 {
 447         const struct msm_pingroup *g;
 448         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 449         unsigned long flags;
 450         u32 val;
 451
 452         g = &pctrl->soc->groups[offset];
 453         if (WARN_ON(g->io_reg < 0))
 454                 return -EINVAL;
 455
 456         spin_lock_irqsave(&pctrl->lock, flags);
 457
 458         val = readl(pctrl->regs + g->io_reg);
 459         if (value)
 460                 val |= BIT(g->out_bit);
 461         else
 462                 val &= ~BIT(g->out_bit);
 463         writel(val, pctrl->regs + g->io_reg);
 464
 465         val = readl(pctrl->regs + g->ctl_reg);
 466         val |= BIT(g->oe_bit);
 467         writel(val, pctrl->regs + g->ctl_reg);
 468
 469         spin_unlock_irqrestore(&pctrl->lock, flags);
 470
 471         return 0;
 472 }
 473
 474 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
 475 {
 476         const struct msm_pingroup *g;
 477         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 478         u32 val;
 479
 480         g = &pctrl->soc->groups[offset];
 481         if (WARN_ON(g->io_reg < 0))
 482                 return -EINVAL;
 483
 484         val = readl(pctrl->regs + g->io_reg);
 485         return !!(val & BIT(g->in_bit));
 486 }
 487
 488 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 489 {
 490         const struct msm_pingroup *g;
 491         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 492         unsigned long flags;
 493         u32 val;
 494
 495         g = &pctrl->soc->groups[offset];
 496         if (WARN_ON(g->io_reg < 0))
 497                 return;
 498
 499         spin_lock_irqsave(&pctrl->lock, flags);
 500
 501         val = readl(pctrl->regs + g->io_reg);
 502         if (value)
 503                 val |= BIT(g->out_bit);
 504         else
 505                 val &= ~BIT(g->out_bit);
 506         writel(val, pctrl->regs + g->io_reg);
 507
 508         spin_unlock_irqrestore(&pctrl->lock, flags);
 509 }
 510
 511 static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 512 {
 513         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 514
 515         return irq_find_mapping(pctrl->domain, offset);
 516 }
 517
 518 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
 519 {
 520         int gpio = chip->base + offset;
 521         return pinctrl_request_gpio(gpio);
 522 }
 523
 524 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
 525 {
 526         int gpio = chip->base + offset;
 527         return pinctrl_free_gpio(gpio);
 528 }
 529
 530 #ifdef CONFIG_DEBUG_FS
 531 #include <linux/seq_file.h>
 532
 533 static void msm_gpio_dbg_show_one(struct seq_file *s,
 534                                   struct pinctrl_dev *pctldev,
 535                                   struct gpio_chip *chip,
 536                                   unsigned offset,
 537                                   unsigned gpio)
 538 {
 539         const struct msm_pingroup *g;
 540         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 541         unsigned func;
 542         int is_out;
 543         int drive;
 544         int pull;
 545         u32 ctl_reg;
 546
 547         static const char * const pulls[] = {
 548                 "no pull",
 549                 "pull down",
 550                 "keeper",
 551                 "pull up"
 552         };
 553
 554         g = &pctrl->soc->groups[offset];
 555         ctl_reg = readl(pctrl->regs + g->ctl_reg);
 556
 557         is_out = !!(ctl_reg & BIT(g->oe_bit));
 558         func = (ctl_reg >> g->mux_bit) & 7;
 559         drive = (ctl_reg >> g->drv_bit) & 7;
 560         pull = (ctl_reg >> g->pull_bit) & 3;
 561
 562         seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 563         seq_printf(s, " %dmA", msm_regval_to_drive(drive));
 564         seq_printf(s, " %s", pulls[pull]);
 565 }
 566
 567 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 568 {
 569         unsigned gpio = chip->base;
 570         unsigned i;
 571
 572         for (i = 0; i < chip->ngpio; i++, gpio++) {
 573                 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 574                 seq_puts(s, "\n");
 575         }
 576 }
 577
 578 #else
 579 #define msm_gpio_dbg_show NULL
 580 #endif
 581
 582 static struct gpio_chip msm_gpio_template = {
 583         .direction_input  = msm_gpio_direction_input,
 584         .direction_output = msm_gpio_direction_output,
 585         .get              = msm_gpio_get,
 586         .set              = msm_gpio_set,
 587         .to_irq           = msm_gpio_to_irq,
 588         .request          = msm_gpio_request,
 589         .free             = msm_gpio_free,
 590         .dbg_show         = msm_gpio_dbg_show,
 591 };
 592
 593 /* For dual-edge interrupts in software, since some hardware has no
 594  * such support:
 595  *
 596  * At appropriate moments, this function may be called to flip the polarity
 597  * settings of both-edge irq lines to try and catch the next edge.
 598  *
 599  * The attempt is considered successful if:
 600  * - the status bit goes high, indicating that an edge was caught, or
 601  * - the input value of the gpio doesn't change during the attempt.
 602  * If the value changes twice during the process, that would cause the first
 603  * test to fail but would force the second, as two opposite
 604  * transitions would cause a detection no matter the polarity setting.
 605  *
 606  * The do-loop tries to sledge-hammer closed the timing hole between
 607  * the initial value-read and the polarity-write - if the line value changes
 608  * during that window, an interrupt is lost, the new polarity setting is
 609  * incorrect, and the first success test will fail, causing a retry.
 610  *
 611  * Algorithm comes from Google's msmgpio driver.
 612  */
 613 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
 614                                           const struct msm_pingroup *g,
 615                                           struct irq_data *d)
 616 {
 617         int loop_limit = 100;
 618         unsigned val, val2, intstat;
 619         unsigned pol;
 620
 621         do {
 622                 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 623
 624                 pol = readl(pctrl->regs + g->intr_cfg_reg);
 625                 pol ^= BIT(g->intr_polarity_bit);
 626                 writel(pol, pctrl->regs + g->intr_cfg_reg);
 627
 628                 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 629                 intstat = readl(pctrl->regs + g->intr_status_reg);
 630                 if (intstat || (val == val2))
 631                         return;
 632         } while (loop_limit-- > 0);
 633         dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
 634                 val, val2);
 635 }
 636
 637 static void msm_gpio_irq_mask(struct irq_data *d)
 638 {
 639         const struct msm_pingroup *g;
 640         struct msm_pinctrl *pctrl;
 641         unsigned long flags;
 642         u32 val;
 643
 644         pctrl = irq_data_get_irq_chip_data(d);
 645         g = &pctrl->soc->groups[d->hwirq];
 646         if (WARN_ON(g->intr_cfg_reg < 0))
 647                 return;
 648
 649         spin_lock_irqsave(&pctrl->lock, flags);
 650
 651         val = readl(pctrl->regs + g->intr_cfg_reg);
 652         val &= ~BIT(g->intr_enable_bit);
 653         writel(val, pctrl->regs + g->intr_cfg_reg);
 654
 655         clear_bit(d->hwirq, pctrl->enabled_irqs);
 656
 657         spin_unlock_irqrestore(&pctrl->lock, flags);
 658 }
 659
 660 static void msm_gpio_irq_unmask(struct irq_data *d)
 661 {
 662         const struct msm_pingroup *g;
 663         struct msm_pinctrl *pctrl;
 664         unsigned long flags;
 665         u32 val;
 666
 667         pctrl = irq_data_get_irq_chip_data(d);
 668         g = &pctrl->soc->groups[d->hwirq];
 669         if (WARN_ON(g->intr_status_reg < 0))
 670                 return;
 671
 672         spin_lock_irqsave(&pctrl->lock, flags);
 673
 674         val = readl(pctrl->regs + g->intr_status_reg);
 675         val &= ~BIT(g->intr_status_bit);
 676         writel(val, pctrl->regs + g->intr_status_reg);
 677
 678         val = readl(pctrl->regs + g->intr_cfg_reg);
 679         val |= BIT(g->intr_enable_bit);
 680         writel(val, pctrl->regs + g->intr_cfg_reg);
 681
 682         set_bit(d->hwirq, pctrl->enabled_irqs);
 683
 684         spin_unlock_irqrestore(&pctrl->lock, flags);
 685 }
 686
 687 static void msm_gpio_irq_ack(struct irq_data *d)
 688 {
 689         const struct msm_pingroup *g;
 690         struct msm_pinctrl *pctrl;
 691         unsigned long flags;
 692         u32 val;
 693
 694         pctrl = irq_data_get_irq_chip_data(d);
 695         g = &pctrl->soc->groups[d->hwirq];
 696         if (WARN_ON(g->intr_status_reg < 0))
 697                 return;
 698
 699         spin_lock_irqsave(&pctrl->lock, flags);
 700
 701         val = readl(pctrl->regs + g->intr_status_reg);
 702         val &= ~BIT(g->intr_status_bit);
 703         writel(val, pctrl->regs + g->intr_status_reg);
 704
 705         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 706                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 707
 708         spin_unlock_irqrestore(&pctrl->lock, flags);
 709 }
 710
 711 #define INTR_TARGET_PROC_APPS    4
 712
 713 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 714 {
 715         const struct msm_pingroup *g;
 716         struct msm_pinctrl *pctrl;
 717         unsigned long flags;
 718         u32 val;
 719
 720         pctrl = irq_data_get_irq_chip_data(d);
 721         g = &pctrl->soc->groups[d->hwirq];
 722         if (WARN_ON(g->intr_cfg_reg < 0))
 723                 return -EINVAL;
 724
 725         spin_lock_irqsave(&pctrl->lock, flags);
 726
 727         /*
 728          * For hw without possibility of detecting both edges
 729          */
 730         if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
 731                 set_bit(d->hwirq, pctrl->dual_edge_irqs);
 732         else
 733                 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 734
 735         /* Route interrupts to application cpu */
 736         val = readl(pctrl->regs + g->intr_target_reg);
 737         val &= ~(7 << g->intr_target_bit);
 738         val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
 739         writel(val, pctrl->regs + g->intr_target_reg);
 740
 741         /* Update configuration for gpio.
 742          * RAW_STATUS_EN is left on for all gpio irqs. Due to the
 743          * internal circuitry of TLMM, toggling the RAW_STATUS
 744          * could cause the INTR_STATUS to be set for EDGE interrupts.
 745          */
 746         val = readl(pctrl->regs + g->intr_cfg_reg);
 747         val |= BIT(g->intr_raw_status_bit);
 748         if (g->intr_detection_width == 2) {
 749                 val &= ~(3 << g->intr_detection_bit);
 750                 val &= ~(1 << g->intr_polarity_bit);
 751                 switch (type) {
 752                 case IRQ_TYPE_EDGE_RISING:
 753                         val |= 1 << g->intr_detection_bit;
 754                         val |= BIT(g->intr_polarity_bit);
 755                         break;
 756                 case IRQ_TYPE_EDGE_FALLING:
 757                         val |= 2 << g->intr_detection_bit;
 758                         val |= BIT(g->intr_polarity_bit);
 759                         break;
 760                 case IRQ_TYPE_EDGE_BOTH:
 761                         val |= 3 << g->intr_detection_bit;
 762                         val |= BIT(g->intr_polarity_bit);
 763                         break;
 764                 case IRQ_TYPE_LEVEL_LOW:
 765                         break;
 766                 case IRQ_TYPE_LEVEL_HIGH:
 767                         val |= BIT(g->intr_polarity_bit);
 768                         break;
 769                 }
 770         } else if (g->intr_detection_width == 1) {
 771                 val &= ~(1 << g->intr_detection_bit);
 772                 val &= ~(1 << g->intr_polarity_bit);
 773                 switch (type) {
 774                 case IRQ_TYPE_EDGE_RISING:
 775                         val |= BIT(g->intr_detection_bit);
 776                         val |= BIT(g->intr_polarity_bit);
 777                         break;
 778                 case IRQ_TYPE_EDGE_FALLING:
 779                         val |= BIT(g->intr_detection_bit);
 780                         break;
 781                 case IRQ_TYPE_EDGE_BOTH:
 782                         val |= BIT(g->intr_detection_bit);
 783                         break;
 784                 case IRQ_TYPE_LEVEL_LOW:
 785                         break;
 786                 case IRQ_TYPE_LEVEL_HIGH:
 787                         val |= BIT(g->intr_polarity_bit);
 788                         break;
 789                 }
 790         } else {
 791                 BUG();
 792         }
 793         writel(val, pctrl->regs + g->intr_cfg_reg);
 794
 795         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 796                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 797
 798         spin_unlock_irqrestore(&pctrl->lock, flags);
 799
 800         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 801                 __irq_set_handler_locked(d->irq, handle_level_irq);
 802         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 803                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 804
 805         return 0;
 806 }
 807
 808 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 809 {
 810         struct msm_pinctrl *pctrl;
 811         unsigned long flags;
 812
 813         pctrl = irq_data_get_irq_chip_data(d);
 814
 815         spin_lock_irqsave(&pctrl->lock, flags);
 816
 817         irq_set_irq_wake(pctrl->irq, on);
 818
 819         spin_unlock_irqrestore(&pctrl->lock, flags);
 820
 821         return 0;
 822 }
 823
 824 static unsigned int msm_gpio_irq_startup(struct irq_data *d)
 825 {
 826         struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
 827
 828         if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) {
 829                 dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n",
 830                         d->hwirq);
 831         }
 832         msm_gpio_irq_unmask(d);
 833         return 0;
 834 }
 835
 836 static void msm_gpio_irq_shutdown(struct irq_data *d)
 837 {
 838         struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
 839
 840         msm_gpio_irq_mask(d);
 841         gpio_unlock_as_irq(&pctrl->chip, d->hwirq);
 842 }
 843
 844 static struct irq_chip msm_gpio_irq_chip = {
 845         .name           = "msmgpio",
 846         .irq_mask       = msm_gpio_irq_mask,
 847         .irq_unmask     = msm_gpio_irq_unmask,
 848         .irq_ack        = msm_gpio_irq_ack,
 849         .irq_set_type   = msm_gpio_irq_set_type,
 850         .irq_set_wake   = msm_gpio_irq_set_wake,
 851         .irq_startup    = msm_gpio_irq_startup,
 852         .irq_shutdown   = msm_gpio_irq_shutdown,
 853 };
 854
 855 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 856 {
 857         const struct msm_pingroup *g;
 858         struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc);
 859         struct irq_chip *chip = irq_get_chip(irq);
 860         int irq_pin;
 861         int handled = 0;
 862         u32 val;
 863         int i;
 864
 865         chained_irq_enter(chip, desc);
 866
 867         /*
 868          * Each pin has it's own IRQ status register, so use
 869          * enabled_irq bitmap to limit the number of reads.
 870          */
 871         for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
 872                 g = &pctrl->soc->groups[i];
 873                 val = readl(pctrl->regs + g->intr_status_reg);
 874                 if (val & BIT(g->intr_status_bit)) {
 875                         irq_pin = irq_find_mapping(pctrl->domain, i);
 876                         generic_handle_irq(irq_pin);
 877                         handled++;
 878                 }
 879         }
 880
 881         /* No interrupts were flagged */
 882         if (handled == 0)
 883                 handle_bad_irq(irq, desc);
 884
 885         chained_irq_exit(chip, desc);
 886 }
 887
 888 /*
 889  * This lock class tells lockdep that GPIO irqs are in a different
 890  * category than their parents, so it won't report false recursion.
 891  */
 892 static struct lock_class_key gpio_lock_class;
 893
 894 static int msm_gpio_init(struct msm_pinctrl *pctrl)
 895 {
 896         struct gpio_chip *chip;
 897         int irq;
 898         int ret;
 899         int i;
 900         int r;
 901         unsigned ngpio = pctrl->soc->ngpios;
 902
 903         if (WARN_ON(ngpio > MAX_NR_GPIO))
 904                 return -EINVAL;
 905
 906         chip = &pctrl->chip;
 907         chip->base = 0;
 908         chip->ngpio = ngpio;
 909         chip->label = dev_name(pctrl->dev);
 910         chip->dev = pctrl->dev;
 911         chip->owner = THIS_MODULE;
 912         chip->of_node = pctrl->dev->of_node;
 913
 914         ret = gpiochip_add(&pctrl->chip);
 915         if (ret) {
 916                 dev_err(pctrl->dev, "Failed register gpiochip\n");
 917                 return ret;
 918         }
 919
 920         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
 921         if (ret) {
 922                 dev_err(pctrl->dev, "Failed to add pin range\n");
 923                 return ret;
 924         }
 925
 926         pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio,
 927                                               &irq_domain_simple_ops, NULL);
 928         if (!pctrl->domain) {
 929                 dev_err(pctrl->dev, "Failed to register irq domain\n");
 930                 r = gpiochip_remove(&pctrl->chip);
 931                 return -ENOSYS;
 932         }
 933
 934         for (i = 0; i < chip->ngpio; i++) {
 935                 irq = irq_create_mapping(pctrl->domain, i);
 936                 irq_set_lockdep_class(irq, &gpio_lock_class);
 937                 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq);
 938                 irq_set_chip_data(irq, pctrl);
 939         }
 940
 941         irq_set_handler_data(pctrl->irq, pctrl);
 942         irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler);
 943
 944         return 0;
 945 }
 946
 947 int msm_pinctrl_probe(struct platform_device *pdev,
 948                       const struct msm_pinctrl_soc_data *soc_data)
 949 {
 950         struct msm_pinctrl *pctrl;
 951         struct resource *res;
 952         int ret;
 953
 954         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 955         if (!pctrl) {
 956                 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
 957                 return -ENOMEM;
 958         }
 959         pctrl->dev = &pdev->dev;
 960         pctrl->soc = soc_data;
 961         pctrl->chip = msm_gpio_template;
 962
 963         spin_lock_init(&pctrl->lock);
 964
 965         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 966         pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
 967         if (IS_ERR(pctrl->regs))
 968                 return PTR_ERR(pctrl->regs);
 969
 970         pctrl->irq = platform_get_irq(pdev, 0);
 971         if (pctrl->irq < 0) {
 972                 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
 973                 return pctrl->irq;
 974         }
 975
 976         msm_pinctrl_desc.name = dev_name(&pdev->dev);
 977         msm_pinctrl_desc.pins = pctrl->soc->pins;
 978         msm_pinctrl_desc.npins = pctrl->soc->npins;
 979         pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
 980         if (!pctrl->pctrl) {
 981                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 982                 return -ENODEV;
 983         }
 984
 985         ret = msm_gpio_init(pctrl);
 986         if (ret) {
 987                 pinctrl_unregister(pctrl->pctrl);
 988                 return ret;
 989         }
 990
 991         platform_set_drvdata(pdev, pctrl);
 992
 993         dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
 994
 995         return 0;
 996 }
 997 EXPORT_SYMBOL(msm_pinctrl_probe);
 998
 999 int msm_pinctrl_remove(struct platform_device *pdev)
1000 {
1001         struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1002         int ret;
1003
1004         ret = gpiochip_remove(&pctrl->chip);
1005         if (ret) {
1006                 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
1007                 return ret;
1008         }
1009
1010         irq_set_chained_handler(pctrl->irq, NULL);
1011         irq_domain_remove(pctrl->domain);
1012         pinctrl_unregister(pctrl->pctrl);
1013
1014         return 0;
1015 }
1016 EXPORT_SYMBOL(msm_pinctrl_remove);
1017