drivers/pinctrl/pinctrl-msm.c

   1 /*
   2  * Copyright (c) 2013, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/pinctrl/pinctrl.h>
  23 #include <linux/pinctrl/pinmux.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26 #include <linux/slab.h>
  27 #include <linux/gpio.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/irq.h>
  30 #include <linux/irqchip/chained_irq.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/spinlock.h>
  33
  34 #include "core.h"
  35 #include "pinconf.h"
  36 #include "pinctrl-msm.h"
  37 #include "pinctrl-utils.h"
  38
  39 #define MAX_NR_GPIO 300
  40
  41 /**
  42  * struct msm_pinctrl - state for a pinctrl-msm device
  43  * @dev:            device handle.
  44  * @pctrl:          pinctrl handle.
  45  * @domain:         irqdomain handle.
  46  * @chip:           gpiochip handle.
  47  * @irq:            parent irq for the TLMM irq_chip.
  48  * @lock:           Spinlock to protect register resources as well
  49  *                  as msm_pinctrl data structures.
  50  * @enabled_irqs:   Bitmap of currently enabled irqs.
  51  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
  52  *                  detection.
  53  * @soc;            Reference to soc_data of platform specific data.
  54  * @regs:           Base address for the TLMM register map.
  55  */
  56 struct msm_pinctrl {
  57         struct device *dev;
  58         struct pinctrl_dev *pctrl;
  59         struct irq_domain *domain;
  60         struct gpio_chip chip;
  61         int irq;
  62
  63         spinlock_t lock;
  64
  65         DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
  66         DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
  67
  68         const struct msm_pinctrl_soc_data *soc;
  69         void __iomem *regs;
  70 };
  71
  72 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
  73 {
  74         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  75
  76         return pctrl->soc->ngroups;
  77 }
  78
  79 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
  80                                       unsigned group)
  81 {
  82         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  83
  84         return pctrl->soc->groups[group].name;
  85 }
  86
  87 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
  88                               unsigned group,
  89                               const unsigned **pins,
  90                               unsigned *num_pins)
  91 {
  92         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  93
  94         *pins = pctrl->soc->groups[group].pins;
  95         *num_pins = pctrl->soc->groups[group].npins;
  96         return 0;
  97 }
  98
  99 static const struct pinctrl_ops msm_pinctrl_ops = {
 100         .get_groups_count       = msm_get_groups_count,
 101         .get_group_name         = msm_get_group_name,
 102         .get_group_pins         = msm_get_group_pins,
 103         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 104         .dt_free_map            = pinctrl_utils_dt_free_map,
 105 };
 106
 107 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
 108 {
 109         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 110
 111         return pctrl->soc->nfunctions;
 112 }
 113
 114 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
 115                                          unsigned function)
 116 {
 117         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 118
 119         return pctrl->soc->functions[function].name;
 120 }
 121
 122 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
 123                                    unsigned function,
 124                                    const char * const **groups,
 125                                    unsigned * const num_groups)
 126 {
 127         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 128
 129         *groups = pctrl->soc->functions[function].groups;
 130         *num_groups = pctrl->soc->functions[function].ngroups;
 131         return 0;
 132 }
 133
 134 static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
 135                              unsigned function,
 136                              unsigned group)
 137 {
 138         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 139         const struct msm_pingroup *g;
 140         unsigned long flags;
 141         u32 val;
 142         int i;
 143
 144         g = &pctrl->soc->groups[group];
 145
 146         if (WARN_ON(g->mux_bit < 0))
 147                 return -EINVAL;
 148
 149         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 150                 if (g->funcs[i] == function)
 151                         break;
 152         }
 153
 154         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 155                 return -EINVAL;
 156
 157         spin_lock_irqsave(&pctrl->lock, flags);
 158
 159         val = readl(pctrl->regs + g->ctl_reg);
 160         val &= ~(0x7 << g->mux_bit);
 161         val |= i << g->mux_bit;
 162         writel(val, pctrl->regs + g->ctl_reg);
 163
 164         spin_unlock_irqrestore(&pctrl->lock, flags);
 165
 166         return 0;
 167 }
 168
 169 static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
 170                                unsigned function,
 171                                unsigned group)
 172 {
 173         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 174         const struct msm_pingroup *g;
 175         unsigned long flags;
 176         u32 val;
 177
 178         g = &pctrl->soc->groups[group];
 179
 180         if (WARN_ON(g->mux_bit < 0))
 181                 return;
 182
 183         spin_lock_irqsave(&pctrl->lock, flags);
 184
 185         /* Clear the mux bits to select gpio mode */
 186         val = readl(pctrl->regs + g->ctl_reg);
 187         val &= ~(0x7 << g->mux_bit);
 188         writel(val, pctrl->regs + g->ctl_reg);
 189
 190         spin_unlock_irqrestore(&pctrl->lock, flags);
 191 }
 192
 193 static const struct pinmux_ops msm_pinmux_ops = {
 194         .get_functions_count    = msm_get_functions_count,
 195         .get_function_name      = msm_get_function_name,
 196         .get_function_groups    = msm_get_function_groups,
 197         .enable                 = msm_pinmux_enable,
 198         .disable                = msm_pinmux_disable,
 199 };
 200
 201 static int msm_config_reg(struct msm_pinctrl *pctrl,
 202                           const struct msm_pingroup *g,
 203                           unsigned param,
 204                           s16 *reg,
 205                           unsigned *mask,
 206                           unsigned *bit)
 207 {
 208         switch (param) {
 209         case PIN_CONFIG_BIAS_DISABLE:
 210                 *reg = g->ctl_reg;
 211                 *bit = g->pull_bit;
 212                 *mask = 3;
 213                 break;
 214         case PIN_CONFIG_BIAS_PULL_DOWN:
 215                 *reg = g->ctl_reg;
 216                 *bit = g->pull_bit;
 217                 *mask = 3;
 218                 break;
 219         case PIN_CONFIG_BIAS_PULL_UP:
 220                 *reg = g->ctl_reg;
 221                 *bit = g->pull_bit;
 222                 *mask = 3;
 223                 break;
 224         case PIN_CONFIG_DRIVE_STRENGTH:
 225                 *reg = g->ctl_reg;
 226                 *bit = g->drv_bit;
 227                 *mask = 7;
 228                 break;
 229         case PIN_CONFIG_OUTPUT:
 230                 *reg = g->ctl_reg;
 231                 *bit = g->oe_bit;
 232                 *mask = 1;
 233                 break;
 234         default:
 235                 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
 236                 return -ENOTSUPP;
 237         }
 238
 239         if (*reg < 0) {
 240                 dev_err(pctrl->dev, "Config param %04x not supported on group %s\n",
 241                         param, g->name);
 242                 return -ENOTSUPP;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static int msm_config_get(struct pinctrl_dev *pctldev,
 249                           unsigned int pin,
 250                           unsigned long *config)
 251 {
 252         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 253         return -ENOTSUPP;
 254 }
 255
 256 static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 257                                 unsigned long *configs, unsigned num_configs)
 258 {
 259         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 260         return -ENOTSUPP;
 261 }
 262
 263 #define MSM_NO_PULL     0
 264 #define MSM_PULL_DOWN   1
 265 #define MSM_PULL_UP     3
 266
 267 static const unsigned msm_regval_to_drive[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
 268 static const unsigned msm_drive_to_regval[] = { -1, -1, 0, -1, 1, -1, 2, -1, 3, -1, 4, -1, 5, -1, 6, -1, 7 };
 269
 270 static int msm_config_group_get(struct pinctrl_dev *pctldev,
 271                                 unsigned int group,
 272                                 unsigned long *config)
 273 {
 274         const struct msm_pingroup *g;
 275         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 276         unsigned param = pinconf_to_config_param(*config);
 277         unsigned mask;
 278         unsigned arg;
 279         unsigned bit;
 280         s16 reg;
 281         int ret;
 282         u32 val;
 283
 284         g = &pctrl->soc->groups[group];
 285
 286         ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
 287         if (ret < 0)
 288                 return ret;
 289
 290         val = readl(pctrl->regs + reg);
 291         arg = (val >> bit) & mask;
 292
 293         /* Convert register value to pinconf value */
 294         switch (param) {
 295         case PIN_CONFIG_BIAS_DISABLE:
 296                 arg = arg == MSM_NO_PULL;
 297                 break;
 298         case PIN_CONFIG_BIAS_PULL_DOWN:
 299                 arg = arg == MSM_PULL_DOWN;
 300                 break;
 301         case PIN_CONFIG_BIAS_PULL_UP:
 302                 arg = arg == MSM_PULL_UP;
 303                 break;
 304         case PIN_CONFIG_DRIVE_STRENGTH:
 305                 arg = msm_regval_to_drive[arg];
 306                 break;
 307         case PIN_CONFIG_OUTPUT:
 308                 /* Pin is not output */
 309                 if (!arg)
 310                         return -EINVAL;
 311
 312                 val = readl(pctrl->regs + g->io_reg);
 313                 arg = !!(val & BIT(g->in_bit));
 314                 break;
 315         default:
 316                 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 317                         param);
 318                 return -EINVAL;
 319         }
 320
 321         *config = pinconf_to_config_packed(param, arg);
 322
 323         return 0;
 324 }
 325
 326 static int msm_config_group_set(struct pinctrl_dev *pctldev,
 327                                 unsigned group,
 328                                 unsigned long *configs,
 329                                 unsigned num_configs)
 330 {
 331         const struct msm_pingroup *g;
 332         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 333         unsigned long flags;
 334         unsigned param;
 335         unsigned mask;
 336         unsigned arg;
 337         unsigned bit;
 338         s16 reg;
 339         int ret;
 340         u32 val;
 341         int i;
 342
 343         g = &pctrl->soc->groups[group];
 344
 345         for (i = 0; i < num_configs; i++) {
 346                 param = pinconf_to_config_param(configs[i]);
 347                 arg = pinconf_to_config_argument(configs[i]);
 348
 349                 ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
 350                 if (ret < 0)
 351                         return ret;
 352
 353                 /* Convert pinconf values to register values */
 354                 switch (param) {
 355                 case PIN_CONFIG_BIAS_DISABLE:
 356                         arg = MSM_NO_PULL;
 357                         break;
 358                 case PIN_CONFIG_BIAS_PULL_DOWN:
 359                         arg = MSM_PULL_DOWN;
 360                         break;
 361                 case PIN_CONFIG_BIAS_PULL_UP:
 362                         arg = MSM_PULL_UP;
 363                         break;
 364                 case PIN_CONFIG_DRIVE_STRENGTH:
 365                         /* Check for invalid values */
 366                         if (arg >= ARRAY_SIZE(msm_drive_to_regval))
 367                                 arg = -1;
 368                         else
 369                                 arg = msm_drive_to_regval[arg];
 370                         break;
 371                 case PIN_CONFIG_OUTPUT:
 372                         /* set output value */
 373                         spin_lock_irqsave(&pctrl->lock, flags);
 374                         val = readl(pctrl->regs + g->io_reg);
 375                         if (arg)
 376                                 val |= BIT(g->out_bit);
 377                         else
 378                                 val &= ~BIT(g->out_bit);
 379                         writel(val, pctrl->regs + g->io_reg);
 380                         spin_unlock_irqrestore(&pctrl->lock, flags);
 381
 382                         /* enable output */
 383                         arg = 1;
 384                         break;
 385                 default:
 386                         dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 387                                 param);
 388                         return -EINVAL;
 389                 }
 390
 391                 /* Range-check user-supplied value */
 392                 if (arg & ~mask) {
 393                         dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
 394                         return -EINVAL;
 395                 }
 396
 397                 spin_lock_irqsave(&pctrl->lock, flags);
 398                 val = readl(pctrl->regs + reg);
 399                 val &= ~(mask << bit);
 400                 val |= arg << bit;
 401                 writel(val, pctrl->regs + reg);
 402                 spin_unlock_irqrestore(&pctrl->lock, flags);
 403         }
 404
 405         return 0;
 406 }
 407
 408 static const struct pinconf_ops msm_pinconf_ops = {
 409         .pin_config_get         = msm_config_get,
 410         .pin_config_set         = msm_config_set,
 411         .pin_config_group_get   = msm_config_group_get,
 412         .pin_config_group_set   = msm_config_group_set,
 413 };
 414
 415 static struct pinctrl_desc msm_pinctrl_desc = {
 416         .pctlops = &msm_pinctrl_ops,
 417         .pmxops = &msm_pinmux_ops,
 418         .confops = &msm_pinconf_ops,
 419         .owner = THIS_MODULE,
 420 };
 421
 422 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 423 {
 424         const struct msm_pingroup *g;
 425         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 426         unsigned long flags;
 427         u32 val;
 428
 429         g = &pctrl->soc->groups[offset];
 430         if (WARN_ON(g->io_reg < 0))
 431                 return -EINVAL;
 432
 433         spin_lock_irqsave(&pctrl->lock, flags);
 434
 435         val = readl(pctrl->regs + g->ctl_reg);
 436         val &= ~BIT(g->oe_bit);
 437         writel(val, pctrl->regs + g->ctl_reg);
 438
 439         spin_unlock_irqrestore(&pctrl->lock, flags);
 440
 441         return 0;
 442 }
 443
 444 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 445 {
 446         const struct msm_pingroup *g;
 447         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 448         unsigned long flags;
 449         u32 val;
 450
 451         g = &pctrl->soc->groups[offset];
 452         if (WARN_ON(g->io_reg < 0))
 453                 return -EINVAL;
 454
 455         spin_lock_irqsave(&pctrl->lock, flags);
 456
 457         val = readl(pctrl->regs + g->io_reg);
 458         if (value)
 459                 val |= BIT(g->out_bit);
 460         else
 461                 val &= ~BIT(g->out_bit);
 462         writel(val, pctrl->regs + g->io_reg);
 463
 464         val = readl(pctrl->regs + g->ctl_reg);
 465         val |= BIT(g->oe_bit);
 466         writel(val, pctrl->regs + g->ctl_reg);
 467
 468         spin_unlock_irqrestore(&pctrl->lock, flags);
 469
 470         return 0;
 471 }
 472
 473 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
 474 {
 475         const struct msm_pingroup *g;
 476         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 477         u32 val;
 478
 479         g = &pctrl->soc->groups[offset];
 480         if (WARN_ON(g->io_reg < 0))
 481                 return -EINVAL;
 482
 483         val = readl(pctrl->regs + g->io_reg);
 484         return !!(val & BIT(g->in_bit));
 485 }
 486
 487 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 488 {
 489         const struct msm_pingroup *g;
 490         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 491         unsigned long flags;
 492         u32 val;
 493
 494         g = &pctrl->soc->groups[offset];
 495         if (WARN_ON(g->io_reg < 0))
 496                 return;
 497
 498         spin_lock_irqsave(&pctrl->lock, flags);
 499
 500         val = readl(pctrl->regs + g->io_reg);
 501         if (value)
 502                 val |= BIT(g->out_bit);
 503         else
 504                 val &= ~BIT(g->out_bit);
 505         writel(val, pctrl->regs + g->io_reg);
 506
 507         spin_unlock_irqrestore(&pctrl->lock, flags);
 508 }
 509
 510 static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 511 {
 512         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 513
 514         return irq_find_mapping(pctrl->domain, offset);
 515 }
 516
 517 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
 518 {
 519         int gpio = chip->base + offset;
 520         return pinctrl_request_gpio(gpio);
 521 }
 522
 523 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
 524 {
 525         int gpio = chip->base + offset;
 526         return pinctrl_free_gpio(gpio);
 527 }
 528
 529 #ifdef CONFIG_DEBUG_FS
 530 #include <linux/seq_file.h>
 531
 532 static void msm_gpio_dbg_show_one(struct seq_file *s,
 533                                   struct pinctrl_dev *pctldev,
 534                                   struct gpio_chip *chip,
 535                                   unsigned offset,
 536                                   unsigned gpio)
 537 {
 538         const struct msm_pingroup *g;
 539         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 540         unsigned func;
 541         int is_out;
 542         int drive;
 543         int pull;
 544         u32 ctl_reg;
 545
 546         static const char * const pulls[] = {
 547                 "no pull",
 548                 "pull down",
 549                 "keeper",
 550                 "pull up"
 551         };
 552
 553         g = &pctrl->soc->groups[offset];
 554         ctl_reg = readl(pctrl->regs + g->ctl_reg);
 555
 556         is_out = !!(ctl_reg & BIT(g->oe_bit));
 557         func = (ctl_reg >> g->mux_bit) & 7;
 558         drive = (ctl_reg >> g->drv_bit) & 7;
 559         pull = (ctl_reg >> g->pull_bit) & 3;
 560
 561         seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 562         seq_printf(s, " %dmA", msm_regval_to_drive[drive]);
 563         seq_printf(s, " %s", pulls[pull]);
 564 }
 565
 566 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 567 {
 568         unsigned gpio = chip->base;
 569         unsigned i;
 570
 571         for (i = 0; i < chip->ngpio; i++, gpio++) {
 572                 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 573                 seq_puts(s, "\n");
 574         }
 575 }
 576
 577 #else
 578 #define msm_gpio_dbg_show NULL
 579 #endif
 580
 581 static struct gpio_chip msm_gpio_template = {
 582         .direction_input  = msm_gpio_direction_input,
 583         .direction_output = msm_gpio_direction_output,
 584         .get              = msm_gpio_get,
 585         .set              = msm_gpio_set,
 586         .to_irq           = msm_gpio_to_irq,
 587         .request          = msm_gpio_request,
 588         .free             = msm_gpio_free,
 589         .dbg_show         = msm_gpio_dbg_show,
 590 };
 591
 592 /* For dual-edge interrupts in software, since some hardware has no
 593  * such support:
 594  *
 595  * At appropriate moments, this function may be called to flip the polarity
 596  * settings of both-edge irq lines to try and catch the next edge.
 597  *
 598  * The attempt is considered successful if:
 599  * - the status bit goes high, indicating that an edge was caught, or
 600  * - the input value of the gpio doesn't change during the attempt.
 601  * If the value changes twice during the process, that would cause the first
 602  * test to fail but would force the second, as two opposite
 603  * transitions would cause a detection no matter the polarity setting.
 604  *
 605  * The do-loop tries to sledge-hammer closed the timing hole between
 606  * the initial value-read and the polarity-write - if the line value changes
 607  * during that window, an interrupt is lost, the new polarity setting is
 608  * incorrect, and the first success test will fail, causing a retry.
 609  *
 610  * Algorithm comes from Google's msmgpio driver.
 611  */
 612 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
 613                                           const struct msm_pingroup *g,
 614                                           struct irq_data *d)
 615 {
 616         int loop_limit = 100;
 617         unsigned val, val2, intstat;
 618         unsigned pol;
 619
 620         do {
 621                 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 622
 623                 pol = readl(pctrl->regs + g->intr_cfg_reg);
 624                 pol ^= BIT(g->intr_polarity_bit);
 625                 writel(pol, pctrl->regs + g->intr_cfg_reg);
 626
 627                 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 628                 intstat = readl(pctrl->regs + g->intr_status_reg);
 629                 if (intstat || (val == val2))
 630                         return;
 631         } while (loop_limit-- > 0);
 632         dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
 633                 val, val2);
 634 }
 635
 636 static void msm_gpio_irq_mask(struct irq_data *d)
 637 {
 638         const struct msm_pingroup *g;
 639         struct msm_pinctrl *pctrl;
 640         unsigned long flags;
 641         u32 val;
 642
 643         pctrl = irq_data_get_irq_chip_data(d);
 644         g = &pctrl->soc->groups[d->hwirq];
 645         if (WARN_ON(g->intr_cfg_reg < 0))
 646                 return;
 647
 648         spin_lock_irqsave(&pctrl->lock, flags);
 649
 650         val = readl(pctrl->regs + g->intr_cfg_reg);
 651         val &= ~BIT(g->intr_enable_bit);
 652         writel(val, pctrl->regs + g->intr_cfg_reg);
 653
 654         clear_bit(d->hwirq, pctrl->enabled_irqs);
 655
 656         spin_unlock_irqrestore(&pctrl->lock, flags);
 657 }
 658
 659 static void msm_gpio_irq_unmask(struct irq_data *d)
 660 {
 661         const struct msm_pingroup *g;
 662         struct msm_pinctrl *pctrl;
 663         unsigned long flags;
 664         u32 val;
 665
 666         pctrl = irq_data_get_irq_chip_data(d);
 667         g = &pctrl->soc->groups[d->hwirq];
 668         if (WARN_ON(g->intr_status_reg < 0))
 669                 return;
 670
 671         spin_lock_irqsave(&pctrl->lock, flags);
 672
 673         val = readl(pctrl->regs + g->intr_status_reg);
 674         val &= ~BIT(g->intr_status_bit);
 675         writel(val, pctrl->regs + g->intr_status_reg);
 676
 677         val = readl(pctrl->regs + g->intr_cfg_reg);
 678         val |= BIT(g->intr_enable_bit);
 679         writel(val, pctrl->regs + g->intr_cfg_reg);
 680
 681         set_bit(d->hwirq, pctrl->enabled_irqs);
 682
 683         spin_unlock_irqrestore(&pctrl->lock, flags);
 684 }
 685
 686 static void msm_gpio_irq_ack(struct irq_data *d)
 687 {
 688         const struct msm_pingroup *g;
 689         struct msm_pinctrl *pctrl;
 690         unsigned long flags;
 691         u32 val;
 692
 693         pctrl = irq_data_get_irq_chip_data(d);
 694         g = &pctrl->soc->groups[d->hwirq];
 695         if (WARN_ON(g->intr_status_reg < 0))
 696                 return;
 697
 698         spin_lock_irqsave(&pctrl->lock, flags);
 699
 700         val = readl(pctrl->regs + g->intr_status_reg);
 701         val &= ~BIT(g->intr_status_bit);
 702         writel(val, pctrl->regs + g->intr_status_reg);
 703
 704         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 705                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 706
 707         spin_unlock_irqrestore(&pctrl->lock, flags);
 708 }
 709
 710 #define INTR_TARGET_PROC_APPS    4
 711
 712 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 713 {
 714         const struct msm_pingroup *g;
 715         struct msm_pinctrl *pctrl;
 716         unsigned long flags;
 717         u32 val;
 718
 719         pctrl = irq_data_get_irq_chip_data(d);
 720         g = &pctrl->soc->groups[d->hwirq];
 721         if (WARN_ON(g->intr_cfg_reg < 0))
 722                 return -EINVAL;
 723
 724         spin_lock_irqsave(&pctrl->lock, flags);
 725
 726         /*
 727          * For hw without possibility of detecting both edges
 728          */
 729         if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
 730                 set_bit(d->hwirq, pctrl->dual_edge_irqs);
 731         else
 732                 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 733
 734         /* Route interrupts to application cpu */
 735         val = readl(pctrl->regs + g->intr_target_reg);
 736         val &= ~(7 << g->intr_target_bit);
 737         val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
 738         writel(val, pctrl->regs + g->intr_target_reg);
 739
 740         /* Update configuration for gpio.
 741          * RAW_STATUS_EN is left on for all gpio irqs. Due to the
 742          * internal circuitry of TLMM, toggling the RAW_STATUS
 743          * could cause the INTR_STATUS to be set for EDGE interrupts.
 744          */
 745         val = readl(pctrl->regs + g->intr_cfg_reg);
 746         val |= BIT(g->intr_raw_status_bit);
 747         if (g->intr_detection_width == 2) {
 748                 val &= ~(3 << g->intr_detection_bit);
 749                 val &= ~(1 << g->intr_polarity_bit);
 750                 switch (type) {
 751                 case IRQ_TYPE_EDGE_RISING:
 752                         val |= 1 << g->intr_detection_bit;
 753                         val |= BIT(g->intr_polarity_bit);
 754                         break;
 755                 case IRQ_TYPE_EDGE_FALLING:
 756                         val |= 2 << g->intr_detection_bit;
 757                         val |= BIT(g->intr_polarity_bit);
 758                         break;
 759                 case IRQ_TYPE_EDGE_BOTH:
 760                         val |= 3 << g->intr_detection_bit;
 761                         val |= BIT(g->intr_polarity_bit);
 762                         break;
 763                 case IRQ_TYPE_LEVEL_LOW:
 764                         break;
 765                 case IRQ_TYPE_LEVEL_HIGH:
 766                         val |= BIT(g->intr_polarity_bit);
 767                         break;
 768                 }
 769         } else if (g->intr_detection_width == 1) {
 770                 val &= ~(1 << g->intr_detection_bit);
 771                 val &= ~(1 << g->intr_polarity_bit);
 772                 switch (type) {
 773                 case IRQ_TYPE_EDGE_RISING:
 774                         val |= BIT(g->intr_detection_bit);
 775                         val |= BIT(g->intr_polarity_bit);
 776                         break;
 777                 case IRQ_TYPE_EDGE_FALLING:
 778                         val |= BIT(g->intr_detection_bit);
 779                         break;
 780                 case IRQ_TYPE_EDGE_BOTH:
 781                         val |= BIT(g->intr_detection_bit);
 782                         break;
 783                 case IRQ_TYPE_LEVEL_LOW:
 784                         break;
 785                 case IRQ_TYPE_LEVEL_HIGH:
 786                         val |= BIT(g->intr_polarity_bit);
 787                         break;
 788                 }
 789         } else {
 790                 BUG();
 791         }
 792         writel(val, pctrl->regs + g->intr_cfg_reg);
 793
 794         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 795                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 796
 797         spin_unlock_irqrestore(&pctrl->lock, flags);
 798
 799         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 800                 __irq_set_handler_locked(d->irq, handle_level_irq);
 801         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 802                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 803
 804         return 0;
 805 }
 806
 807 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 808 {
 809         struct msm_pinctrl *pctrl;
 810         unsigned long flags;
 811
 812         pctrl = irq_data_get_irq_chip_data(d);
 813
 814         spin_lock_irqsave(&pctrl->lock, flags);
 815
 816         irq_set_irq_wake(pctrl->irq, on);
 817
 818         spin_unlock_irqrestore(&pctrl->lock, flags);
 819
 820         return 0;
 821 }
 822
 823 static unsigned int msm_gpio_irq_startup(struct irq_data *d)
 824 {
 825         struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
 826
 827         if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) {
 828                 dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n",
 829                         d->hwirq);
 830         }
 831         msm_gpio_irq_unmask(d);
 832         return 0;
 833 }
 834
 835 static void msm_gpio_irq_shutdown(struct irq_data *d)
 836 {
 837         struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
 838
 839         msm_gpio_irq_mask(d);
 840         gpio_unlock_as_irq(&pctrl->chip, d->hwirq);
 841 }
 842
 843 static struct irq_chip msm_gpio_irq_chip = {
 844         .name           = "msmgpio",
 845         .irq_mask       = msm_gpio_irq_mask,
 846         .irq_unmask     = msm_gpio_irq_unmask,
 847         .irq_ack        = msm_gpio_irq_ack,
 848         .irq_set_type   = msm_gpio_irq_set_type,
 849         .irq_set_wake   = msm_gpio_irq_set_wake,
 850         .irq_startup    = msm_gpio_irq_startup,
 851         .irq_shutdown   = msm_gpio_irq_shutdown,
 852 };
 853
 854 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 855 {
 856         const struct msm_pingroup *g;
 857         struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc);
 858         struct irq_chip *chip = irq_get_chip(irq);
 859         int irq_pin;
 860         int handled = 0;
 861         u32 val;
 862         int i;
 863
 864         chained_irq_enter(chip, desc);
 865
 866         /*
 867          * Each pin has it's own IRQ status register, so use
 868          * enabled_irq bitmap to limit the number of reads.
 869          */
 870         for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
 871                 g = &pctrl->soc->groups[i];
 872                 val = readl(pctrl->regs + g->intr_status_reg);
 873                 if (val & BIT(g->intr_status_bit)) {
 874                         irq_pin = irq_find_mapping(pctrl->domain, i);
 875                         generic_handle_irq(irq_pin);
 876                         handled++;
 877                 }
 878         }
 879
 880         /* No interrupts were flagged */
 881         if (handled == 0)
 882                 handle_bad_irq(irq, desc);
 883
 884         chained_irq_exit(chip, desc);
 885 }
 886
 887 /*
 888  * This lock class tells lockdep that GPIO irqs are in a different
 889  * category than their parents, so it won't report false recursion.
 890  */
 891 static struct lock_class_key gpio_lock_class;
 892
 893 static int msm_gpio_init(struct msm_pinctrl *pctrl)
 894 {
 895         struct gpio_chip *chip;
 896         int irq;
 897         int ret;
 898         int i;
 899         int r;
 900         unsigned ngpio = pctrl->soc->ngpios;
 901
 902         if (WARN_ON(ngpio > MAX_NR_GPIO))
 903                 return -EINVAL;
 904
 905         chip = &pctrl->chip;
 906         chip->base = 0;
 907         chip->ngpio = ngpio;
 908         chip->label = dev_name(pctrl->dev);
 909         chip->dev = pctrl->dev;
 910         chip->owner = THIS_MODULE;
 911         chip->of_node = pctrl->dev->of_node;
 912
 913         ret = gpiochip_add(&pctrl->chip);
 914         if (ret) {
 915                 dev_err(pctrl->dev, "Failed register gpiochip\n");
 916                 return ret;
 917         }
 918
 919         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
 920         if (ret) {
 921                 dev_err(pctrl->dev, "Failed to add pin range\n");
 922                 return ret;
 923         }
 924
 925         pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio,
 926                                               &irq_domain_simple_ops, NULL);
 927         if (!pctrl->domain) {
 928                 dev_err(pctrl->dev, "Failed to register irq domain\n");
 929                 r = gpiochip_remove(&pctrl->chip);
 930                 return -ENOSYS;
 931         }
 932
 933         for (i = 0; i < chip->ngpio; i++) {
 934                 irq = irq_create_mapping(pctrl->domain, i);
 935                 irq_set_lockdep_class(irq, &gpio_lock_class);
 936                 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq);
 937                 irq_set_chip_data(irq, pctrl);
 938         }
 939
 940         irq_set_handler_data(pctrl->irq, pctrl);
 941         irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler);
 942
 943         return 0;
 944 }
 945
 946 int msm_pinctrl_probe(struct platform_device *pdev,
 947                       const struct msm_pinctrl_soc_data *soc_data)
 948 {
 949         struct msm_pinctrl *pctrl;
 950         struct resource *res;
 951         int ret;
 952
 953         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 954         if (!pctrl) {
 955                 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
 956                 return -ENOMEM;
 957         }
 958         pctrl->dev = &pdev->dev;
 959         pctrl->soc = soc_data;
 960         pctrl->chip = msm_gpio_template;
 961
 962         spin_lock_init(&pctrl->lock);
 963
 964         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 965         pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
 966         if (IS_ERR(pctrl->regs))
 967                 return PTR_ERR(pctrl->regs);
 968
 969         pctrl->irq = platform_get_irq(pdev, 0);
 970         if (pctrl->irq < 0) {
 971                 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
 972                 return pctrl->irq;
 973         }
 974
 975         msm_pinctrl_desc.name = dev_name(&pdev->dev);
 976         msm_pinctrl_desc.pins = pctrl->soc->pins;
 977         msm_pinctrl_desc.npins = pctrl->soc->npins;
 978         pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
 979         if (!pctrl->pctrl) {
 980                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 981                 return -ENODEV;
 982         }
 983
 984         ret = msm_gpio_init(pctrl);
 985         if (ret) {
 986                 pinctrl_unregister(pctrl->pctrl);
 987                 return ret;
 988         }
 989
 990         platform_set_drvdata(pdev, pctrl);
 991
 992         dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
 993
 994         return 0;
 995 }
 996 EXPORT_SYMBOL(msm_pinctrl_probe);
 997
 998 int msm_pinctrl_remove(struct platform_device *pdev)
 999 {
1000         struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1001         int ret;
1002
1003         ret = gpiochip_remove(&pctrl->chip);
1004         if (ret) {
1005                 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
1006                 return ret;
1007         }
1008
1009         irq_set_chained_handler(pctrl->irq, NULL);
1010         irq_domain_remove(pctrl->domain);
1011         pinctrl_unregister(pctrl->pctrl);
1012
1013         return 0;
1014 }
1015 EXPORT_SYMBOL(msm_pinctrl_remove);
1016