2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/err.h>
17 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/slab.h>
26 #include <linux/gpio.h>
27 #include <linux/interrupt.h>
28 #include <linux/spinlock.h>
32 #include "pinctrl-msm.h"
33 #include "pinctrl-utils.h"
35 #define MAX_NR_GPIO 300
38 * struct msm_pinctrl - state for a pinctrl-msm device
39 * @dev: device handle.
40 * @pctrl: pinctrl handle.
41 * @chip: gpiochip handle.
42 * @irq: parent irq for the TLMM irq_chip.
43 * @lock: Spinlock to protect register resources as well
44 * as msm_pinctrl data structures.
45 * @enabled_irqs: Bitmap of currently enabled irqs.
46 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
48 * @soc; Reference to soc_data of platform specific data.
49 * @regs: Base address for the TLMM register map.
53 struct pinctrl_dev *pctrl;
54 struct gpio_chip chip;
59 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
60 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
62 const struct msm_pinctrl_soc_data *soc;
66 static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc)
68 return container_of(gc, struct msm_pinctrl, chip);
71 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
73 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
75 return pctrl->soc->ngroups;
78 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
81 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
83 return pctrl->soc->groups[group].name;
86 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
88 const unsigned **pins,
91 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
93 *pins = pctrl->soc->groups[group].pins;
94 *num_pins = pctrl->soc->groups[group].npins;
98 static const struct pinctrl_ops msm_pinctrl_ops = {
99 .get_groups_count = msm_get_groups_count,
100 .get_group_name = msm_get_group_name,
101 .get_group_pins = msm_get_group_pins,
102 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
103 .dt_free_map = pinctrl_utils_dt_free_map,
106 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
108 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
110 return pctrl->soc->nfunctions;
113 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
116 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
118 return pctrl->soc->functions[function].name;
121 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
123 const char * const **groups,
124 unsigned * const num_groups)
126 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
128 *groups = pctrl->soc->functions[function].groups;
129 *num_groups = pctrl->soc->functions[function].ngroups;
133 static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
137 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
138 const struct msm_pingroup *g;
143 g = &pctrl->soc->groups[group];
145 if (WARN_ON(g->mux_bit < 0))
148 for (i = 0; i < g->nfuncs; i++) {
149 if (g->funcs[i] == function)
153 if (WARN_ON(i == g->nfuncs))
156 spin_lock_irqsave(&pctrl->lock, flags);
158 val = readl(pctrl->regs + g->ctl_reg);
159 val &= ~(0x7 << g->mux_bit);
160 val |= i << g->mux_bit;
161 writel(val, pctrl->regs + g->ctl_reg);
163 spin_unlock_irqrestore(&pctrl->lock, flags);
168 static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
172 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
173 const struct msm_pingroup *g;
177 g = &pctrl->soc->groups[group];
179 if (WARN_ON(g->mux_bit < 0))
182 spin_lock_irqsave(&pctrl->lock, flags);
184 /* Clear the mux bits to select gpio mode */
185 val = readl(pctrl->regs + g->ctl_reg);
186 val &= ~(0x7 << g->mux_bit);
187 writel(val, pctrl->regs + g->ctl_reg);
189 spin_unlock_irqrestore(&pctrl->lock, flags);
192 static const struct pinmux_ops msm_pinmux_ops = {
193 .get_functions_count = msm_get_functions_count,
194 .get_function_name = msm_get_function_name,
195 .get_function_groups = msm_get_function_groups,
196 .enable = msm_pinmux_enable,
197 .disable = msm_pinmux_disable,
200 static int msm_config_reg(struct msm_pinctrl *pctrl,
201 const struct msm_pingroup *g,
207 case PIN_CONFIG_BIAS_DISABLE:
208 case PIN_CONFIG_BIAS_PULL_DOWN:
209 case PIN_CONFIG_BIAS_PULL_UP:
213 case PIN_CONFIG_DRIVE_STRENGTH:
217 case PIN_CONFIG_OUTPUT:
222 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
229 static int msm_config_get(struct pinctrl_dev *pctldev,
231 unsigned long *config)
233 dev_err(pctldev->dev, "pin_config_set op not supported\n");
237 static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
238 unsigned long *configs, unsigned num_configs)
240 dev_err(pctldev->dev, "pin_config_set op not supported\n");
244 #define MSM_NO_PULL 0
245 #define MSM_PULL_DOWN 1
246 #define MSM_PULL_UP 3
248 static unsigned msm_regval_to_drive(u32 val)
250 return (val + 1) * 2;
253 static int msm_config_group_get(struct pinctrl_dev *pctldev,
255 unsigned long *config)
257 const struct msm_pingroup *g;
258 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
259 unsigned param = pinconf_to_config_param(*config);
266 g = &pctrl->soc->groups[group];
268 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
272 val = readl(pctrl->regs + g->ctl_reg);
273 arg = (val >> bit) & mask;
275 /* Convert register value to pinconf value */
277 case PIN_CONFIG_BIAS_DISABLE:
278 arg = arg == MSM_NO_PULL;
280 case PIN_CONFIG_BIAS_PULL_DOWN:
281 arg = arg == MSM_PULL_DOWN;
283 case PIN_CONFIG_BIAS_PULL_UP:
284 arg = arg == MSM_PULL_UP;
286 case PIN_CONFIG_DRIVE_STRENGTH:
287 arg = msm_regval_to_drive(arg);
289 case PIN_CONFIG_OUTPUT:
290 /* Pin is not output */
294 val = readl(pctrl->regs + g->io_reg);
295 arg = !!(val & BIT(g->in_bit));
298 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
303 *config = pinconf_to_config_packed(param, arg);
308 static int msm_config_group_set(struct pinctrl_dev *pctldev,
310 unsigned long *configs,
311 unsigned num_configs)
313 const struct msm_pingroup *g;
314 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
324 g = &pctrl->soc->groups[group];
326 for (i = 0; i < num_configs; i++) {
327 param = pinconf_to_config_param(configs[i]);
328 arg = pinconf_to_config_argument(configs[i]);
330 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
334 /* Convert pinconf values to register values */
336 case PIN_CONFIG_BIAS_DISABLE:
339 case PIN_CONFIG_BIAS_PULL_DOWN:
342 case PIN_CONFIG_BIAS_PULL_UP:
345 case PIN_CONFIG_DRIVE_STRENGTH:
346 /* Check for invalid values */
347 if (arg > 16 || arg < 2 || (arg % 2) != 0)
352 case PIN_CONFIG_OUTPUT:
353 /* set output value */
354 spin_lock_irqsave(&pctrl->lock, flags);
355 val = readl(pctrl->regs + g->io_reg);
357 val |= BIT(g->out_bit);
359 val &= ~BIT(g->out_bit);
360 writel(val, pctrl->regs + g->io_reg);
361 spin_unlock_irqrestore(&pctrl->lock, flags);
367 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
372 /* Range-check user-supplied value */
374 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
378 spin_lock_irqsave(&pctrl->lock, flags);
379 val = readl(pctrl->regs + g->ctl_reg);
380 val &= ~(mask << bit);
382 writel(val, pctrl->regs + g->ctl_reg);
383 spin_unlock_irqrestore(&pctrl->lock, flags);
389 static const struct pinconf_ops msm_pinconf_ops = {
390 .pin_config_get = msm_config_get,
391 .pin_config_set = msm_config_set,
392 .pin_config_group_get = msm_config_group_get,
393 .pin_config_group_set = msm_config_group_set,
396 static struct pinctrl_desc msm_pinctrl_desc = {
397 .pctlops = &msm_pinctrl_ops,
398 .pmxops = &msm_pinmux_ops,
399 .confops = &msm_pinconf_ops,
400 .owner = THIS_MODULE,
403 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
405 const struct msm_pingroup *g;
406 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
410 g = &pctrl->soc->groups[offset];
412 spin_lock_irqsave(&pctrl->lock, flags);
414 val = readl(pctrl->regs + g->ctl_reg);
415 val &= ~BIT(g->oe_bit);
416 writel(val, pctrl->regs + g->ctl_reg);
418 spin_unlock_irqrestore(&pctrl->lock, flags);
423 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
425 const struct msm_pingroup *g;
426 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
430 g = &pctrl->soc->groups[offset];
432 spin_lock_irqsave(&pctrl->lock, flags);
434 val = readl(pctrl->regs + g->io_reg);
436 val |= BIT(g->out_bit);
438 val &= ~BIT(g->out_bit);
439 writel(val, pctrl->regs + g->io_reg);
441 val = readl(pctrl->regs + g->ctl_reg);
442 val |= BIT(g->oe_bit);
443 writel(val, pctrl->regs + g->ctl_reg);
445 spin_unlock_irqrestore(&pctrl->lock, flags);
450 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
452 const struct msm_pingroup *g;
453 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
456 g = &pctrl->soc->groups[offset];
458 val = readl(pctrl->regs + g->io_reg);
459 return !!(val & BIT(g->in_bit));
462 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
464 const struct msm_pingroup *g;
465 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
469 g = &pctrl->soc->groups[offset];
471 spin_lock_irqsave(&pctrl->lock, flags);
473 val = readl(pctrl->regs + g->io_reg);
475 val |= BIT(g->out_bit);
477 val &= ~BIT(g->out_bit);
478 writel(val, pctrl->regs + g->io_reg);
480 spin_unlock_irqrestore(&pctrl->lock, flags);
483 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
485 int gpio = chip->base + offset;
486 return pinctrl_request_gpio(gpio);
489 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
491 int gpio = chip->base + offset;
492 return pinctrl_free_gpio(gpio);
495 #ifdef CONFIG_DEBUG_FS
496 #include <linux/seq_file.h>
498 static void msm_gpio_dbg_show_one(struct seq_file *s,
499 struct pinctrl_dev *pctldev,
500 struct gpio_chip *chip,
504 const struct msm_pingroup *g;
505 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
512 static const char * const pulls[] = {
519 g = &pctrl->soc->groups[offset];
520 ctl_reg = readl(pctrl->regs + g->ctl_reg);
522 is_out = !!(ctl_reg & BIT(g->oe_bit));
523 func = (ctl_reg >> g->mux_bit) & 7;
524 drive = (ctl_reg >> g->drv_bit) & 7;
525 pull = (ctl_reg >> g->pull_bit) & 3;
527 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
528 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
529 seq_printf(s, " %s", pulls[pull]);
532 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
534 unsigned gpio = chip->base;
537 for (i = 0; i < chip->ngpio; i++, gpio++) {
538 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
544 #define msm_gpio_dbg_show NULL
547 static struct gpio_chip msm_gpio_template = {
548 .direction_input = msm_gpio_direction_input,
549 .direction_output = msm_gpio_direction_output,
552 .request = msm_gpio_request,
553 .free = msm_gpio_free,
554 .dbg_show = msm_gpio_dbg_show,
557 /* For dual-edge interrupts in software, since some hardware has no
560 * At appropriate moments, this function may be called to flip the polarity
561 * settings of both-edge irq lines to try and catch the next edge.
563 * The attempt is considered successful if:
564 * - the status bit goes high, indicating that an edge was caught, or
565 * - the input value of the gpio doesn't change during the attempt.
566 * If the value changes twice during the process, that would cause the first
567 * test to fail but would force the second, as two opposite
568 * transitions would cause a detection no matter the polarity setting.
570 * The do-loop tries to sledge-hammer closed the timing hole between
571 * the initial value-read and the polarity-write - if the line value changes
572 * during that window, an interrupt is lost, the new polarity setting is
573 * incorrect, and the first success test will fail, causing a retry.
575 * Algorithm comes from Google's msmgpio driver.
577 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
578 const struct msm_pingroup *g,
581 int loop_limit = 100;
582 unsigned val, val2, intstat;
586 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
588 pol = readl(pctrl->regs + g->intr_cfg_reg);
589 pol ^= BIT(g->intr_polarity_bit);
590 writel(pol, pctrl->regs + g->intr_cfg_reg);
592 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
593 intstat = readl(pctrl->regs + g->intr_status_reg);
594 if (intstat || (val == val2))
596 } while (loop_limit-- > 0);
597 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
601 static void msm_gpio_irq_mask(struct irq_data *d)
603 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
604 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
605 const struct msm_pingroup *g;
609 g = &pctrl->soc->groups[d->hwirq];
611 spin_lock_irqsave(&pctrl->lock, flags);
613 val = readl(pctrl->regs + g->intr_cfg_reg);
614 val &= ~BIT(g->intr_enable_bit);
615 writel(val, pctrl->regs + g->intr_cfg_reg);
617 clear_bit(d->hwirq, pctrl->enabled_irqs);
619 spin_unlock_irqrestore(&pctrl->lock, flags);
622 static void msm_gpio_irq_unmask(struct irq_data *d)
624 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
625 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
626 const struct msm_pingroup *g;
630 g = &pctrl->soc->groups[d->hwirq];
632 spin_lock_irqsave(&pctrl->lock, flags);
634 val = readl(pctrl->regs + g->intr_status_reg);
635 val &= ~BIT(g->intr_status_bit);
636 writel(val, pctrl->regs + g->intr_status_reg);
638 val = readl(pctrl->regs + g->intr_cfg_reg);
639 val |= BIT(g->intr_enable_bit);
640 writel(val, pctrl->regs + g->intr_cfg_reg);
642 set_bit(d->hwirq, pctrl->enabled_irqs);
644 spin_unlock_irqrestore(&pctrl->lock, flags);
647 static void msm_gpio_irq_ack(struct irq_data *d)
649 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
650 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
651 const struct msm_pingroup *g;
655 g = &pctrl->soc->groups[d->hwirq];
657 spin_lock_irqsave(&pctrl->lock, flags);
659 val = readl(pctrl->regs + g->intr_status_reg);
660 if (g->intr_ack_high)
661 val |= BIT(g->intr_status_bit);
663 val &= ~BIT(g->intr_status_bit);
664 writel(val, pctrl->regs + g->intr_status_reg);
666 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
667 msm_gpio_update_dual_edge_pos(pctrl, g, d);
669 spin_unlock_irqrestore(&pctrl->lock, flags);
672 #define INTR_TARGET_PROC_APPS 4
674 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
676 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
677 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
678 const struct msm_pingroup *g;
682 g = &pctrl->soc->groups[d->hwirq];
684 spin_lock_irqsave(&pctrl->lock, flags);
687 * For hw without possibility of detecting both edges
689 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
690 set_bit(d->hwirq, pctrl->dual_edge_irqs);
692 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
694 /* Route interrupts to application cpu */
695 val = readl(pctrl->regs + g->intr_target_reg);
696 val &= ~(7 << g->intr_target_bit);
697 val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
698 writel(val, pctrl->regs + g->intr_target_reg);
700 /* Update configuration for gpio.
701 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
702 * internal circuitry of TLMM, toggling the RAW_STATUS
703 * could cause the INTR_STATUS to be set for EDGE interrupts.
705 val = readl(pctrl->regs + g->intr_cfg_reg);
706 val |= BIT(g->intr_raw_status_bit);
707 if (g->intr_detection_width == 2) {
708 val &= ~(3 << g->intr_detection_bit);
709 val &= ~(1 << g->intr_polarity_bit);
711 case IRQ_TYPE_EDGE_RISING:
712 val |= 1 << g->intr_detection_bit;
713 val |= BIT(g->intr_polarity_bit);
715 case IRQ_TYPE_EDGE_FALLING:
716 val |= 2 << g->intr_detection_bit;
717 val |= BIT(g->intr_polarity_bit);
719 case IRQ_TYPE_EDGE_BOTH:
720 val |= 3 << g->intr_detection_bit;
721 val |= BIT(g->intr_polarity_bit);
723 case IRQ_TYPE_LEVEL_LOW:
725 case IRQ_TYPE_LEVEL_HIGH:
726 val |= BIT(g->intr_polarity_bit);
729 } else if (g->intr_detection_width == 1) {
730 val &= ~(1 << g->intr_detection_bit);
731 val &= ~(1 << g->intr_polarity_bit);
733 case IRQ_TYPE_EDGE_RISING:
734 val |= BIT(g->intr_detection_bit);
735 val |= BIT(g->intr_polarity_bit);
737 case IRQ_TYPE_EDGE_FALLING:
738 val |= BIT(g->intr_detection_bit);
740 case IRQ_TYPE_EDGE_BOTH:
741 val |= BIT(g->intr_detection_bit);
742 val |= BIT(g->intr_polarity_bit);
744 case IRQ_TYPE_LEVEL_LOW:
746 case IRQ_TYPE_LEVEL_HIGH:
747 val |= BIT(g->intr_polarity_bit);
753 writel(val, pctrl->regs + g->intr_cfg_reg);
755 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
756 msm_gpio_update_dual_edge_pos(pctrl, g, d);
758 spin_unlock_irqrestore(&pctrl->lock, flags);
760 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
761 __irq_set_handler_locked(d->irq, handle_level_irq);
762 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
763 __irq_set_handler_locked(d->irq, handle_edge_irq);
768 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
770 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
771 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
774 spin_lock_irqsave(&pctrl->lock, flags);
776 irq_set_irq_wake(pctrl->irq, on);
778 spin_unlock_irqrestore(&pctrl->lock, flags);
783 static struct irq_chip msm_gpio_irq_chip = {
785 .irq_mask = msm_gpio_irq_mask,
786 .irq_unmask = msm_gpio_irq_unmask,
787 .irq_ack = msm_gpio_irq_ack,
788 .irq_set_type = msm_gpio_irq_set_type,
789 .irq_set_wake = msm_gpio_irq_set_wake,
792 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
794 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
795 const struct msm_pingroup *g;
796 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
797 struct irq_chip *chip = irq_get_chip(irq);
803 chained_irq_enter(chip, desc);
806 * Each pin has it's own IRQ status register, so use
807 * enabled_irq bitmap to limit the number of reads.
809 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
810 g = &pctrl->soc->groups[i];
811 val = readl(pctrl->regs + g->intr_status_reg);
812 if (val & BIT(g->intr_status_bit)) {
813 irq_pin = irq_find_mapping(gc->irqdomain, i);
814 generic_handle_irq(irq_pin);
819 /* No interrupts were flagged */
821 handle_bad_irq(irq, desc);
823 chained_irq_exit(chip, desc);
826 static int msm_gpio_init(struct msm_pinctrl *pctrl)
828 struct gpio_chip *chip;
830 unsigned ngpio = pctrl->soc->ngpios;
832 if (WARN_ON(ngpio > MAX_NR_GPIO))
838 chip->label = dev_name(pctrl->dev);
839 chip->dev = pctrl->dev;
840 chip->owner = THIS_MODULE;
841 chip->of_node = pctrl->dev->of_node;
843 ret = gpiochip_add(&pctrl->chip);
845 dev_err(pctrl->dev, "Failed register gpiochip\n");
849 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
851 dev_err(pctrl->dev, "Failed to add pin range\n");
855 ret = gpiochip_irqchip_add(chip,
861 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
865 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
866 msm_gpio_irq_handler);
871 int msm_pinctrl_probe(struct platform_device *pdev,
872 const struct msm_pinctrl_soc_data *soc_data)
874 struct msm_pinctrl *pctrl;
875 struct resource *res;
878 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
880 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
883 pctrl->dev = &pdev->dev;
884 pctrl->soc = soc_data;
885 pctrl->chip = msm_gpio_template;
887 spin_lock_init(&pctrl->lock);
889 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
890 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
891 if (IS_ERR(pctrl->regs))
892 return PTR_ERR(pctrl->regs);
894 pctrl->irq = platform_get_irq(pdev, 0);
895 if (pctrl->irq < 0) {
896 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
900 msm_pinctrl_desc.name = dev_name(&pdev->dev);
901 msm_pinctrl_desc.pins = pctrl->soc->pins;
902 msm_pinctrl_desc.npins = pctrl->soc->npins;
903 pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
905 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
909 ret = msm_gpio_init(pctrl);
911 pinctrl_unregister(pctrl->pctrl);
915 platform_set_drvdata(pdev, pctrl);
917 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
921 EXPORT_SYMBOL(msm_pinctrl_probe);
923 int msm_pinctrl_remove(struct platform_device *pdev)
925 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
928 ret = gpiochip_remove(&pctrl->chip);
930 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
934 pinctrl_unregister(pctrl->pctrl);
938 EXPORT_SYMBOL(msm_pinctrl_remove);