2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/slab.h>
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 /* Since we request GPIOs from ourself */
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/platform_data/pinctrl-nomadik.h>
35 #include <asm/mach/irq.h>
37 #include "pinctrl-nomadik.h"
40 * The GPIO module in the Nomadik family of Systems-on-Chip is an
41 * AMBA device, managing 32 pins and alternate functions. The logic block
42 * is currently used in the Nomadik and ux500.
44 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
47 struct nmk_gpio_chip {
48 struct gpio_chip chip;
49 struct irq_domain *domain;
53 unsigned int parent_irq;
54 int secondary_parent_irq;
55 u32 (*get_secondary_status)(unsigned int bank);
56 void (*set_ioforce)(bool enable);
59 /* Keep track of configured edges */
72 * struct nmk_pinctrl - state container for the Nomadik pin controller
73 * @dev: containing device pointer
74 * @pctl: corresponding pin controller device
75 * @soc: SoC data for this specific chip
76 * @prcm_base: PRCM register range virtual base
80 struct pinctrl_dev *pctl;
81 const struct nmk_pinctrl_soc_data *soc;
82 void __iomem *prcm_base;
85 static struct nmk_gpio_chip *
86 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
88 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
90 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
92 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
93 unsigned offset, int gpio_mode)
95 u32 bit = 1 << offset;
98 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
99 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
100 if (gpio_mode & NMK_GPIO_ALT_A)
102 if (gpio_mode & NMK_GPIO_ALT_B)
104 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
105 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
108 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
109 unsigned offset, enum nmk_gpio_slpm mode)
111 u32 bit = 1 << offset;
114 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
115 if (mode == NMK_GPIO_SLPM_NOCHANGE)
119 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
122 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
123 unsigned offset, enum nmk_gpio_pull pull)
125 u32 bit = 1 << offset;
128 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
129 if (pull == NMK_GPIO_PULL_NONE) {
131 nmk_chip->pull_up &= ~bit;
136 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
138 if (pull == NMK_GPIO_PULL_UP) {
139 nmk_chip->pull_up |= bit;
140 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
141 } else if (pull == NMK_GPIO_PULL_DOWN) {
142 nmk_chip->pull_up &= ~bit;
143 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
147 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
148 unsigned offset, bool lowemi)
150 u32 bit = BIT(offset);
151 bool enabled = nmk_chip->lowemi & bit;
153 if (lowemi == enabled)
157 nmk_chip->lowemi |= bit;
159 nmk_chip->lowemi &= ~bit;
161 writel_relaxed(nmk_chip->lowemi,
162 nmk_chip->addr + NMK_GPIO_LOWEMI);
165 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
168 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
171 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
172 unsigned offset, int val)
175 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
177 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
180 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
181 unsigned offset, int val)
183 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
184 __nmk_gpio_set_output(nmk_chip, offset, val);
187 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
188 unsigned offset, int gpio_mode,
191 u32 rwimsc = nmk_chip->rwimsc;
192 u32 fwimsc = nmk_chip->fwimsc;
194 if (glitch && nmk_chip->set_ioforce) {
195 u32 bit = BIT(offset);
197 /* Prevent spurious wakeups */
198 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
199 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
201 nmk_chip->set_ioforce(true);
204 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
206 if (glitch && nmk_chip->set_ioforce) {
207 nmk_chip->set_ioforce(false);
209 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
210 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
215 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
217 u32 falling = nmk_chip->fimsc & BIT(offset);
218 u32 rising = nmk_chip->rimsc & BIT(offset);
219 int gpio = nmk_chip->chip.base + offset;
220 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
221 struct irq_data *d = irq_get_irq_data(irq);
223 if (!rising && !falling)
226 if (!d || !irqd_irq_disabled(d))
230 nmk_chip->rimsc &= ~BIT(offset);
231 writel_relaxed(nmk_chip->rimsc,
232 nmk_chip->addr + NMK_GPIO_RIMSC);
236 nmk_chip->fimsc &= ~BIT(offset);
237 writel_relaxed(nmk_chip->fimsc,
238 nmk_chip->addr + NMK_GPIO_FIMSC);
241 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
244 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
249 val = ((val & ~mask) | (value & mask));
253 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
254 unsigned offset, unsigned alt_num)
260 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
261 const u16 *gpiocr_regs;
263 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
264 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
269 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
270 if (npct->soc->altcx_pins[i].pin == offset)
273 if (i == npct->soc->npins_altcx) {
274 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
279 pin_desc = npct->soc->altcx_pins + i;
280 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
283 * If alt_num is NULL, just clear current ALTCx selection
284 * to make sure we come back to a pure ALTC selection
287 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
288 if (pin_desc->altcx[i].used == true) {
289 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
290 bit = pin_desc->altcx[i].control_bit;
291 if (readl(npct->prcm_base + reg) & BIT(bit)) {
292 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
294 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
302 alt_index = alt_num - 1;
303 if (pin_desc->altcx[alt_index].used == false) {
305 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
311 * Check if any other ALTCx functions are activated on this pin
312 * and disable it first.
314 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
317 if (pin_desc->altcx[i].used == true) {
318 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
319 bit = pin_desc->altcx[i].control_bit;
320 if (readl(npct->prcm_base + reg) & BIT(bit)) {
321 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
323 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
329 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
330 bit = pin_desc->altcx[alt_index].control_bit;
331 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
332 offset, alt_index+1);
333 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
336 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
337 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
339 static const char *afnames[] = {
340 [NMK_GPIO_ALT_GPIO] = "GPIO",
341 [NMK_GPIO_ALT_A] = "A",
342 [NMK_GPIO_ALT_B] = "B",
343 [NMK_GPIO_ALT_C] = "C"
345 static const char *pullnames[] = {
346 [NMK_GPIO_PULL_NONE] = "none",
347 [NMK_GPIO_PULL_UP] = "up",
348 [NMK_GPIO_PULL_DOWN] = "down",
349 [3] /* illegal */ = "??"
351 static const char *slpmnames[] = {
352 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
353 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
356 int pin = PIN_NUM(cfg);
357 int pull = PIN_PULL(cfg);
358 int af = PIN_ALT(cfg);
359 int slpm = PIN_SLPM(cfg);
360 int output = PIN_DIR(cfg);
361 int val = PIN_VAL(cfg);
362 bool glitch = af == NMK_GPIO_ALT_C;
364 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
365 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
366 output ? "output " : "input",
367 output ? (val ? "high" : "low") : "");
370 int slpm_pull = PIN_SLPM_PULL(cfg);
371 int slpm_output = PIN_SLPM_DIR(cfg);
372 int slpm_val = PIN_SLPM_VAL(cfg);
374 af = NMK_GPIO_ALT_GPIO;
377 * The SLPM_* values are normal values + 1 to allow zero to
378 * mean "same as normal".
381 pull = slpm_pull - 1;
383 output = slpm_output - 1;
387 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
389 slpm_pull ? pullnames[pull] : "same",
390 slpm_output ? (output ? "output" : "input") : "same",
391 slpm_val ? (val ? "high" : "low") : "same");
395 __nmk_gpio_make_output(nmk_chip, offset, val);
397 __nmk_gpio_make_input(nmk_chip, offset);
398 __nmk_gpio_set_pull(nmk_chip, offset, pull);
401 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
404 * If the pin is switching to altfunc, and there was an interrupt
405 * installed on it which has been lazy disabled, actually mask the
406 * interrupt to prevent spurious interrupts that would occur while the
407 * pin is under control of the peripheral. Only SKE does this.
409 if (af != NMK_GPIO_ALT_GPIO)
410 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
413 * If we've backed up the SLPM registers (glitch workaround), modify
414 * the backups since they will be restored.
417 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
418 slpmregs[nmk_chip->bank] |= BIT(offset);
420 slpmregs[nmk_chip->bank] &= ~BIT(offset);
422 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
424 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
428 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
429 * - Save SLPM registers
430 * - Set SLPM=0 for the IOs you want to switch and others to 1
431 * - Configure the GPIO registers for the IOs that are being switched
433 * - Modify the AFLSA/B registers for the IOs that are being switched
435 * - Restore SLPM registers
436 * - Any spurious wake up event during switch sequence to be ignored and
439 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
443 for (i = 0; i < NUM_BANKS; i++) {
444 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
445 unsigned int temp = slpm[i];
450 clk_enable(chip->clk);
452 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
453 writel(temp, chip->addr + NMK_GPIO_SLPC);
457 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
461 for (i = 0; i < NUM_BANKS; i++) {
462 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
467 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
469 clk_disable(chip->clk);
473 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
475 static unsigned int slpm[NUM_BANKS];
481 for (i = 0; i < num; i++) {
482 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
488 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
491 memset(slpm, 0xff, sizeof(slpm));
493 for (i = 0; i < num; i++) {
494 int pin = PIN_NUM(cfgs[i]);
495 int offset = pin % NMK_GPIO_PER_CHIP;
497 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
498 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
501 nmk_gpio_glitch_slpm_init(slpm);
504 for (i = 0; i < num; i++) {
505 struct nmk_gpio_chip *nmk_chip;
506 int pin = PIN_NUM(cfgs[i]);
508 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
514 clk_enable(nmk_chip->clk);
515 spin_lock(&nmk_chip->lock);
516 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
517 cfgs[i], sleep, glitch ? slpm : NULL);
518 spin_unlock(&nmk_chip->lock);
519 clk_disable(nmk_chip->clk);
523 nmk_gpio_glitch_slpm_restore(slpm);
525 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
531 * nmk_config_pin - configure a pin's mux attributes
532 * @cfg: pin confguration
533 * @sleep: Non-zero to apply the sleep mode configuration
534 * Configures a pin's mode (alternate function or GPIO), its pull up status,
535 * and its sleep mode based on the specified configuration. The @cfg is
536 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
537 * are constructed using, and can be further enhanced with, the macros in
538 * <linux/platform_data/pinctrl-nomadik.h>
540 * If a pin's mode is set to GPIO, it is configured as an input to avoid
541 * side-effects. The gpio can be manipulated later using standard GPIO API
544 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
546 return __nmk_config_pins(&cfg, 1, sleep);
548 EXPORT_SYMBOL(nmk_config_pin);
551 * nmk_config_pins - configure several pins at once
552 * @cfgs: array of pin configurations
553 * @num: number of elments in the array
555 * Configures several pins using nmk_config_pin(). Refer to that function for
556 * further information.
558 int nmk_config_pins(pin_cfg_t *cfgs, int num)
560 return __nmk_config_pins(cfgs, num, false);
562 EXPORT_SYMBOL(nmk_config_pins);
564 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
566 return __nmk_config_pins(cfgs, num, true);
568 EXPORT_SYMBOL(nmk_config_pins_sleep);
571 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
573 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
575 * This register is actually in the pinmux layer, not the GPIO block itself.
576 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
577 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
578 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
579 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
580 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
581 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
583 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
584 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
585 * entered) regardless of the altfunction selected. Also wake-up detection is
588 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
589 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
590 * (for altfunction GPIO) or respective on-chip peripherals (for other
591 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
593 * Note that enable_irq_wake() will automatically enable wakeup detection.
595 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
597 struct nmk_gpio_chip *nmk_chip;
600 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
604 clk_enable(nmk_chip->clk);
605 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
606 spin_lock(&nmk_chip->lock);
608 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
610 spin_unlock(&nmk_chip->lock);
611 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
612 clk_disable(nmk_chip->clk);
618 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
620 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
622 * Enables/disables pull up/down on a specified pin. This only takes effect if
623 * the pin is configured as an input (either explicitly or by the alternate
626 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
627 * configured as an input. Otherwise, due to the way the controller registers
628 * work, this function will change the value output on the pin.
630 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
632 struct nmk_gpio_chip *nmk_chip;
635 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
639 clk_enable(nmk_chip->clk);
640 spin_lock_irqsave(&nmk_chip->lock, flags);
641 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
642 spin_unlock_irqrestore(&nmk_chip->lock, flags);
643 clk_disable(nmk_chip->clk);
650 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
652 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
653 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
655 * Sets the mode of the specified pin to one of the alternate functions or
658 int nmk_gpio_set_mode(int gpio, int gpio_mode)
660 struct nmk_gpio_chip *nmk_chip;
663 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
667 clk_enable(nmk_chip->clk);
668 spin_lock_irqsave(&nmk_chip->lock, flags);
669 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
670 spin_unlock_irqrestore(&nmk_chip->lock, flags);
671 clk_disable(nmk_chip->clk);
675 EXPORT_SYMBOL(nmk_gpio_set_mode);
677 static int nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
682 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
683 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
684 const u16 *gpiocr_regs;
686 for (i = 0; i < npct->soc->npins_altcx; i++) {
687 if (npct->soc->altcx_pins[i].pin == gpio)
690 if (i == npct->soc->npins_altcx)
691 return NMK_GPIO_ALT_C;
693 pin_desc = npct->soc->altcx_pins + i;
694 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
695 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
696 if (pin_desc->altcx[i].used == true) {
697 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
698 bit = pin_desc->altcx[i].control_bit;
699 if (readl(npct->prcm_base + reg) & BIT(bit))
700 return NMK_GPIO_ALT_C+i+1;
703 return NMK_GPIO_ALT_C;
706 int nmk_gpio_get_mode(int gpio)
708 struct nmk_gpio_chip *nmk_chip;
709 u32 afunc, bfunc, bit;
711 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
715 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
717 clk_enable(nmk_chip->clk);
719 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
720 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
722 clk_disable(nmk_chip->clk);
724 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
726 EXPORT_SYMBOL(nmk_gpio_get_mode);
730 static inline int nmk_gpio_get_bitmask(int gpio)
732 return 1 << (gpio % NMK_GPIO_PER_CHIP);
735 static void nmk_gpio_irq_ack(struct irq_data *d)
737 struct nmk_gpio_chip *nmk_chip;
739 nmk_chip = irq_data_get_irq_chip_data(d);
743 clk_enable(nmk_chip->clk);
744 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
745 clk_disable(nmk_chip->clk);
748 enum nmk_gpio_irq_type {
753 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
754 int gpio, enum nmk_gpio_irq_type which,
757 u32 bitmask = nmk_gpio_get_bitmask(gpio);
763 if (which == NORMAL) {
764 rimscreg = NMK_GPIO_RIMSC;
765 fimscreg = NMK_GPIO_FIMSC;
766 rimscval = &nmk_chip->rimsc;
767 fimscval = &nmk_chip->fimsc;
769 rimscreg = NMK_GPIO_RWIMSC;
770 fimscreg = NMK_GPIO_FWIMSC;
771 rimscval = &nmk_chip->rwimsc;
772 fimscval = &nmk_chip->fwimsc;
775 /* we must individually set/clear the two edges */
776 if (nmk_chip->edge_rising & bitmask) {
778 *rimscval |= bitmask;
780 *rimscval &= ~bitmask;
781 writel(*rimscval, nmk_chip->addr + rimscreg);
783 if (nmk_chip->edge_falling & bitmask) {
785 *fimscval |= bitmask;
787 *fimscval &= ~bitmask;
788 writel(*fimscval, nmk_chip->addr + fimscreg);
792 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
796 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
797 * disabled, since setting SLPM to 1 increases power consumption, and
798 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
800 if (nmk_chip->sleepmode && on) {
801 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
802 NMK_GPIO_SLPM_WAKEUP_ENABLE);
805 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
808 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
810 struct nmk_gpio_chip *nmk_chip;
814 nmk_chip = irq_data_get_irq_chip_data(d);
815 bitmask = nmk_gpio_get_bitmask(d->hwirq);
819 clk_enable(nmk_chip->clk);
820 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
821 spin_lock(&nmk_chip->lock);
823 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
825 if (!(nmk_chip->real_wake & bitmask))
826 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
828 spin_unlock(&nmk_chip->lock);
829 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
830 clk_disable(nmk_chip->clk);
835 static void nmk_gpio_irq_mask(struct irq_data *d)
837 nmk_gpio_irq_maskunmask(d, false);
840 static void nmk_gpio_irq_unmask(struct irq_data *d)
842 nmk_gpio_irq_maskunmask(d, true);
845 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
847 struct nmk_gpio_chip *nmk_chip;
851 nmk_chip = irq_data_get_irq_chip_data(d);
854 bitmask = nmk_gpio_get_bitmask(d->hwirq);
856 clk_enable(nmk_chip->clk);
857 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
858 spin_lock(&nmk_chip->lock);
860 if (irqd_irq_disabled(d))
861 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
864 nmk_chip->real_wake |= bitmask;
866 nmk_chip->real_wake &= ~bitmask;
868 spin_unlock(&nmk_chip->lock);
869 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
870 clk_disable(nmk_chip->clk);
875 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
877 bool enabled = !irqd_irq_disabled(d);
878 bool wake = irqd_is_wakeup_set(d);
879 struct nmk_gpio_chip *nmk_chip;
883 nmk_chip = irq_data_get_irq_chip_data(d);
884 bitmask = nmk_gpio_get_bitmask(d->hwirq);
887 if (type & IRQ_TYPE_LEVEL_HIGH)
889 if (type & IRQ_TYPE_LEVEL_LOW)
892 clk_enable(nmk_chip->clk);
893 spin_lock_irqsave(&nmk_chip->lock, flags);
896 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
899 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
901 nmk_chip->edge_rising &= ~bitmask;
902 if (type & IRQ_TYPE_EDGE_RISING)
903 nmk_chip->edge_rising |= bitmask;
905 nmk_chip->edge_falling &= ~bitmask;
906 if (type & IRQ_TYPE_EDGE_FALLING)
907 nmk_chip->edge_falling |= bitmask;
910 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
913 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
915 spin_unlock_irqrestore(&nmk_chip->lock, flags);
916 clk_disable(nmk_chip->clk);
921 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
923 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
925 clk_enable(nmk_chip->clk);
926 nmk_gpio_irq_unmask(d);
930 static void nmk_gpio_irq_shutdown(struct irq_data *d)
932 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
934 nmk_gpio_irq_mask(d);
935 clk_disable(nmk_chip->clk);
938 static struct irq_chip nmk_gpio_irq_chip = {
939 .name = "Nomadik-GPIO",
940 .irq_ack = nmk_gpio_irq_ack,
941 .irq_mask = nmk_gpio_irq_mask,
942 .irq_unmask = nmk_gpio_irq_unmask,
943 .irq_set_type = nmk_gpio_irq_set_type,
944 .irq_set_wake = nmk_gpio_irq_set_wake,
945 .irq_startup = nmk_gpio_irq_startup,
946 .irq_shutdown = nmk_gpio_irq_shutdown,
947 .flags = IRQCHIP_MASK_ON_SUSPEND,
950 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
953 struct nmk_gpio_chip *nmk_chip;
954 struct irq_chip *host_chip = irq_get_chip(irq);
956 chained_irq_enter(host_chip, desc);
958 nmk_chip = irq_get_handler_data(irq);
960 int bit = __ffs(status);
962 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
966 chained_irq_exit(host_chip, desc);
969 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
971 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
974 clk_enable(nmk_chip->clk);
975 status = readl(nmk_chip->addr + NMK_GPIO_IS);
976 clk_disable(nmk_chip->clk);
978 __nmk_gpio_irq_handler(irq, desc, status);
981 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
982 struct irq_desc *desc)
984 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
985 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
987 __nmk_gpio_irq_handler(irq, desc, status);
990 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
992 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
993 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
995 if (nmk_chip->secondary_parent_irq >= 0) {
996 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
997 nmk_gpio_secondary_irq_handler);
998 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
1006 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
1009 * Map back to global GPIO space and request muxing, the direction
1010 * parameter does not matter for this controller.
1012 int gpio = chip->base + offset;
1014 return pinctrl_request_gpio(gpio);
1017 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
1019 int gpio = chip->base + offset;
1021 pinctrl_free_gpio(gpio);
1024 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
1026 struct nmk_gpio_chip *nmk_chip =
1027 container_of(chip, struct nmk_gpio_chip, chip);
1029 clk_enable(nmk_chip->clk);
1031 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
1033 clk_disable(nmk_chip->clk);
1038 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
1040 struct nmk_gpio_chip *nmk_chip =
1041 container_of(chip, struct nmk_gpio_chip, chip);
1042 u32 bit = 1 << offset;
1045 clk_enable(nmk_chip->clk);
1047 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
1049 clk_disable(nmk_chip->clk);
1054 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
1057 struct nmk_gpio_chip *nmk_chip =
1058 container_of(chip, struct nmk_gpio_chip, chip);
1060 clk_enable(nmk_chip->clk);
1062 __nmk_gpio_set_output(nmk_chip, offset, val);
1064 clk_disable(nmk_chip->clk);
1067 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
1070 struct nmk_gpio_chip *nmk_chip =
1071 container_of(chip, struct nmk_gpio_chip, chip);
1073 clk_enable(nmk_chip->clk);
1075 __nmk_gpio_make_output(nmk_chip, offset, val);
1077 clk_disable(nmk_chip->clk);
1082 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1084 struct nmk_gpio_chip *nmk_chip =
1085 container_of(chip, struct nmk_gpio_chip, chip);
1087 return irq_create_mapping(nmk_chip->domain, offset);
1090 #ifdef CONFIG_DEBUG_FS
1092 #include <linux/seq_file.h>
1094 static void nmk_gpio_dbg_show_one(struct seq_file *s,
1095 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
1096 unsigned offset, unsigned gpio)
1098 const char *label = gpiochip_is_requested(chip, offset);
1099 struct nmk_gpio_chip *nmk_chip =
1100 container_of(chip, struct nmk_gpio_chip, chip);
1104 u32 bit = 1 << offset;
1105 const char *modes[] = {
1106 [NMK_GPIO_ALT_GPIO] = "gpio",
1107 [NMK_GPIO_ALT_A] = "altA",
1108 [NMK_GPIO_ALT_B] = "altB",
1109 [NMK_GPIO_ALT_C] = "altC",
1110 [NMK_GPIO_ALT_C+1] = "altC1",
1111 [NMK_GPIO_ALT_C+2] = "altC2",
1112 [NMK_GPIO_ALT_C+3] = "altC3",
1113 [NMK_GPIO_ALT_C+4] = "altC4",
1116 clk_enable(nmk_chip->clk);
1117 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1118 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1119 mode = nmk_gpio_get_mode(gpio);
1120 if ((mode == NMK_GPIO_ALT_C) && pctldev)
1121 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1123 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
1124 gpio, label ?: "(none)",
1125 is_out ? "out" : "in ",
1127 ? (chip->get(chip, offset) ? "hi" : "lo")
1129 (mode < 0) ? "unknown" : modes[mode],
1130 pull ? "pull" : "none");
1132 if (label && !is_out) {
1133 int irq = gpio_to_irq(gpio);
1134 struct irq_desc *desc = irq_to_desc(irq);
1136 /* This races with request_irq(), set_irq_type(),
1137 * and set_irq_wake() ... but those are "rare".
1139 if (irq >= 0 && desc->action) {
1141 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1143 if (nmk_chip->edge_rising & bitmask)
1144 trigger = "edge-rising";
1145 else if (nmk_chip->edge_falling & bitmask)
1146 trigger = "edge-falling";
1148 trigger = "edge-undefined";
1150 seq_printf(s, " irq-%d %s%s",
1152 irqd_is_wakeup_set(&desc->irq_data)
1156 clk_disable(nmk_chip->clk);
1159 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1162 unsigned gpio = chip->base;
1164 for (i = 0; i < chip->ngpio; i++, gpio++) {
1165 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1166 seq_printf(s, "\n");
1171 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1172 struct pinctrl_dev *pctldev,
1173 struct gpio_chip *chip,
1174 unsigned offset, unsigned gpio)
1177 #define nmk_gpio_dbg_show NULL
1180 /* This structure is replicated for each GPIO block allocated at probe time */
1181 static struct gpio_chip nmk_gpio_template = {
1182 .request = nmk_gpio_request,
1183 .free = nmk_gpio_free,
1184 .direction_input = nmk_gpio_make_input,
1185 .get = nmk_gpio_get_input,
1186 .direction_output = nmk_gpio_make_output,
1187 .set = nmk_gpio_set_output,
1188 .to_irq = nmk_gpio_to_irq,
1189 .dbg_show = nmk_gpio_dbg_show,
1193 void nmk_gpio_clocks_enable(void)
1197 for (i = 0; i < NUM_BANKS; i++) {
1198 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1203 clk_enable(chip->clk);
1207 void nmk_gpio_clocks_disable(void)
1211 for (i = 0; i < NUM_BANKS; i++) {
1212 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1217 clk_disable(chip->clk);
1222 * Called from the suspend/resume path to only keep the real wakeup interrupts
1223 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1224 * and not the rest of the interrupts which we needed to have as wakeups for
1227 * PM ops are not used since this needs to be done at the end, after all the
1228 * other drivers are done with their suspend callbacks.
1230 void nmk_gpio_wakeups_suspend(void)
1234 for (i = 0; i < NUM_BANKS; i++) {
1235 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1240 clk_enable(chip->clk);
1242 writel(chip->rwimsc & chip->real_wake,
1243 chip->addr + NMK_GPIO_RWIMSC);
1244 writel(chip->fwimsc & chip->real_wake,
1245 chip->addr + NMK_GPIO_FWIMSC);
1247 clk_disable(chip->clk);
1251 void nmk_gpio_wakeups_resume(void)
1255 for (i = 0; i < NUM_BANKS; i++) {
1256 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1261 clk_enable(chip->clk);
1263 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1264 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1266 clk_disable(chip->clk);
1271 * Read the pull up/pull down status.
1272 * A bit set in 'pull_up' means that pull up
1273 * is selected if pull is enabled in PDIS register.
1274 * Note: only pull up/down set via this driver can
1275 * be detected due to HW limitations.
1277 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1279 if (gpio_bank < NUM_BANKS) {
1280 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1285 *pull_up = chip->pull_up;
1289 int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1290 irq_hw_number_t hwirq)
1292 struct nmk_gpio_chip *nmk_chip = d->host_data;
1297 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1298 set_irq_flags(irq, IRQF_VALID);
1299 irq_set_chip_data(irq, nmk_chip);
1300 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1305 const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1306 .map = nmk_gpio_irq_map,
1307 .xlate = irq_domain_xlate_twocell,
1310 static int __devinit nmk_gpio_probe(struct platform_device *dev)
1312 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1313 struct device_node *np = dev->dev.of_node;
1314 struct nmk_gpio_chip *nmk_chip;
1315 struct gpio_chip *chip;
1316 struct resource *res;
1324 if (!pdata && !np) {
1325 dev_err(&dev->dev, "No platform data or device tree found\n");
1330 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1334 if (of_get_property(np, "st,supports-sleepmode", NULL))
1335 pdata->supports_sleepmode = true;
1337 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1338 dev_err(&dev->dev, "gpio-bank property not found\n");
1343 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1344 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1347 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1353 irq = platform_get_irq(dev, 0);
1359 secondary_irq = platform_get_irq(dev, 1);
1360 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1365 base = devm_request_and_ioremap(&dev->dev, res);
1371 clk = devm_clk_get(&dev->dev, NULL);
1378 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1385 * The virt address in nmk_chip->addr is in the nomadik register space,
1386 * so we can simply convert the resource address, without remapping
1388 nmk_chip->bank = dev->id;
1389 nmk_chip->clk = clk;
1390 nmk_chip->addr = base;
1391 nmk_chip->chip = nmk_gpio_template;
1392 nmk_chip->parent_irq = irq;
1393 nmk_chip->secondary_parent_irq = secondary_irq;
1394 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1395 nmk_chip->set_ioforce = pdata->set_ioforce;
1396 nmk_chip->sleepmode = pdata->supports_sleepmode;
1397 spin_lock_init(&nmk_chip->lock);
1399 chip = &nmk_chip->chip;
1400 chip->base = pdata->first_gpio;
1401 chip->ngpio = pdata->num_gpio;
1402 chip->label = pdata->name ?: dev_name(&dev->dev);
1403 chip->dev = &dev->dev;
1404 chip->owner = THIS_MODULE;
1406 clk_enable(nmk_chip->clk);
1407 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1408 clk_disable(nmk_chip->clk);
1410 #ifdef CONFIG_OF_GPIO
1414 ret = gpiochip_add(&nmk_chip->chip);
1418 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1420 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1422 platform_set_drvdata(dev, nmk_chip);
1425 irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio);
1426 nmk_chip->domain = irq_domain_add_simple(np,
1427 NMK_GPIO_PER_CHIP, irq_start,
1428 &nmk_gpio_irq_simple_ops, nmk_chip);
1429 if (!nmk_chip->domain) {
1430 dev_err(&dev->dev, "failed to create irqdomain\n");
1435 nmk_gpio_init_irq(nmk_chip);
1437 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1442 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1443 pdata->first_gpio, pdata->first_gpio+31);
1448 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1450 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1452 return npct->soc->ngroups;
1455 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1458 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1460 return npct->soc->groups[selector].name;
1463 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1464 const unsigned **pins,
1467 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1469 *pins = npct->soc->groups[selector].pins;
1470 *num_pins = npct->soc->groups[selector].npins;
1474 static struct pinctrl_gpio_range *
1475 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1477 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1480 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1481 struct pinctrl_gpio_range *range;
1483 range = &npct->soc->gpio_ranges[i];
1484 if (offset >= range->pin_base &&
1485 offset <= (range->pin_base + range->npins - 1))
1491 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1494 struct pinctrl_gpio_range *range;
1495 struct gpio_chip *chip;
1497 range = nmk_match_gpio_range(pctldev, offset);
1498 if (!range || !range->gc) {
1499 seq_printf(s, "invalid pin offset");
1503 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1506 static struct pinctrl_ops nmk_pinctrl_ops = {
1507 .get_groups_count = nmk_get_groups_cnt,
1508 .get_group_name = nmk_get_group_name,
1509 .get_group_pins = nmk_get_group_pins,
1510 .pin_dbg_show = nmk_pin_dbg_show,
1513 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1515 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1517 return npct->soc->nfunctions;
1520 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1523 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1525 return npct->soc->functions[function].name;
1528 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1530 const char * const **groups,
1531 unsigned * const num_groups)
1533 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1535 *groups = npct->soc->functions[function].groups;
1536 *num_groups = npct->soc->functions[function].ngroups;
1541 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1544 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1545 const struct nmk_pingroup *g;
1546 static unsigned int slpm[NUM_BANKS];
1547 unsigned long flags;
1552 g = &npct->soc->groups[group];
1554 if (g->altsetting < 0)
1557 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1560 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1561 * we may pass through an undesired state. In this case we take
1564 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1565 * - Save SLPM registers (since we have a shadow register in the
1566 * nmk_chip we're using that as backup)
1567 * - Set SLPM=0 for the IOs you want to switch and others to 1
1568 * - Configure the GPIO registers for the IOs that are being switched
1570 * - Modify the AFLSA/B registers for the IOs that are being switched
1572 * - Restore SLPM registers
1573 * - Any spurious wake up event during switch sequence to be ignored
1576 * We REALLY need to save ALL slpm registers, because the external
1577 * IOFORCE will switch *all* ports to their sleepmode setting to as
1578 * to avoid glitches. (Not just one port!)
1580 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1583 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1585 /* Initially don't put any pins to sleep when switching */
1586 memset(slpm, 0xff, sizeof(slpm));
1589 * Then mask the pins that need to be sleeping now when we're
1590 * switching to the ALT C function.
1592 for (i = 0; i < g->npins; i++)
1593 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1594 nmk_gpio_glitch_slpm_init(slpm);
1597 for (i = 0; i < g->npins; i++) {
1598 struct pinctrl_gpio_range *range;
1599 struct nmk_gpio_chip *nmk_chip;
1600 struct gpio_chip *chip;
1603 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1606 "invalid pin offset %d in group %s at index %d\n",
1607 g->pins[i], g->name, i);
1611 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1612 g->pins[i], g->name, i);
1616 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1617 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1619 clk_enable(nmk_chip->clk);
1620 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1622 * If the pin is switching to altfunc, and there was an
1623 * interrupt installed on it which has been lazy disabled,
1624 * actually mask the interrupt to prevent spurious interrupts
1625 * that would occur while the pin is under control of the
1626 * peripheral. Only SKE does this.
1628 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1630 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1631 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1632 clk_disable(nmk_chip->clk);
1635 * Call PRCM GPIOCR config function in case ALTC
1636 * has been selected:
1637 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1639 * - If selection is pure ALTC and previous selection was ALTCx,
1640 * then some bits in PRCM GPIOCR registers must be cleared.
1642 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1643 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1644 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1647 /* When all pins are successfully reconfigured we get here */
1652 nmk_gpio_glitch_slpm_restore(slpm);
1653 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1659 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1660 unsigned function, unsigned group)
1662 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1663 const struct nmk_pingroup *g;
1665 g = &npct->soc->groups[group];
1667 if (g->altsetting < 0)
1670 /* Poke out the mux, set the pin to some default state? */
1671 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1674 int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1675 struct pinctrl_gpio_range *range,
1678 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1679 struct nmk_gpio_chip *nmk_chip;
1680 struct gpio_chip *chip;
1684 dev_err(npct->dev, "invalid range\n");
1688 dev_err(npct->dev, "missing GPIO chip in range\n");
1692 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1694 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1696 clk_enable(nmk_chip->clk);
1697 bit = offset % NMK_GPIO_PER_CHIP;
1698 /* There is no glitch when converting any pin to GPIO */
1699 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1700 clk_disable(nmk_chip->clk);
1705 void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1706 struct pinctrl_gpio_range *range,
1709 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1711 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1712 /* Set the pin to some default state, GPIO is usually default */
1715 static struct pinmux_ops nmk_pinmux_ops = {
1716 .get_functions_count = nmk_pmx_get_funcs_cnt,
1717 .get_function_name = nmk_pmx_get_func_name,
1718 .get_function_groups = nmk_pmx_get_func_groups,
1719 .enable = nmk_pmx_enable,
1720 .disable = nmk_pmx_disable,
1721 .gpio_request_enable = nmk_gpio_request_enable,
1722 .gpio_disable_free = nmk_gpio_disable_free,
1725 int nmk_pin_config_get(struct pinctrl_dev *pctldev,
1727 unsigned long *config)
1729 /* Not implemented */
1733 int nmk_pin_config_set(struct pinctrl_dev *pctldev,
1735 unsigned long config)
1737 static const char *pullnames[] = {
1738 [NMK_GPIO_PULL_NONE] = "none",
1739 [NMK_GPIO_PULL_UP] = "up",
1740 [NMK_GPIO_PULL_DOWN] = "down",
1741 [3] /* illegal */ = "??"
1743 static const char *slpmnames[] = {
1744 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1745 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1747 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1748 struct nmk_gpio_chip *nmk_chip;
1749 struct pinctrl_gpio_range *range;
1750 struct gpio_chip *chip;
1754 * The pin config contains pin number and altfunction fields, here
1755 * we just ignore that part. It's being handled by the framework and
1756 * pinmux callback respectively.
1758 pin_cfg_t cfg = (pin_cfg_t) config;
1759 int pull = PIN_PULL(cfg);
1760 int slpm = PIN_SLPM(cfg);
1761 int output = PIN_DIR(cfg);
1762 int val = PIN_VAL(cfg);
1763 bool lowemi = PIN_LOWEMI(cfg);
1764 bool gpiomode = PIN_GPIOMODE(cfg);
1765 bool sleep = PIN_SLEEPMODE(cfg);
1767 range = nmk_match_gpio_range(pctldev, pin);
1769 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1773 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1778 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1781 int slpm_pull = PIN_SLPM_PULL(cfg);
1782 int slpm_output = PIN_SLPM_DIR(cfg);
1783 int slpm_val = PIN_SLPM_VAL(cfg);
1785 /* All pins go into GPIO mode at sleep */
1789 * The SLPM_* values are normal values + 1 to allow zero to
1790 * mean "same as normal".
1793 pull = slpm_pull - 1;
1795 output = slpm_output - 1;
1799 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1801 slpm_pull ? pullnames[pull] : "same",
1802 slpm_output ? (output ? "output" : "input") : "same",
1803 slpm_val ? (val ? "high" : "low") : "same");
1806 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1807 pin, cfg, pullnames[pull], slpmnames[slpm],
1808 output ? "output " : "input",
1809 output ? (val ? "high" : "low") : "",
1810 lowemi ? "on" : "off" );
1812 clk_enable(nmk_chip->clk);
1813 bit = pin % NMK_GPIO_PER_CHIP;
1815 /* No glitch when going to GPIO mode */
1816 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1818 __nmk_gpio_make_output(nmk_chip, bit, val);
1820 __nmk_gpio_make_input(nmk_chip, bit);
1821 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1823 /* TODO: isn't this only applicable on output pins? */
1824 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1826 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1827 clk_disable(nmk_chip->clk);
1831 static struct pinconf_ops nmk_pinconf_ops = {
1832 .pin_config_get = nmk_pin_config_get,
1833 .pin_config_set = nmk_pin_config_set,
1836 static struct pinctrl_desc nmk_pinctrl_desc = {
1837 .name = "pinctrl-nomadik",
1838 .pctlops = &nmk_pinctrl_ops,
1839 .pmxops = &nmk_pinmux_ops,
1840 .confops = &nmk_pinconf_ops,
1841 .owner = THIS_MODULE,
1844 static const struct of_device_id nmk_pinctrl_match[] = {
1846 .compatible = "stericsson,nmk_pinctrl",
1847 .data = (void *)PINCTRL_NMK_DB8500,
1852 static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1854 const struct platform_device_id *platid = platform_get_device_id(pdev);
1855 struct device_node *np = pdev->dev.of_node;
1856 struct nmk_pinctrl *npct;
1857 struct resource *res;
1858 unsigned int version = 0;
1861 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1866 version = platid->driver_data;
1868 version = (unsigned int)
1869 of_match_device(nmk_pinctrl_match, &pdev->dev)->data;
1871 /* Poke in other ASIC variants here */
1872 if (version == PINCTRL_NMK_STN8815)
1873 nmk_pinctrl_stn8815_init(&npct->soc);
1874 if (version == PINCTRL_NMK_DB8500)
1875 nmk_pinctrl_db8500_init(&npct->soc);
1876 if (version == PINCTRL_NMK_DB8540)
1877 nmk_pinctrl_db8540_init(&npct->soc);
1879 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1881 npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
1882 resource_size(res));
1883 if (!npct->prcm_base) {
1885 "failed to ioremap PRCM registers\n");
1889 dev_info(&pdev->dev,
1890 "No PRCM base, assume no ALT-Cx control is available\n");
1894 * We need all the GPIO drivers to probe FIRST, or we will not be able
1895 * to obtain references to the struct gpio_chip * for them, and we
1896 * need this to proceed.
1898 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1899 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
1900 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1901 return -EPROBE_DEFER;
1903 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
1906 nmk_pinctrl_desc.pins = npct->soc->pins;
1907 nmk_pinctrl_desc.npins = npct->soc->npins;
1908 npct->dev = &pdev->dev;
1910 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1912 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1916 /* We will handle a range of GPIO pins */
1917 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1918 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1920 platform_set_drvdata(pdev, npct);
1921 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1926 static const struct of_device_id nmk_gpio_match[] = {
1927 { .compatible = "st,nomadik-gpio", },
1931 static struct platform_driver nmk_gpio_driver = {
1933 .owner = THIS_MODULE,
1935 .of_match_table = nmk_gpio_match,
1937 .probe = nmk_gpio_probe,
1940 static const struct platform_device_id nmk_pinctrl_id[] = {
1941 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1942 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1943 { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1947 static struct platform_driver nmk_pinctrl_driver = {
1949 .owner = THIS_MODULE,
1950 .name = "pinctrl-nomadik",
1951 .of_match_table = nmk_pinctrl_match,
1953 .probe = nmk_pinctrl_probe,
1954 .id_table = nmk_pinctrl_id,
1957 static int __init nmk_gpio_init(void)
1961 ret = platform_driver_register(&nmk_gpio_driver);
1964 return platform_driver_register(&nmk_pinctrl_driver);
1967 core_initcall(nmk_gpio_init);
1969 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1970 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1971 MODULE_LICENSE("GPL");