2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29 #include <linux/of_address.h>
30 #include <linux/pinctrl/machine.h>
31 #include <linux/pinctrl/pinctrl.h>
32 #include <linux/pinctrl/pinmux.h>
33 #include <linux/pinctrl/pinconf.h>
34 /* Since we request GPIOs from ourself */
35 #include <linux/pinctrl/consumer.h>
36 #include "pinctrl-nomadik.h"
40 * The GPIO module in the Nomadik family of Systems-on-Chip is an
41 * AMBA device, managing 32 pins and alternate functions. The logic block
42 * is currently used in the Nomadik and ux500.
44 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
48 * pin configurations are represented by 32-bit integers:
50 * bit 0.. 8 - Pin Number (512 Pins Maximum)
51 * bit 9..10 - Alternate Function Selection
52 * bit 11..12 - Pull up/down state
53 * bit 13 - Sleep mode behaviour
55 * bit 15 - Value (if output)
56 * bit 16..18 - SLPM pull up/down state
57 * bit 19..20 - SLPM direction
58 * bit 21..22 - SLPM Value (if output)
59 * bit 23..25 - PDIS value (if input)
63 * to facilitate the definition, the following macros are provided
65 * PIN_CFG_DEFAULT - default config (0):
66 * pull up/down = disabled
67 * sleep mode = input/wakeup
70 * SLPM direction = same as normal
71 * SLPM pull = same as normal
72 * SLPM value = same as normal
74 * PIN_CFG - default config with alternate function
77 typedef unsigned long pin_cfg_t;
79 #define PIN_NUM_MASK 0x1ff
80 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
82 #define PIN_ALT_SHIFT 9
83 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
84 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
85 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
86 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
87 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
88 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
90 #define PIN_PULL_SHIFT 11
91 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
92 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
93 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
94 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
95 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
97 #define PIN_SLPM_SHIFT 13
98 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
99 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
100 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
101 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
102 /* These two replace the above in DB8500v2+ */
103 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
104 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
105 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
107 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
108 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
110 #define PIN_DIR_SHIFT 14
111 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
112 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
113 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
114 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
116 #define PIN_VAL_SHIFT 15
117 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
118 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
119 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
120 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
122 #define PIN_SLPM_PULL_SHIFT 16
123 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
124 #define PIN_SLPM_PULL(x) \
125 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
126 #define PIN_SLPM_PULL_NONE \
127 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
128 #define PIN_SLPM_PULL_UP \
129 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
130 #define PIN_SLPM_PULL_DOWN \
131 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
133 #define PIN_SLPM_DIR_SHIFT 19
134 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
135 #define PIN_SLPM_DIR(x) \
136 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
137 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
138 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
140 #define PIN_SLPM_VAL_SHIFT 21
141 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
142 #define PIN_SLPM_VAL(x) \
143 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
144 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
145 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
147 #define PIN_SLPM_PDIS_SHIFT 23
148 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
149 #define PIN_SLPM_PDIS(x) \
150 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
151 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
152 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
153 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
155 #define PIN_LOWEMI_SHIFT 25
156 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
157 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
158 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
159 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
161 #define PIN_GPIOMODE_SHIFT 26
162 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
163 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
164 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
165 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
167 #define PIN_SLEEPMODE_SHIFT 27
168 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
169 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
170 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
171 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
174 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
175 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
176 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
177 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
178 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
179 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
181 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
182 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
183 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
184 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
185 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
187 #define PIN_CFG_DEFAULT (0)
189 #define PIN_CFG(num, alt) \
191 (PIN_NUM(num) | PIN_##alt))
193 #define PIN_CFG_INPUT(num, alt, pull) \
195 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
197 #define PIN_CFG_OUTPUT(num, alt, val) \
199 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
202 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
203 * the "gpio" namespace for generic and cross-machine functions
206 #define GPIO_BLOCK_SHIFT 5
207 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
209 /* Register in the logic block */
210 #define NMK_GPIO_DAT 0x00
211 #define NMK_GPIO_DATS 0x04
212 #define NMK_GPIO_DATC 0x08
213 #define NMK_GPIO_PDIS 0x0c
214 #define NMK_GPIO_DIR 0x10
215 #define NMK_GPIO_DIRS 0x14
216 #define NMK_GPIO_DIRC 0x18
217 #define NMK_GPIO_SLPC 0x1c
218 #define NMK_GPIO_AFSLA 0x20
219 #define NMK_GPIO_AFSLB 0x24
220 #define NMK_GPIO_LOWEMI 0x28
222 #define NMK_GPIO_RIMSC 0x40
223 #define NMK_GPIO_FIMSC 0x44
224 #define NMK_GPIO_IS 0x48
225 #define NMK_GPIO_IC 0x4c
226 #define NMK_GPIO_RWIMSC 0x50
227 #define NMK_GPIO_FWIMSC 0x54
228 #define NMK_GPIO_WKS 0x58
229 /* These appear in DB8540 and later ASICs */
230 #define NMK_GPIO_EDGELEVEL 0x5C
231 #define NMK_GPIO_LEVEL 0x60
234 /* Pull up/down values */
244 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
245 NMK_GPIO_SLPM_NOCHANGE,
246 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
250 * Platform data to register a block: only the initial gpio/irq number.
252 struct nmk_gpio_platform_data {
257 u32 (*get_latent_status)(unsigned int bank);
258 void (*set_ioforce)(bool enable);
259 bool supports_sleepmode;
262 struct nmk_gpio_chip {
263 struct gpio_chip chip;
264 struct irq_domain *domain;
268 unsigned int parent_irq;
269 int latent_parent_irq;
270 u32 (*get_latent_status)(unsigned int bank);
271 void (*set_ioforce)(bool enable);
274 /* Keep track of configured edges */
287 * struct nmk_pinctrl - state container for the Nomadik pin controller
288 * @dev: containing device pointer
289 * @pctl: corresponding pin controller device
290 * @soc: SoC data for this specific chip
291 * @prcm_base: PRCM register range virtual base
295 struct pinctrl_dev *pctl;
296 const struct nmk_pinctrl_soc_data *soc;
297 void __iomem *prcm_base;
300 static struct nmk_gpio_chip *
301 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
303 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
305 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
307 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
308 unsigned offset, int gpio_mode)
310 u32 bit = 1 << offset;
313 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
314 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
315 if (gpio_mode & NMK_GPIO_ALT_A)
317 if (gpio_mode & NMK_GPIO_ALT_B)
319 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
320 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
323 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
324 unsigned offset, enum nmk_gpio_slpm mode)
326 u32 bit = 1 << offset;
329 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
330 if (mode == NMK_GPIO_SLPM_NOCHANGE)
334 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
337 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
338 unsigned offset, enum nmk_gpio_pull pull)
340 u32 bit = 1 << offset;
343 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
344 if (pull == NMK_GPIO_PULL_NONE) {
346 nmk_chip->pull_up &= ~bit;
351 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
353 if (pull == NMK_GPIO_PULL_UP) {
354 nmk_chip->pull_up |= bit;
355 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
356 } else if (pull == NMK_GPIO_PULL_DOWN) {
357 nmk_chip->pull_up &= ~bit;
358 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
362 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
363 unsigned offset, bool lowemi)
365 u32 bit = BIT(offset);
366 bool enabled = nmk_chip->lowemi & bit;
368 if (lowemi == enabled)
372 nmk_chip->lowemi |= bit;
374 nmk_chip->lowemi &= ~bit;
376 writel_relaxed(nmk_chip->lowemi,
377 nmk_chip->addr + NMK_GPIO_LOWEMI);
380 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
383 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
386 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
387 unsigned offset, int val)
390 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
392 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
395 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
396 unsigned offset, int val)
398 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
399 __nmk_gpio_set_output(nmk_chip, offset, val);
402 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
403 unsigned offset, int gpio_mode,
406 u32 rwimsc = nmk_chip->rwimsc;
407 u32 fwimsc = nmk_chip->fwimsc;
409 if (glitch && nmk_chip->set_ioforce) {
410 u32 bit = BIT(offset);
412 /* Prevent spurious wakeups */
413 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
414 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
416 nmk_chip->set_ioforce(true);
419 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
421 if (glitch && nmk_chip->set_ioforce) {
422 nmk_chip->set_ioforce(false);
424 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
425 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
430 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
432 u32 falling = nmk_chip->fimsc & BIT(offset);
433 u32 rising = nmk_chip->rimsc & BIT(offset);
434 int gpio = nmk_chip->chip.base + offset;
435 int irq = irq_find_mapping(nmk_chip->domain, offset);
436 struct irq_data *d = irq_get_irq_data(irq);
438 if (!rising && !falling)
441 if (!d || !irqd_irq_disabled(d))
445 nmk_chip->rimsc &= ~BIT(offset);
446 writel_relaxed(nmk_chip->rimsc,
447 nmk_chip->addr + NMK_GPIO_RIMSC);
451 nmk_chip->fimsc &= ~BIT(offset);
452 writel_relaxed(nmk_chip->fimsc,
453 nmk_chip->addr + NMK_GPIO_FIMSC);
456 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
459 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
464 val = ((val & ~mask) | (value & mask));
468 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
469 unsigned offset, unsigned alt_num)
475 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
476 const u16 *gpiocr_regs;
478 if (!npct->prcm_base)
481 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
482 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
487 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
488 if (npct->soc->altcx_pins[i].pin == offset)
491 if (i == npct->soc->npins_altcx) {
492 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
497 pin_desc = npct->soc->altcx_pins + i;
498 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
501 * If alt_num is NULL, just clear current ALTCx selection
502 * to make sure we come back to a pure ALTC selection
505 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
506 if (pin_desc->altcx[i].used == true) {
507 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
508 bit = pin_desc->altcx[i].control_bit;
509 if (readl(npct->prcm_base + reg) & BIT(bit)) {
510 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
512 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
520 alt_index = alt_num - 1;
521 if (pin_desc->altcx[alt_index].used == false) {
523 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
529 * Check if any other ALTCx functions are activated on this pin
530 * and disable it first.
532 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
535 if (pin_desc->altcx[i].used == true) {
536 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
537 bit = pin_desc->altcx[i].control_bit;
538 if (readl(npct->prcm_base + reg) & BIT(bit)) {
539 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
541 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
547 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
548 bit = pin_desc->altcx[alt_index].control_bit;
549 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
550 offset, alt_index+1);
551 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
555 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
556 * - Save SLPM registers
557 * - Set SLPM=0 for the IOs you want to switch and others to 1
558 * - Configure the GPIO registers for the IOs that are being switched
560 * - Modify the AFLSA/B registers for the IOs that are being switched
562 * - Restore SLPM registers
563 * - Any spurious wake up event during switch sequence to be ignored and
566 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
570 for (i = 0; i < NUM_BANKS; i++) {
571 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
572 unsigned int temp = slpm[i];
577 clk_enable(chip->clk);
579 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
580 writel(temp, chip->addr + NMK_GPIO_SLPC);
584 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
588 for (i = 0; i < NUM_BANKS; i++) {
589 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
594 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
596 clk_disable(chip->clk);
600 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
605 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
606 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
607 const u16 *gpiocr_regs;
609 if (!npct->prcm_base)
610 return NMK_GPIO_ALT_C;
612 for (i = 0; i < npct->soc->npins_altcx; i++) {
613 if (npct->soc->altcx_pins[i].pin == gpio)
616 if (i == npct->soc->npins_altcx)
617 return NMK_GPIO_ALT_C;
619 pin_desc = npct->soc->altcx_pins + i;
620 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
621 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
622 if (pin_desc->altcx[i].used == true) {
623 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
624 bit = pin_desc->altcx[i].control_bit;
625 if (readl(npct->prcm_base + reg) & BIT(bit))
626 return NMK_GPIO_ALT_C+i+1;
629 return NMK_GPIO_ALT_C;
632 int nmk_gpio_get_mode(int gpio)
634 struct nmk_gpio_chip *nmk_chip;
635 u32 afunc, bfunc, bit;
637 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
641 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
643 clk_enable(nmk_chip->clk);
645 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
646 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
648 clk_disable(nmk_chip->clk);
650 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
652 EXPORT_SYMBOL(nmk_gpio_get_mode);
656 static inline int nmk_gpio_get_bitmask(int gpio)
658 return 1 << (gpio % NMK_GPIO_PER_CHIP);
661 static void nmk_gpio_irq_ack(struct irq_data *d)
663 struct nmk_gpio_chip *nmk_chip;
665 nmk_chip = irq_data_get_irq_chip_data(d);
669 clk_enable(nmk_chip->clk);
670 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
671 clk_disable(nmk_chip->clk);
674 enum nmk_gpio_irq_type {
679 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
680 int gpio, enum nmk_gpio_irq_type which,
683 u32 bitmask = nmk_gpio_get_bitmask(gpio);
689 if (which == NORMAL) {
690 rimscreg = NMK_GPIO_RIMSC;
691 fimscreg = NMK_GPIO_FIMSC;
692 rimscval = &nmk_chip->rimsc;
693 fimscval = &nmk_chip->fimsc;
695 rimscreg = NMK_GPIO_RWIMSC;
696 fimscreg = NMK_GPIO_FWIMSC;
697 rimscval = &nmk_chip->rwimsc;
698 fimscval = &nmk_chip->fwimsc;
701 /* we must individually set/clear the two edges */
702 if (nmk_chip->edge_rising & bitmask) {
704 *rimscval |= bitmask;
706 *rimscval &= ~bitmask;
707 writel(*rimscval, nmk_chip->addr + rimscreg);
709 if (nmk_chip->edge_falling & bitmask) {
711 *fimscval |= bitmask;
713 *fimscval &= ~bitmask;
714 writel(*fimscval, nmk_chip->addr + fimscreg);
718 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
722 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
723 * disabled, since setting SLPM to 1 increases power consumption, and
724 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
726 if (nmk_chip->sleepmode && on) {
727 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
728 NMK_GPIO_SLPM_WAKEUP_ENABLE);
731 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
734 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
736 struct nmk_gpio_chip *nmk_chip;
740 nmk_chip = irq_data_get_irq_chip_data(d);
741 bitmask = nmk_gpio_get_bitmask(d->hwirq);
745 clk_enable(nmk_chip->clk);
746 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
747 spin_lock(&nmk_chip->lock);
749 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
751 if (!(nmk_chip->real_wake & bitmask))
752 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
754 spin_unlock(&nmk_chip->lock);
755 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
756 clk_disable(nmk_chip->clk);
761 static void nmk_gpio_irq_mask(struct irq_data *d)
763 nmk_gpio_irq_maskunmask(d, false);
766 static void nmk_gpio_irq_unmask(struct irq_data *d)
768 nmk_gpio_irq_maskunmask(d, true);
771 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
773 struct nmk_gpio_chip *nmk_chip;
777 nmk_chip = irq_data_get_irq_chip_data(d);
780 bitmask = nmk_gpio_get_bitmask(d->hwirq);
782 clk_enable(nmk_chip->clk);
783 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
784 spin_lock(&nmk_chip->lock);
786 if (irqd_irq_disabled(d))
787 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
790 nmk_chip->real_wake |= bitmask;
792 nmk_chip->real_wake &= ~bitmask;
794 spin_unlock(&nmk_chip->lock);
795 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
796 clk_disable(nmk_chip->clk);
801 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
803 bool enabled = !irqd_irq_disabled(d);
804 bool wake = irqd_is_wakeup_set(d);
805 struct nmk_gpio_chip *nmk_chip;
809 nmk_chip = irq_data_get_irq_chip_data(d);
810 bitmask = nmk_gpio_get_bitmask(d->hwirq);
813 if (type & IRQ_TYPE_LEVEL_HIGH)
815 if (type & IRQ_TYPE_LEVEL_LOW)
818 clk_enable(nmk_chip->clk);
819 spin_lock_irqsave(&nmk_chip->lock, flags);
822 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
825 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
827 nmk_chip->edge_rising &= ~bitmask;
828 if (type & IRQ_TYPE_EDGE_RISING)
829 nmk_chip->edge_rising |= bitmask;
831 nmk_chip->edge_falling &= ~bitmask;
832 if (type & IRQ_TYPE_EDGE_FALLING)
833 nmk_chip->edge_falling |= bitmask;
836 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
839 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
841 spin_unlock_irqrestore(&nmk_chip->lock, flags);
842 clk_disable(nmk_chip->clk);
847 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
849 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
851 clk_enable(nmk_chip->clk);
852 nmk_gpio_irq_unmask(d);
856 static void nmk_gpio_irq_shutdown(struct irq_data *d)
858 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
860 nmk_gpio_irq_mask(d);
861 clk_disable(nmk_chip->clk);
864 static int nmk_gpio_irq_reqres(struct irq_data *d)
866 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
868 if (gpio_lock_as_irq(&nmk_chip->chip, d->hwirq)) {
869 dev_err(nmk_chip->chip.dev,
870 "unable to lock HW IRQ %lu for IRQ\n",
877 static void nmk_gpio_irq_relres(struct irq_data *d)
879 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
881 gpio_unlock_as_irq(&nmk_chip->chip, d->hwirq);
884 static struct irq_chip nmk_gpio_irq_chip = {
885 .name = "Nomadik-GPIO",
886 .irq_ack = nmk_gpio_irq_ack,
887 .irq_mask = nmk_gpio_irq_mask,
888 .irq_unmask = nmk_gpio_irq_unmask,
889 .irq_set_type = nmk_gpio_irq_set_type,
890 .irq_set_wake = nmk_gpio_irq_set_wake,
891 .irq_startup = nmk_gpio_irq_startup,
892 .irq_shutdown = nmk_gpio_irq_shutdown,
893 .irq_request_resources = nmk_gpio_irq_reqres,
894 .irq_release_resources = nmk_gpio_irq_relres,
895 .flags = IRQCHIP_MASK_ON_SUSPEND,
898 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
901 struct nmk_gpio_chip *nmk_chip;
902 struct irq_chip *host_chip = irq_get_chip(irq);
904 chained_irq_enter(host_chip, desc);
906 nmk_chip = irq_get_handler_data(irq);
908 int bit = __ffs(status);
910 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
914 chained_irq_exit(host_chip, desc);
917 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
919 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
922 clk_enable(nmk_chip->clk);
923 status = readl(nmk_chip->addr + NMK_GPIO_IS);
924 clk_disable(nmk_chip->clk);
926 __nmk_gpio_irq_handler(irq, desc, status);
929 static void nmk_gpio_latent_irq_handler(unsigned int irq,
930 struct irq_desc *desc)
932 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
933 u32 status = nmk_chip->get_latent_status(nmk_chip->bank);
935 __nmk_gpio_irq_handler(irq, desc, status);
938 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
940 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
941 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
943 if (nmk_chip->latent_parent_irq >= 0) {
944 irq_set_chained_handler(nmk_chip->latent_parent_irq,
945 nmk_gpio_latent_irq_handler);
946 irq_set_handler_data(nmk_chip->latent_parent_irq, nmk_chip);
954 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
957 * Map back to global GPIO space and request muxing, the direction
958 * parameter does not matter for this controller.
960 int gpio = chip->base + offset;
962 return pinctrl_request_gpio(gpio);
965 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
967 int gpio = chip->base + offset;
969 pinctrl_free_gpio(gpio);
972 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
974 struct nmk_gpio_chip *nmk_chip =
975 container_of(chip, struct nmk_gpio_chip, chip);
977 clk_enable(nmk_chip->clk);
979 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
981 clk_disable(nmk_chip->clk);
986 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
988 struct nmk_gpio_chip *nmk_chip =
989 container_of(chip, struct nmk_gpio_chip, chip);
990 u32 bit = 1 << offset;
993 clk_enable(nmk_chip->clk);
995 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
997 clk_disable(nmk_chip->clk);
1002 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
1005 struct nmk_gpio_chip *nmk_chip =
1006 container_of(chip, struct nmk_gpio_chip, chip);
1008 clk_enable(nmk_chip->clk);
1010 __nmk_gpio_set_output(nmk_chip, offset, val);
1012 clk_disable(nmk_chip->clk);
1015 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
1018 struct nmk_gpio_chip *nmk_chip =
1019 container_of(chip, struct nmk_gpio_chip, chip);
1021 clk_enable(nmk_chip->clk);
1023 __nmk_gpio_make_output(nmk_chip, offset, val);
1025 clk_disable(nmk_chip->clk);
1030 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1032 struct nmk_gpio_chip *nmk_chip =
1033 container_of(chip, struct nmk_gpio_chip, chip);
1035 return irq_create_mapping(nmk_chip->domain, offset);
1038 #ifdef CONFIG_DEBUG_FS
1040 #include <linux/seq_file.h>
1042 static void nmk_gpio_dbg_show_one(struct seq_file *s,
1043 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
1044 unsigned offset, unsigned gpio)
1046 const char *label = gpiochip_is_requested(chip, offset);
1047 struct nmk_gpio_chip *nmk_chip =
1048 container_of(chip, struct nmk_gpio_chip, chip);
1052 u32 bit = 1 << offset;
1053 const char *modes[] = {
1054 [NMK_GPIO_ALT_GPIO] = "gpio",
1055 [NMK_GPIO_ALT_A] = "altA",
1056 [NMK_GPIO_ALT_B] = "altB",
1057 [NMK_GPIO_ALT_C] = "altC",
1058 [NMK_GPIO_ALT_C+1] = "altC1",
1059 [NMK_GPIO_ALT_C+2] = "altC2",
1060 [NMK_GPIO_ALT_C+3] = "altC3",
1061 [NMK_GPIO_ALT_C+4] = "altC4",
1064 clk_enable(nmk_chip->clk);
1065 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1066 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1067 mode = nmk_gpio_get_mode(gpio);
1068 if ((mode == NMK_GPIO_ALT_C) && pctldev)
1069 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1071 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
1072 gpio, label ?: "(none)",
1073 is_out ? "out" : "in ",
1075 ? (chip->get(chip, offset) ? "hi" : "lo")
1077 (mode < 0) ? "unknown" : modes[mode],
1078 pull ? "pull" : "none");
1081 int irq = gpio_to_irq(gpio);
1082 struct irq_desc *desc = irq_to_desc(irq);
1084 /* This races with request_irq(), set_irq_type(),
1085 * and set_irq_wake() ... but those are "rare".
1087 if (irq > 0 && desc && desc->action) {
1089 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1091 if (nmk_chip->edge_rising & bitmask)
1092 trigger = "edge-rising";
1093 else if (nmk_chip->edge_falling & bitmask)
1094 trigger = "edge-falling";
1096 trigger = "edge-undefined";
1098 seq_printf(s, " irq-%d %s%s",
1100 irqd_is_wakeup_set(&desc->irq_data)
1104 clk_disable(nmk_chip->clk);
1107 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1110 unsigned gpio = chip->base;
1112 for (i = 0; i < chip->ngpio; i++, gpio++) {
1113 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1114 seq_printf(s, "\n");
1119 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1120 struct pinctrl_dev *pctldev,
1121 struct gpio_chip *chip,
1122 unsigned offset, unsigned gpio)
1125 #define nmk_gpio_dbg_show NULL
1128 /* This structure is replicated for each GPIO block allocated at probe time */
1129 static struct gpio_chip nmk_gpio_template = {
1130 .request = nmk_gpio_request,
1131 .free = nmk_gpio_free,
1132 .direction_input = nmk_gpio_make_input,
1133 .get = nmk_gpio_get_input,
1134 .direction_output = nmk_gpio_make_output,
1135 .set = nmk_gpio_set_output,
1136 .to_irq = nmk_gpio_to_irq,
1137 .dbg_show = nmk_gpio_dbg_show,
1141 void nmk_gpio_clocks_enable(void)
1145 for (i = 0; i < NUM_BANKS; i++) {
1146 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1151 clk_enable(chip->clk);
1155 void nmk_gpio_clocks_disable(void)
1159 for (i = 0; i < NUM_BANKS; i++) {
1160 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1165 clk_disable(chip->clk);
1170 * Called from the suspend/resume path to only keep the real wakeup interrupts
1171 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1172 * and not the rest of the interrupts which we needed to have as wakeups for
1175 * PM ops are not used since this needs to be done at the end, after all the
1176 * other drivers are done with their suspend callbacks.
1178 void nmk_gpio_wakeups_suspend(void)
1182 for (i = 0; i < NUM_BANKS; i++) {
1183 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1188 clk_enable(chip->clk);
1190 writel(chip->rwimsc & chip->real_wake,
1191 chip->addr + NMK_GPIO_RWIMSC);
1192 writel(chip->fwimsc & chip->real_wake,
1193 chip->addr + NMK_GPIO_FWIMSC);
1195 clk_disable(chip->clk);
1199 void nmk_gpio_wakeups_resume(void)
1203 for (i = 0; i < NUM_BANKS; i++) {
1204 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1209 clk_enable(chip->clk);
1211 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1212 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1214 clk_disable(chip->clk);
1219 * Read the pull up/pull down status.
1220 * A bit set in 'pull_up' means that pull up
1221 * is selected if pull is enabled in PDIS register.
1222 * Note: only pull up/down set via this driver can
1223 * be detected due to HW limitations.
1225 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1227 if (gpio_bank < NUM_BANKS) {
1228 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1233 *pull_up = chip->pull_up;
1237 static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1238 irq_hw_number_t hwirq)
1240 struct nmk_gpio_chip *nmk_chip = d->host_data;
1245 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1246 set_irq_flags(irq, IRQF_VALID);
1247 irq_set_chip_data(irq, nmk_chip);
1248 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1253 static const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1254 .map = nmk_gpio_irq_map,
1255 .xlate = irq_domain_xlate_twocell,
1258 static int nmk_gpio_probe(struct platform_device *dev)
1260 struct nmk_gpio_platform_data *pdata;
1261 struct device_node *np = dev->dev.of_node;
1262 struct nmk_gpio_chip *nmk_chip;
1263 struct gpio_chip *chip;
1264 struct resource *res;
1271 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1275 if (of_get_property(np, "st,supports-sleepmode", NULL))
1276 pdata->supports_sleepmode = true;
1278 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1279 dev_err(&dev->dev, "gpio-bank property not found\n");
1283 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1284 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1286 irq = platform_get_irq(dev, 0);
1290 latent_irq = platform_get_irq(dev, 1);
1291 if (latent_irq >= 0 && !pdata->get_latent_status)
1294 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1295 base = devm_ioremap_resource(&dev->dev, res);
1297 return PTR_ERR(base);
1299 clk = devm_clk_get(&dev->dev, NULL);
1301 return PTR_ERR(clk);
1304 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1309 * The virt address in nmk_chip->addr is in the nomadik register space,
1310 * so we can simply convert the resource address, without remapping
1312 nmk_chip->bank = dev->id;
1313 nmk_chip->clk = clk;
1314 nmk_chip->addr = base;
1315 nmk_chip->chip = nmk_gpio_template;
1316 nmk_chip->parent_irq = irq;
1317 nmk_chip->latent_parent_irq = latent_irq;
1318 nmk_chip->get_latent_status = pdata->get_latent_status;
1319 nmk_chip->set_ioforce = pdata->set_ioforce;
1320 nmk_chip->sleepmode = pdata->supports_sleepmode;
1321 spin_lock_init(&nmk_chip->lock);
1323 chip = &nmk_chip->chip;
1324 chip->base = pdata->first_gpio;
1325 chip->ngpio = pdata->num_gpio;
1326 chip->label = pdata->name ?: dev_name(&dev->dev);
1327 chip->dev = &dev->dev;
1328 chip->owner = THIS_MODULE;
1330 clk_enable(nmk_chip->clk);
1331 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1332 clk_disable(nmk_chip->clk);
1335 ret = gpiochip_add(&nmk_chip->chip);
1339 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1341 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1343 platform_set_drvdata(dev, nmk_chip);
1345 nmk_chip->domain = irq_domain_add_simple(np,
1346 NMK_GPIO_PER_CHIP, 0,
1347 &nmk_gpio_irq_simple_ops, nmk_chip);
1348 if (!nmk_chip->domain) {
1349 dev_err(&dev->dev, "failed to create irqdomain\n");
1350 /* Just do this, no matter if it fails */
1351 ret = gpiochip_remove(&nmk_chip->chip);
1355 nmk_gpio_init_irq(nmk_chip);
1357 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1362 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1364 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1366 return npct->soc->ngroups;
1369 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1372 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1374 return npct->soc->groups[selector].name;
1377 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1378 const unsigned **pins,
1381 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1383 *pins = npct->soc->groups[selector].pins;
1384 *num_pins = npct->soc->groups[selector].npins;
1388 static struct pinctrl_gpio_range *
1389 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1391 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1394 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1395 struct pinctrl_gpio_range *range;
1397 range = &npct->soc->gpio_ranges[i];
1398 if (offset >= range->pin_base &&
1399 offset <= (range->pin_base + range->npins - 1))
1405 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1408 struct pinctrl_gpio_range *range;
1409 struct gpio_chip *chip;
1411 range = nmk_match_gpio_range(pctldev, offset);
1412 if (!range || !range->gc) {
1413 seq_printf(s, "invalid pin offset");
1417 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1420 static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1421 struct pinctrl_map *map, unsigned num_maps)
1425 for (i = 0; i < num_maps; i++)
1426 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1427 kfree(map[i].data.configs.configs);
1431 static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
1432 unsigned *num_maps, unsigned reserve)
1434 unsigned old_num = *reserved_maps;
1435 unsigned new_num = *num_maps + reserve;
1436 struct pinctrl_map *new_map;
1438 if (old_num >= new_num)
1441 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1445 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1448 *reserved_maps = new_num;
1453 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1454 unsigned *num_maps, const char *group,
1455 const char *function)
1457 if (*num_maps == *reserved_maps)
1460 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1461 (*map)[*num_maps].data.mux.group = group;
1462 (*map)[*num_maps].data.mux.function = function;
1468 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1469 unsigned *reserved_maps,
1470 unsigned *num_maps, const char *group,
1471 unsigned long *configs, unsigned num_configs)
1473 unsigned long *dup_configs;
1475 if (*num_maps == *reserved_maps)
1478 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1483 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1485 (*map)[*num_maps].data.configs.group_or_pin = group;
1486 (*map)[*num_maps].data.configs.configs = dup_configs;
1487 (*map)[*num_maps].data.configs.num_configs = num_configs;
1493 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1494 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1495 .size = ARRAY_SIZE(y), }
1497 static const unsigned long nmk_pin_input_modes[] = {
1503 static const unsigned long nmk_pin_output_modes[] = {
1509 static const unsigned long nmk_pin_sleep_modes[] = {
1510 PIN_SLEEPMODE_DISABLED,
1511 PIN_SLEEPMODE_ENABLED,
1514 static const unsigned long nmk_pin_sleep_input_modes[] = {
1515 PIN_SLPM_INPUT_NOPULL,
1516 PIN_SLPM_INPUT_PULLUP,
1517 PIN_SLPM_INPUT_PULLDOWN,
1521 static const unsigned long nmk_pin_sleep_output_modes[] = {
1522 PIN_SLPM_OUTPUT_LOW,
1523 PIN_SLPM_OUTPUT_HIGH,
1524 PIN_SLPM_DIR_OUTPUT,
1527 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1528 PIN_SLPM_WAKEUP_DISABLE,
1529 PIN_SLPM_WAKEUP_ENABLE,
1532 static const unsigned long nmk_pin_gpio_modes[] = {
1533 PIN_GPIOMODE_DISABLED,
1534 PIN_GPIOMODE_ENABLED,
1537 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1538 PIN_SLPM_PDIS_DISABLED,
1539 PIN_SLPM_PDIS_ENABLED,
1542 struct nmk_cfg_param {
1543 const char *property;
1544 unsigned long config;
1545 const unsigned long *choice;
1549 static const struct nmk_cfg_param nmk_cfg_params[] = {
1550 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1551 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1552 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1553 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1554 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1555 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1556 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1557 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1560 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1564 if (nmk_cfg_params[index].choice == NULL)
1565 *config = nmk_cfg_params[index].config;
1567 /* test if out of range */
1568 if (val < nmk_cfg_params[index].size) {
1569 *config = nmk_cfg_params[index].config |
1570 nmk_cfg_params[index].choice[val];
1576 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1579 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1581 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1582 for (i = 0; i < npct->soc->npins; i++)
1583 if (npct->soc->pins[i].number == pin_number)
1584 return npct->soc->pins[i].name;
1588 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1589 unsigned long *configs)
1591 bool has_config = 0;
1592 unsigned long cfg = 0;
1595 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1596 ret = of_property_read_u32(np,
1597 nmk_cfg_params[i].property, &val);
1598 if (ret != -EINVAL) {
1599 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1609 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1610 struct device_node *np,
1611 struct pinctrl_map **map,
1612 unsigned *reserved_maps,
1616 const char *function = NULL;
1617 unsigned long configs = 0;
1618 bool has_config = 0;
1619 unsigned reserve = 0;
1620 struct property *prop;
1621 const char *group, *gpio_name;
1622 struct device_node *np_config;
1624 ret = of_property_read_string(np, "ste,function", &function);
1628 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1630 np_config = of_parse_phandle(np, "ste,config", 0);
1632 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1634 ret = of_property_count_strings(np, "ste,pins");
1643 ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
1647 of_property_for_each_string(np, "ste,pins", prop, group) {
1649 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1655 gpio_name = nmk_find_pin_name(pctldev, group);
1657 ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
1658 gpio_name, &configs, 1);
1668 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1669 struct device_node *np_config,
1670 struct pinctrl_map **map, unsigned *num_maps)
1672 unsigned reserved_maps;
1673 struct device_node *np;
1680 for_each_child_of_node(np_config, np) {
1681 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1682 &reserved_maps, num_maps);
1684 nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
1692 static const struct pinctrl_ops nmk_pinctrl_ops = {
1693 .get_groups_count = nmk_get_groups_cnt,
1694 .get_group_name = nmk_get_group_name,
1695 .get_group_pins = nmk_get_group_pins,
1696 .pin_dbg_show = nmk_pin_dbg_show,
1697 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1698 .dt_free_map = nmk_pinctrl_dt_free_map,
1701 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1703 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1705 return npct->soc->nfunctions;
1708 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1711 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1713 return npct->soc->functions[function].name;
1716 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1718 const char * const **groups,
1719 unsigned * const num_groups)
1721 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1723 *groups = npct->soc->functions[function].groups;
1724 *num_groups = npct->soc->functions[function].ngroups;
1729 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1732 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1733 const struct nmk_pingroup *g;
1734 static unsigned int slpm[NUM_BANKS];
1735 unsigned long flags = 0;
1740 g = &npct->soc->groups[group];
1742 if (g->altsetting < 0)
1745 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1748 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1749 * we may pass through an undesired state. In this case we take
1752 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1753 * - Save SLPM registers (since we have a shadow register in the
1754 * nmk_chip we're using that as backup)
1755 * - Set SLPM=0 for the IOs you want to switch and others to 1
1756 * - Configure the GPIO registers for the IOs that are being switched
1758 * - Modify the AFLSA/B registers for the IOs that are being switched
1760 * - Restore SLPM registers
1761 * - Any spurious wake up event during switch sequence to be ignored
1764 * We REALLY need to save ALL slpm registers, because the external
1765 * IOFORCE will switch *all* ports to their sleepmode setting to as
1766 * to avoid glitches. (Not just one port!)
1768 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1771 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1773 /* Initially don't put any pins to sleep when switching */
1774 memset(slpm, 0xff, sizeof(slpm));
1777 * Then mask the pins that need to be sleeping now when we're
1778 * switching to the ALT C function.
1780 for (i = 0; i < g->npins; i++)
1781 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1782 nmk_gpio_glitch_slpm_init(slpm);
1785 for (i = 0; i < g->npins; i++) {
1786 struct pinctrl_gpio_range *range;
1787 struct nmk_gpio_chip *nmk_chip;
1788 struct gpio_chip *chip;
1791 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1794 "invalid pin offset %d in group %s at index %d\n",
1795 g->pins[i], g->name, i);
1799 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1800 g->pins[i], g->name, i);
1804 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1805 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1807 clk_enable(nmk_chip->clk);
1808 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1810 * If the pin is switching to altfunc, and there was an
1811 * interrupt installed on it which has been lazy disabled,
1812 * actually mask the interrupt to prevent spurious interrupts
1813 * that would occur while the pin is under control of the
1814 * peripheral. Only SKE does this.
1816 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1818 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1819 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1820 clk_disable(nmk_chip->clk);
1823 * Call PRCM GPIOCR config function in case ALTC
1824 * has been selected:
1825 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1827 * - If selection is pure ALTC and previous selection was ALTCx,
1828 * then some bits in PRCM GPIOCR registers must be cleared.
1830 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1831 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1832 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1835 /* When all pins are successfully reconfigured we get here */
1840 nmk_gpio_glitch_slpm_restore(slpm);
1841 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1847 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1848 unsigned function, unsigned group)
1850 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1851 const struct nmk_pingroup *g;
1853 g = &npct->soc->groups[group];
1855 if (g->altsetting < 0)
1858 /* Poke out the mux, set the pin to some default state? */
1859 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1862 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1863 struct pinctrl_gpio_range *range,
1866 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1867 struct nmk_gpio_chip *nmk_chip;
1868 struct gpio_chip *chip;
1872 dev_err(npct->dev, "invalid range\n");
1876 dev_err(npct->dev, "missing GPIO chip in range\n");
1880 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1882 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1884 clk_enable(nmk_chip->clk);
1885 bit = offset % NMK_GPIO_PER_CHIP;
1886 /* There is no glitch when converting any pin to GPIO */
1887 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1888 clk_disable(nmk_chip->clk);
1893 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1894 struct pinctrl_gpio_range *range,
1897 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1899 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1900 /* Set the pin to some default state, GPIO is usually default */
1903 static const struct pinmux_ops nmk_pinmux_ops = {
1904 .get_functions_count = nmk_pmx_get_funcs_cnt,
1905 .get_function_name = nmk_pmx_get_func_name,
1906 .get_function_groups = nmk_pmx_get_func_groups,
1907 .enable = nmk_pmx_enable,
1908 .disable = nmk_pmx_disable,
1909 .gpio_request_enable = nmk_gpio_request_enable,
1910 .gpio_disable_free = nmk_gpio_disable_free,
1913 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1914 unsigned long *config)
1916 /* Not implemented */
1920 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1921 unsigned long *configs, unsigned num_configs)
1923 static const char *pullnames[] = {
1924 [NMK_GPIO_PULL_NONE] = "none",
1925 [NMK_GPIO_PULL_UP] = "up",
1926 [NMK_GPIO_PULL_DOWN] = "down",
1927 [3] /* illegal */ = "??"
1929 static const char *slpmnames[] = {
1930 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1931 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1933 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1934 struct nmk_gpio_chip *nmk_chip;
1935 struct pinctrl_gpio_range *range;
1936 struct gpio_chip *chip;
1939 int pull, slpm, output, val, i;
1940 bool lowemi, gpiomode, sleep;
1942 range = nmk_match_gpio_range(pctldev, pin);
1944 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1948 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1953 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1955 for (i = 0; i < num_configs; i++) {
1957 * The pin config contains pin number and altfunction fields,
1958 * here we just ignore that part. It's being handled by the
1959 * framework and pinmux callback respectively.
1961 cfg = (pin_cfg_t) configs[i];
1962 pull = PIN_PULL(cfg);
1963 slpm = PIN_SLPM(cfg);
1964 output = PIN_DIR(cfg);
1966 lowemi = PIN_LOWEMI(cfg);
1967 gpiomode = PIN_GPIOMODE(cfg);
1968 sleep = PIN_SLEEPMODE(cfg);
1971 int slpm_pull = PIN_SLPM_PULL(cfg);
1972 int slpm_output = PIN_SLPM_DIR(cfg);
1973 int slpm_val = PIN_SLPM_VAL(cfg);
1975 /* All pins go into GPIO mode at sleep */
1979 * The SLPM_* values are normal values + 1 to allow zero
1980 * to mean "same as normal".
1983 pull = slpm_pull - 1;
1985 output = slpm_output - 1;
1989 dev_dbg(nmk_chip->chip.dev,
1990 "pin %d: sleep pull %s, dir %s, val %s\n",
1992 slpm_pull ? pullnames[pull] : "same",
1993 slpm_output ? (output ? "output" : "input")
1995 slpm_val ? (val ? "high" : "low") : "same");
1998 dev_dbg(nmk_chip->chip.dev,
1999 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
2000 pin, cfg, pullnames[pull], slpmnames[slpm],
2001 output ? "output " : "input",
2002 output ? (val ? "high" : "low") : "",
2003 lowemi ? "on" : "off");
2005 clk_enable(nmk_chip->clk);
2006 bit = pin % NMK_GPIO_PER_CHIP;
2008 /* No glitch when going to GPIO mode */
2009 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
2011 __nmk_gpio_make_output(nmk_chip, bit, val);
2013 __nmk_gpio_make_input(nmk_chip, bit);
2014 __nmk_gpio_set_pull(nmk_chip, bit, pull);
2016 /* TODO: isn't this only applicable on output pins? */
2017 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
2019 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
2020 clk_disable(nmk_chip->clk);
2021 } /* for each config */
2026 static const struct pinconf_ops nmk_pinconf_ops = {
2027 .pin_config_get = nmk_pin_config_get,
2028 .pin_config_set = nmk_pin_config_set,
2031 static struct pinctrl_desc nmk_pinctrl_desc = {
2032 .name = "pinctrl-nomadik",
2033 .pctlops = &nmk_pinctrl_ops,
2034 .pmxops = &nmk_pinmux_ops,
2035 .confops = &nmk_pinconf_ops,
2036 .owner = THIS_MODULE,
2039 static const struct of_device_id nmk_pinctrl_match[] = {
2041 .compatible = "stericsson,stn8815-pinctrl",
2042 .data = (void *)PINCTRL_NMK_STN8815,
2045 .compatible = "stericsson,db8500-pinctrl",
2046 .data = (void *)PINCTRL_NMK_DB8500,
2049 .compatible = "stericsson,db8540-pinctrl",
2050 .data = (void *)PINCTRL_NMK_DB8540,
2055 static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
2057 struct nmk_pinctrl *npct;
2059 npct = platform_get_drvdata(pdev);
2063 return pinctrl_force_sleep(npct->pctl);
2066 static int nmk_pinctrl_resume(struct platform_device *pdev)
2068 struct nmk_pinctrl *npct;
2070 npct = platform_get_drvdata(pdev);
2074 return pinctrl_force_default(npct->pctl);
2077 static int nmk_pinctrl_probe(struct platform_device *pdev)
2079 const struct of_device_id *match;
2080 struct device_node *np = pdev->dev.of_node;
2081 struct device_node *prcm_np;
2082 struct nmk_pinctrl *npct;
2083 unsigned int version = 0;
2086 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
2090 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
2093 version = (unsigned int) match->data;
2095 /* Poke in other ASIC variants here */
2096 if (version == PINCTRL_NMK_STN8815)
2097 nmk_pinctrl_stn8815_init(&npct->soc);
2098 if (version == PINCTRL_NMK_DB8500)
2099 nmk_pinctrl_db8500_init(&npct->soc);
2100 if (version == PINCTRL_NMK_DB8540)
2101 nmk_pinctrl_db8540_init(&npct->soc);
2103 prcm_np = of_parse_phandle(np, "prcm", 0);
2105 npct->prcm_base = of_iomap(prcm_np, 0);
2106 if (!npct->prcm_base) {
2107 if (version == PINCTRL_NMK_STN8815) {
2108 dev_info(&pdev->dev,
2110 "assuming no ALT-Cx control is available\n");
2112 dev_err(&pdev->dev, "missing PRCM base address\n");
2118 * We need all the GPIO drivers to probe FIRST, or we will not be able
2119 * to obtain references to the struct gpio_chip * for them, and we
2120 * need this to proceed.
2122 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
2123 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
2124 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
2125 return -EPROBE_DEFER;
2127 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
2130 nmk_pinctrl_desc.pins = npct->soc->pins;
2131 nmk_pinctrl_desc.npins = npct->soc->npins;
2132 npct->dev = &pdev->dev;
2134 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
2136 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
2140 /* We will handle a range of GPIO pins */
2141 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
2142 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
2144 platform_set_drvdata(pdev, npct);
2145 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
2150 static const struct of_device_id nmk_gpio_match[] = {
2151 { .compatible = "st,nomadik-gpio", },
2155 static struct platform_driver nmk_gpio_driver = {
2157 .owner = THIS_MODULE,
2159 .of_match_table = nmk_gpio_match,
2161 .probe = nmk_gpio_probe,
2164 static struct platform_driver nmk_pinctrl_driver = {
2166 .owner = THIS_MODULE,
2167 .name = "pinctrl-nomadik",
2168 .of_match_table = nmk_pinctrl_match,
2170 .probe = nmk_pinctrl_probe,
2172 .suspend = nmk_pinctrl_suspend,
2173 .resume = nmk_pinctrl_resume,
2177 static int __init nmk_gpio_init(void)
2181 ret = platform_driver_register(&nmk_gpio_driver);
2184 return platform_driver_register(&nmk_pinctrl_driver);
2187 core_initcall(nmk_gpio_init);
2189 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
2190 MODULE_DESCRIPTION("Nomadik GPIO Driver");
2191 MODULE_LICENSE("GPL");