2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/slab.h>
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 /* Since we request GPIOs from ourself */
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/platform_data/pinctrl-nomadik.h>
34 #include <asm/mach/irq.h>
35 #include <mach/irqs.h>
36 #include "pinctrl-nomadik.h"
39 * The GPIO module in the Nomadik family of Systems-on-Chip is an
40 * AMBA device, managing 32 pins and alternate functions. The logic block
41 * is currently used in the Nomadik and ux500.
43 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
46 struct nmk_gpio_chip {
47 struct gpio_chip chip;
48 struct irq_domain *domain;
52 unsigned int parent_irq;
53 int secondary_parent_irq;
54 u32 (*get_secondary_status)(unsigned int bank);
55 void (*set_ioforce)(bool enable);
58 /* Keep track of configured edges */
71 * struct nmk_pinctrl - state container for the Nomadik pin controller
72 * @dev: containing device pointer
73 * @pctl: corresponding pin controller device
74 * @soc: SoC data for this specific chip
75 * @prcm_base: PRCM register range virtual base
79 struct pinctrl_dev *pctl;
80 const struct nmk_pinctrl_soc_data *soc;
81 void __iomem *prcm_base;
84 static struct nmk_gpio_chip *
85 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
87 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
89 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
91 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
92 unsigned offset, int gpio_mode)
94 u32 bit = 1 << offset;
97 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
98 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
99 if (gpio_mode & NMK_GPIO_ALT_A)
101 if (gpio_mode & NMK_GPIO_ALT_B)
103 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
104 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
107 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
108 unsigned offset, enum nmk_gpio_slpm mode)
110 u32 bit = 1 << offset;
113 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
114 if (mode == NMK_GPIO_SLPM_NOCHANGE)
118 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
121 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
122 unsigned offset, enum nmk_gpio_pull pull)
124 u32 bit = 1 << offset;
127 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
128 if (pull == NMK_GPIO_PULL_NONE) {
130 nmk_chip->pull_up &= ~bit;
135 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
137 if (pull == NMK_GPIO_PULL_UP) {
138 nmk_chip->pull_up |= bit;
139 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
140 } else if (pull == NMK_GPIO_PULL_DOWN) {
141 nmk_chip->pull_up &= ~bit;
142 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
146 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
147 unsigned offset, bool lowemi)
149 u32 bit = BIT(offset);
150 bool enabled = nmk_chip->lowemi & bit;
152 if (lowemi == enabled)
156 nmk_chip->lowemi |= bit;
158 nmk_chip->lowemi &= ~bit;
160 writel_relaxed(nmk_chip->lowemi,
161 nmk_chip->addr + NMK_GPIO_LOWEMI);
164 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
167 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
170 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
171 unsigned offset, int val)
174 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
176 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
179 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
180 unsigned offset, int val)
182 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
183 __nmk_gpio_set_output(nmk_chip, offset, val);
186 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
187 unsigned offset, int gpio_mode,
190 u32 rwimsc = nmk_chip->rwimsc;
191 u32 fwimsc = nmk_chip->fwimsc;
193 if (glitch && nmk_chip->set_ioforce) {
194 u32 bit = BIT(offset);
196 /* Prevent spurious wakeups */
197 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
198 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
200 nmk_chip->set_ioforce(true);
203 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
205 if (glitch && nmk_chip->set_ioforce) {
206 nmk_chip->set_ioforce(false);
208 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
209 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
214 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
216 u32 falling = nmk_chip->fimsc & BIT(offset);
217 u32 rising = nmk_chip->rimsc & BIT(offset);
218 int gpio = nmk_chip->chip.base + offset;
219 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
220 struct irq_data *d = irq_get_irq_data(irq);
222 if (!rising && !falling)
225 if (!d || !irqd_irq_disabled(d))
229 nmk_chip->rimsc &= ~BIT(offset);
230 writel_relaxed(nmk_chip->rimsc,
231 nmk_chip->addr + NMK_GPIO_RIMSC);
235 nmk_chip->fimsc &= ~BIT(offset);
236 writel_relaxed(nmk_chip->fimsc,
237 nmk_chip->addr + NMK_GPIO_FIMSC);
240 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
243 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
248 val = ((val & ~mask) | (value & mask));
252 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
253 unsigned offset, unsigned alt_num)
259 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
260 const u16 *gpiocr_regs;
262 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
263 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
268 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
269 if (npct->soc->altcx_pins[i].pin == offset)
272 if (i == npct->soc->npins_altcx) {
273 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
278 pin_desc = npct->soc->altcx_pins + i;
279 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
282 * If alt_num is NULL, just clear current ALTCx selection
283 * to make sure we come back to a pure ALTC selection
286 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
287 if (pin_desc->altcx[i].used == true) {
288 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
289 bit = pin_desc->altcx[i].control_bit;
290 if (readl(npct->prcm_base + reg) & BIT(bit)) {
291 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
293 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
301 alt_index = alt_num - 1;
302 if (pin_desc->altcx[alt_index].used == false) {
304 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
310 * Check if any other ALTCx functions are activated on this pin
311 * and disable it first.
313 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
316 if (pin_desc->altcx[i].used == true) {
317 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
318 bit = pin_desc->altcx[i].control_bit;
319 if (readl(npct->prcm_base + reg) & BIT(bit)) {
320 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
322 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
328 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
329 bit = pin_desc->altcx[alt_index].control_bit;
330 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
331 offset, alt_index+1);
332 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
335 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
336 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
338 static const char *afnames[] = {
339 [NMK_GPIO_ALT_GPIO] = "GPIO",
340 [NMK_GPIO_ALT_A] = "A",
341 [NMK_GPIO_ALT_B] = "B",
342 [NMK_GPIO_ALT_C] = "C"
344 static const char *pullnames[] = {
345 [NMK_GPIO_PULL_NONE] = "none",
346 [NMK_GPIO_PULL_UP] = "up",
347 [NMK_GPIO_PULL_DOWN] = "down",
348 [3] /* illegal */ = "??"
350 static const char *slpmnames[] = {
351 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
352 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
355 int pin = PIN_NUM(cfg);
356 int pull = PIN_PULL(cfg);
357 int af = PIN_ALT(cfg);
358 int slpm = PIN_SLPM(cfg);
359 int output = PIN_DIR(cfg);
360 int val = PIN_VAL(cfg);
361 bool glitch = af == NMK_GPIO_ALT_C;
363 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
364 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
365 output ? "output " : "input",
366 output ? (val ? "high" : "low") : "");
369 int slpm_pull = PIN_SLPM_PULL(cfg);
370 int slpm_output = PIN_SLPM_DIR(cfg);
371 int slpm_val = PIN_SLPM_VAL(cfg);
373 af = NMK_GPIO_ALT_GPIO;
376 * The SLPM_* values are normal values + 1 to allow zero to
377 * mean "same as normal".
380 pull = slpm_pull - 1;
382 output = slpm_output - 1;
386 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
388 slpm_pull ? pullnames[pull] : "same",
389 slpm_output ? (output ? "output" : "input") : "same",
390 slpm_val ? (val ? "high" : "low") : "same");
394 __nmk_gpio_make_output(nmk_chip, offset, val);
396 __nmk_gpio_make_input(nmk_chip, offset);
397 __nmk_gpio_set_pull(nmk_chip, offset, pull);
400 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
403 * If the pin is switching to altfunc, and there was an interrupt
404 * installed on it which has been lazy disabled, actually mask the
405 * interrupt to prevent spurious interrupts that would occur while the
406 * pin is under control of the peripheral. Only SKE does this.
408 if (af != NMK_GPIO_ALT_GPIO)
409 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
412 * If we've backed up the SLPM registers (glitch workaround), modify
413 * the backups since they will be restored.
416 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
417 slpmregs[nmk_chip->bank] |= BIT(offset);
419 slpmregs[nmk_chip->bank] &= ~BIT(offset);
421 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
423 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
427 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
428 * - Save SLPM registers
429 * - Set SLPM=0 for the IOs you want to switch and others to 1
430 * - Configure the GPIO registers for the IOs that are being switched
432 * - Modify the AFLSA/B registers for the IOs that are being switched
434 * - Restore SLPM registers
435 * - Any spurious wake up event during switch sequence to be ignored and
438 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
442 for (i = 0; i < NUM_BANKS; i++) {
443 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
444 unsigned int temp = slpm[i];
449 clk_enable(chip->clk);
451 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
452 writel(temp, chip->addr + NMK_GPIO_SLPC);
456 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
460 for (i = 0; i < NUM_BANKS; i++) {
461 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
466 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
468 clk_disable(chip->clk);
472 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
474 static unsigned int slpm[NUM_BANKS];
480 for (i = 0; i < num; i++) {
481 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
487 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
490 memset(slpm, 0xff, sizeof(slpm));
492 for (i = 0; i < num; i++) {
493 int pin = PIN_NUM(cfgs[i]);
494 int offset = pin % NMK_GPIO_PER_CHIP;
496 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
497 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
500 nmk_gpio_glitch_slpm_init(slpm);
503 for (i = 0; i < num; i++) {
504 struct nmk_gpio_chip *nmk_chip;
505 int pin = PIN_NUM(cfgs[i]);
507 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
513 clk_enable(nmk_chip->clk);
514 spin_lock(&nmk_chip->lock);
515 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
516 cfgs[i], sleep, glitch ? slpm : NULL);
517 spin_unlock(&nmk_chip->lock);
518 clk_disable(nmk_chip->clk);
522 nmk_gpio_glitch_slpm_restore(slpm);
524 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
530 * nmk_config_pin - configure a pin's mux attributes
531 * @cfg: pin confguration
532 * @sleep: Non-zero to apply the sleep mode configuration
533 * Configures a pin's mode (alternate function or GPIO), its pull up status,
534 * and its sleep mode based on the specified configuration. The @cfg is
535 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
536 * are constructed using, and can be further enhanced with, the macros in
537 * <linux/platform_data/pinctrl-nomadik.h>
539 * If a pin's mode is set to GPIO, it is configured as an input to avoid
540 * side-effects. The gpio can be manipulated later using standard GPIO API
543 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
545 return __nmk_config_pins(&cfg, 1, sleep);
547 EXPORT_SYMBOL(nmk_config_pin);
550 * nmk_config_pins - configure several pins at once
551 * @cfgs: array of pin configurations
552 * @num: number of elments in the array
554 * Configures several pins using nmk_config_pin(). Refer to that function for
555 * further information.
557 int nmk_config_pins(pin_cfg_t *cfgs, int num)
559 return __nmk_config_pins(cfgs, num, false);
561 EXPORT_SYMBOL(nmk_config_pins);
563 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
565 return __nmk_config_pins(cfgs, num, true);
567 EXPORT_SYMBOL(nmk_config_pins_sleep);
570 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
572 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
574 * This register is actually in the pinmux layer, not the GPIO block itself.
575 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
576 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
577 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
578 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
579 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
580 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
582 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
583 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
584 * entered) regardless of the altfunction selected. Also wake-up detection is
587 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
588 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
589 * (for altfunction GPIO) or respective on-chip peripherals (for other
590 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
592 * Note that enable_irq_wake() will automatically enable wakeup detection.
594 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
596 struct nmk_gpio_chip *nmk_chip;
599 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
603 clk_enable(nmk_chip->clk);
604 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
605 spin_lock(&nmk_chip->lock);
607 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
609 spin_unlock(&nmk_chip->lock);
610 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
611 clk_disable(nmk_chip->clk);
617 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
619 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
621 * Enables/disables pull up/down on a specified pin. This only takes effect if
622 * the pin is configured as an input (either explicitly or by the alternate
625 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
626 * configured as an input. Otherwise, due to the way the controller registers
627 * work, this function will change the value output on the pin.
629 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
631 struct nmk_gpio_chip *nmk_chip;
634 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
638 clk_enable(nmk_chip->clk);
639 spin_lock_irqsave(&nmk_chip->lock, flags);
640 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
641 spin_unlock_irqrestore(&nmk_chip->lock, flags);
642 clk_disable(nmk_chip->clk);
649 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
651 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
652 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
654 * Sets the mode of the specified pin to one of the alternate functions or
657 int nmk_gpio_set_mode(int gpio, int gpio_mode)
659 struct nmk_gpio_chip *nmk_chip;
662 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
666 clk_enable(nmk_chip->clk);
667 spin_lock_irqsave(&nmk_chip->lock, flags);
668 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
669 spin_unlock_irqrestore(&nmk_chip->lock, flags);
670 clk_disable(nmk_chip->clk);
674 EXPORT_SYMBOL(nmk_gpio_set_mode);
676 static int nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
681 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
682 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
683 const u16 *gpiocr_regs;
685 for (i = 0; i < npct->soc->npins_altcx; i++) {
686 if (npct->soc->altcx_pins[i].pin == gpio)
689 if (i == npct->soc->npins_altcx)
690 return NMK_GPIO_ALT_C;
692 pin_desc = npct->soc->altcx_pins + i;
693 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
694 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
695 if (pin_desc->altcx[i].used == true) {
696 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
697 bit = pin_desc->altcx[i].control_bit;
698 if (readl(npct->prcm_base + reg) & BIT(bit))
699 return NMK_GPIO_ALT_C+i+1;
702 return NMK_GPIO_ALT_C;
705 int nmk_gpio_get_mode(int gpio)
707 struct nmk_gpio_chip *nmk_chip;
708 u32 afunc, bfunc, bit;
710 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
714 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
716 clk_enable(nmk_chip->clk);
718 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
719 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
721 clk_disable(nmk_chip->clk);
723 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
725 EXPORT_SYMBOL(nmk_gpio_get_mode);
729 static inline int nmk_gpio_get_bitmask(int gpio)
731 return 1 << (gpio % NMK_GPIO_PER_CHIP);
734 static void nmk_gpio_irq_ack(struct irq_data *d)
736 struct nmk_gpio_chip *nmk_chip;
738 nmk_chip = irq_data_get_irq_chip_data(d);
742 clk_enable(nmk_chip->clk);
743 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
744 clk_disable(nmk_chip->clk);
747 enum nmk_gpio_irq_type {
752 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
753 int gpio, enum nmk_gpio_irq_type which,
756 u32 bitmask = nmk_gpio_get_bitmask(gpio);
762 if (which == NORMAL) {
763 rimscreg = NMK_GPIO_RIMSC;
764 fimscreg = NMK_GPIO_FIMSC;
765 rimscval = &nmk_chip->rimsc;
766 fimscval = &nmk_chip->fimsc;
768 rimscreg = NMK_GPIO_RWIMSC;
769 fimscreg = NMK_GPIO_FWIMSC;
770 rimscval = &nmk_chip->rwimsc;
771 fimscval = &nmk_chip->fwimsc;
774 /* we must individually set/clear the two edges */
775 if (nmk_chip->edge_rising & bitmask) {
777 *rimscval |= bitmask;
779 *rimscval &= ~bitmask;
780 writel(*rimscval, nmk_chip->addr + rimscreg);
782 if (nmk_chip->edge_falling & bitmask) {
784 *fimscval |= bitmask;
786 *fimscval &= ~bitmask;
787 writel(*fimscval, nmk_chip->addr + fimscreg);
791 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
795 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
796 * disabled, since setting SLPM to 1 increases power consumption, and
797 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
799 if (nmk_chip->sleepmode && on) {
800 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
801 NMK_GPIO_SLPM_WAKEUP_ENABLE);
804 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
807 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
809 struct nmk_gpio_chip *nmk_chip;
813 nmk_chip = irq_data_get_irq_chip_data(d);
814 bitmask = nmk_gpio_get_bitmask(d->hwirq);
818 clk_enable(nmk_chip->clk);
819 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
820 spin_lock(&nmk_chip->lock);
822 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
824 if (!(nmk_chip->real_wake & bitmask))
825 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
827 spin_unlock(&nmk_chip->lock);
828 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
829 clk_disable(nmk_chip->clk);
834 static void nmk_gpio_irq_mask(struct irq_data *d)
836 nmk_gpio_irq_maskunmask(d, false);
839 static void nmk_gpio_irq_unmask(struct irq_data *d)
841 nmk_gpio_irq_maskunmask(d, true);
844 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
846 struct nmk_gpio_chip *nmk_chip;
850 nmk_chip = irq_data_get_irq_chip_data(d);
853 bitmask = nmk_gpio_get_bitmask(d->hwirq);
855 clk_enable(nmk_chip->clk);
856 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
857 spin_lock(&nmk_chip->lock);
859 if (irqd_irq_disabled(d))
860 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
863 nmk_chip->real_wake |= bitmask;
865 nmk_chip->real_wake &= ~bitmask;
867 spin_unlock(&nmk_chip->lock);
868 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
869 clk_disable(nmk_chip->clk);
874 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
876 bool enabled = !irqd_irq_disabled(d);
877 bool wake = irqd_is_wakeup_set(d);
878 struct nmk_gpio_chip *nmk_chip;
882 nmk_chip = irq_data_get_irq_chip_data(d);
883 bitmask = nmk_gpio_get_bitmask(d->hwirq);
886 if (type & IRQ_TYPE_LEVEL_HIGH)
888 if (type & IRQ_TYPE_LEVEL_LOW)
891 clk_enable(nmk_chip->clk);
892 spin_lock_irqsave(&nmk_chip->lock, flags);
895 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
898 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
900 nmk_chip->edge_rising &= ~bitmask;
901 if (type & IRQ_TYPE_EDGE_RISING)
902 nmk_chip->edge_rising |= bitmask;
904 nmk_chip->edge_falling &= ~bitmask;
905 if (type & IRQ_TYPE_EDGE_FALLING)
906 nmk_chip->edge_falling |= bitmask;
909 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
912 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
914 spin_unlock_irqrestore(&nmk_chip->lock, flags);
915 clk_disable(nmk_chip->clk);
920 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
922 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
924 clk_enable(nmk_chip->clk);
925 nmk_gpio_irq_unmask(d);
929 static void nmk_gpio_irq_shutdown(struct irq_data *d)
931 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
933 nmk_gpio_irq_mask(d);
934 clk_disable(nmk_chip->clk);
937 static struct irq_chip nmk_gpio_irq_chip = {
938 .name = "Nomadik-GPIO",
939 .irq_ack = nmk_gpio_irq_ack,
940 .irq_mask = nmk_gpio_irq_mask,
941 .irq_unmask = nmk_gpio_irq_unmask,
942 .irq_set_type = nmk_gpio_irq_set_type,
943 .irq_set_wake = nmk_gpio_irq_set_wake,
944 .irq_startup = nmk_gpio_irq_startup,
945 .irq_shutdown = nmk_gpio_irq_shutdown,
946 .flags = IRQCHIP_MASK_ON_SUSPEND,
949 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
952 struct nmk_gpio_chip *nmk_chip;
953 struct irq_chip *host_chip = irq_get_chip(irq);
955 chained_irq_enter(host_chip, desc);
957 nmk_chip = irq_get_handler_data(irq);
959 int bit = __ffs(status);
961 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
965 chained_irq_exit(host_chip, desc);
968 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
970 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
973 clk_enable(nmk_chip->clk);
974 status = readl(nmk_chip->addr + NMK_GPIO_IS);
975 clk_disable(nmk_chip->clk);
977 __nmk_gpio_irq_handler(irq, desc, status);
980 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
981 struct irq_desc *desc)
983 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
984 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
986 __nmk_gpio_irq_handler(irq, desc, status);
989 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
991 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
992 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
994 if (nmk_chip->secondary_parent_irq >= 0) {
995 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
996 nmk_gpio_secondary_irq_handler);
997 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
1005 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
1008 * Map back to global GPIO space and request muxing, the direction
1009 * parameter does not matter for this controller.
1011 int gpio = chip->base + offset;
1013 return pinctrl_request_gpio(gpio);
1016 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
1018 int gpio = chip->base + offset;
1020 pinctrl_free_gpio(gpio);
1023 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
1025 struct nmk_gpio_chip *nmk_chip =
1026 container_of(chip, struct nmk_gpio_chip, chip);
1028 clk_enable(nmk_chip->clk);
1030 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
1032 clk_disable(nmk_chip->clk);
1037 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
1039 struct nmk_gpio_chip *nmk_chip =
1040 container_of(chip, struct nmk_gpio_chip, chip);
1041 u32 bit = 1 << offset;
1044 clk_enable(nmk_chip->clk);
1046 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
1048 clk_disable(nmk_chip->clk);
1053 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
1056 struct nmk_gpio_chip *nmk_chip =
1057 container_of(chip, struct nmk_gpio_chip, chip);
1059 clk_enable(nmk_chip->clk);
1061 __nmk_gpio_set_output(nmk_chip, offset, val);
1063 clk_disable(nmk_chip->clk);
1066 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
1069 struct nmk_gpio_chip *nmk_chip =
1070 container_of(chip, struct nmk_gpio_chip, chip);
1072 clk_enable(nmk_chip->clk);
1074 __nmk_gpio_make_output(nmk_chip, offset, val);
1076 clk_disable(nmk_chip->clk);
1081 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1083 struct nmk_gpio_chip *nmk_chip =
1084 container_of(chip, struct nmk_gpio_chip, chip);
1086 return irq_create_mapping(nmk_chip->domain, offset);
1089 #ifdef CONFIG_DEBUG_FS
1091 #include <linux/seq_file.h>
1093 static void nmk_gpio_dbg_show_one(struct seq_file *s,
1094 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
1095 unsigned offset, unsigned gpio)
1097 const char *label = gpiochip_is_requested(chip, offset);
1098 struct nmk_gpio_chip *nmk_chip =
1099 container_of(chip, struct nmk_gpio_chip, chip);
1103 u32 bit = 1 << offset;
1104 const char *modes[] = {
1105 [NMK_GPIO_ALT_GPIO] = "gpio",
1106 [NMK_GPIO_ALT_A] = "altA",
1107 [NMK_GPIO_ALT_B] = "altB",
1108 [NMK_GPIO_ALT_C] = "altC",
1109 [NMK_GPIO_ALT_C+1] = "altC1",
1110 [NMK_GPIO_ALT_C+2] = "altC2",
1111 [NMK_GPIO_ALT_C+3] = "altC3",
1112 [NMK_GPIO_ALT_C+4] = "altC4",
1115 clk_enable(nmk_chip->clk);
1116 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1117 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1118 mode = nmk_gpio_get_mode(gpio);
1119 if ((mode == NMK_GPIO_ALT_C) && pctldev)
1120 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1122 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
1123 gpio, label ?: "(none)",
1124 is_out ? "out" : "in ",
1126 ? (chip->get(chip, offset) ? "hi" : "lo")
1128 (mode < 0) ? "unknown" : modes[mode],
1129 pull ? "pull" : "none");
1131 if (label && !is_out) {
1132 int irq = gpio_to_irq(gpio);
1133 struct irq_desc *desc = irq_to_desc(irq);
1135 /* This races with request_irq(), set_irq_type(),
1136 * and set_irq_wake() ... but those are "rare".
1138 if (irq >= 0 && desc->action) {
1140 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1142 if (nmk_chip->edge_rising & bitmask)
1143 trigger = "edge-rising";
1144 else if (nmk_chip->edge_falling & bitmask)
1145 trigger = "edge-falling";
1147 trigger = "edge-undefined";
1149 seq_printf(s, " irq-%d %s%s",
1151 irqd_is_wakeup_set(&desc->irq_data)
1155 clk_disable(nmk_chip->clk);
1158 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1161 unsigned gpio = chip->base;
1163 for (i = 0; i < chip->ngpio; i++, gpio++) {
1164 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1165 seq_printf(s, "\n");
1170 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1171 struct pinctrl_dev *pctldev,
1172 struct gpio_chip *chip,
1173 unsigned offset, unsigned gpio)
1176 #define nmk_gpio_dbg_show NULL
1179 /* This structure is replicated for each GPIO block allocated at probe time */
1180 static struct gpio_chip nmk_gpio_template = {
1181 .request = nmk_gpio_request,
1182 .free = nmk_gpio_free,
1183 .direction_input = nmk_gpio_make_input,
1184 .get = nmk_gpio_get_input,
1185 .direction_output = nmk_gpio_make_output,
1186 .set = nmk_gpio_set_output,
1187 .to_irq = nmk_gpio_to_irq,
1188 .dbg_show = nmk_gpio_dbg_show,
1192 void nmk_gpio_clocks_enable(void)
1196 for (i = 0; i < NUM_BANKS; i++) {
1197 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1202 clk_enable(chip->clk);
1206 void nmk_gpio_clocks_disable(void)
1210 for (i = 0; i < NUM_BANKS; i++) {
1211 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1216 clk_disable(chip->clk);
1221 * Called from the suspend/resume path to only keep the real wakeup interrupts
1222 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1223 * and not the rest of the interrupts which we needed to have as wakeups for
1226 * PM ops are not used since this needs to be done at the end, after all the
1227 * other drivers are done with their suspend callbacks.
1229 void nmk_gpio_wakeups_suspend(void)
1233 for (i = 0; i < NUM_BANKS; i++) {
1234 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1239 clk_enable(chip->clk);
1241 writel(chip->rwimsc & chip->real_wake,
1242 chip->addr + NMK_GPIO_RWIMSC);
1243 writel(chip->fwimsc & chip->real_wake,
1244 chip->addr + NMK_GPIO_FWIMSC);
1246 clk_disable(chip->clk);
1250 void nmk_gpio_wakeups_resume(void)
1254 for (i = 0; i < NUM_BANKS; i++) {
1255 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1260 clk_enable(chip->clk);
1262 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1263 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1265 clk_disable(chip->clk);
1270 * Read the pull up/pull down status.
1271 * A bit set in 'pull_up' means that pull up
1272 * is selected if pull is enabled in PDIS register.
1273 * Note: only pull up/down set via this driver can
1274 * be detected due to HW limitations.
1276 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1278 if (gpio_bank < NUM_BANKS) {
1279 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1284 *pull_up = chip->pull_up;
1288 static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1289 irq_hw_number_t hwirq)
1291 struct nmk_gpio_chip *nmk_chip = d->host_data;
1296 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1297 set_irq_flags(irq, IRQF_VALID);
1298 irq_set_chip_data(irq, nmk_chip);
1299 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1304 const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1305 .map = nmk_gpio_irq_map,
1306 .xlate = irq_domain_xlate_twocell,
1309 static int __devinit nmk_gpio_probe(struct platform_device *dev)
1311 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1312 struct device_node *np = dev->dev.of_node;
1313 struct nmk_gpio_chip *nmk_chip;
1314 struct gpio_chip *chip;
1315 struct resource *res;
1323 if (!pdata && !np) {
1324 dev_err(&dev->dev, "No platform data or device tree found\n");
1329 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1333 if (of_get_property(np, "st,supports-sleepmode", NULL))
1334 pdata->supports_sleepmode = true;
1336 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1337 dev_err(&dev->dev, "gpio-bank property not found\n");
1342 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1343 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1346 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1352 irq = platform_get_irq(dev, 0);
1358 secondary_irq = platform_get_irq(dev, 1);
1359 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1364 base = devm_request_and_ioremap(&dev->dev, res);
1370 clk = devm_clk_get(&dev->dev, NULL);
1377 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1384 * The virt address in nmk_chip->addr is in the nomadik register space,
1385 * so we can simply convert the resource address, without remapping
1387 nmk_chip->bank = dev->id;
1388 nmk_chip->clk = clk;
1389 nmk_chip->addr = base;
1390 nmk_chip->chip = nmk_gpio_template;
1391 nmk_chip->parent_irq = irq;
1392 nmk_chip->secondary_parent_irq = secondary_irq;
1393 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1394 nmk_chip->set_ioforce = pdata->set_ioforce;
1395 nmk_chip->sleepmode = pdata->supports_sleepmode;
1396 spin_lock_init(&nmk_chip->lock);
1398 chip = &nmk_chip->chip;
1399 chip->base = pdata->first_gpio;
1400 chip->ngpio = pdata->num_gpio;
1401 chip->label = pdata->name ?: dev_name(&dev->dev);
1402 chip->dev = &dev->dev;
1403 chip->owner = THIS_MODULE;
1405 clk_enable(nmk_chip->clk);
1406 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1407 clk_disable(nmk_chip->clk);
1409 #ifdef CONFIG_OF_GPIO
1413 ret = gpiochip_add(&nmk_chip->chip);
1417 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1419 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1421 platform_set_drvdata(dev, nmk_chip);
1424 irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio);
1425 nmk_chip->domain = irq_domain_add_simple(np,
1426 NMK_GPIO_PER_CHIP, irq_start,
1427 &nmk_gpio_irq_simple_ops, nmk_chip);
1428 if (!nmk_chip->domain) {
1429 dev_err(&dev->dev, "failed to create irqdomain\n");
1434 nmk_gpio_init_irq(nmk_chip);
1436 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1441 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1442 pdata->first_gpio, pdata->first_gpio+31);
1447 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1449 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1451 return npct->soc->ngroups;
1454 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1457 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1459 return npct->soc->groups[selector].name;
1462 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1463 const unsigned **pins,
1466 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1468 *pins = npct->soc->groups[selector].pins;
1469 *num_pins = npct->soc->groups[selector].npins;
1473 static struct pinctrl_gpio_range *
1474 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1476 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1479 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1480 struct pinctrl_gpio_range *range;
1482 range = &npct->soc->gpio_ranges[i];
1483 if (offset >= range->pin_base &&
1484 offset <= (range->pin_base + range->npins - 1))
1490 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1493 struct pinctrl_gpio_range *range;
1494 struct gpio_chip *chip;
1496 range = nmk_match_gpio_range(pctldev, offset);
1497 if (!range || !range->gc) {
1498 seq_printf(s, "invalid pin offset");
1502 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1505 static struct pinctrl_ops nmk_pinctrl_ops = {
1506 .get_groups_count = nmk_get_groups_cnt,
1507 .get_group_name = nmk_get_group_name,
1508 .get_group_pins = nmk_get_group_pins,
1509 .pin_dbg_show = nmk_pin_dbg_show,
1512 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1514 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1516 return npct->soc->nfunctions;
1519 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1522 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1524 return npct->soc->functions[function].name;
1527 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1529 const char * const **groups,
1530 unsigned * const num_groups)
1532 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1534 *groups = npct->soc->functions[function].groups;
1535 *num_groups = npct->soc->functions[function].ngroups;
1540 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1543 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1544 const struct nmk_pingroup *g;
1545 static unsigned int slpm[NUM_BANKS];
1546 unsigned long flags;
1551 g = &npct->soc->groups[group];
1553 if (g->altsetting < 0)
1556 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1559 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1560 * we may pass through an undesired state. In this case we take
1563 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1564 * - Save SLPM registers (since we have a shadow register in the
1565 * nmk_chip we're using that as backup)
1566 * - Set SLPM=0 for the IOs you want to switch and others to 1
1567 * - Configure the GPIO registers for the IOs that are being switched
1569 * - Modify the AFLSA/B registers for the IOs that are being switched
1571 * - Restore SLPM registers
1572 * - Any spurious wake up event during switch sequence to be ignored
1575 * We REALLY need to save ALL slpm registers, because the external
1576 * IOFORCE will switch *all* ports to their sleepmode setting to as
1577 * to avoid glitches. (Not just one port!)
1579 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1582 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1584 /* Initially don't put any pins to sleep when switching */
1585 memset(slpm, 0xff, sizeof(slpm));
1588 * Then mask the pins that need to be sleeping now when we're
1589 * switching to the ALT C function.
1591 for (i = 0; i < g->npins; i++)
1592 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1593 nmk_gpio_glitch_slpm_init(slpm);
1596 for (i = 0; i < g->npins; i++) {
1597 struct pinctrl_gpio_range *range;
1598 struct nmk_gpio_chip *nmk_chip;
1599 struct gpio_chip *chip;
1602 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1605 "invalid pin offset %d in group %s at index %d\n",
1606 g->pins[i], g->name, i);
1610 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1611 g->pins[i], g->name, i);
1615 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1616 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1618 clk_enable(nmk_chip->clk);
1619 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1621 * If the pin is switching to altfunc, and there was an
1622 * interrupt installed on it which has been lazy disabled,
1623 * actually mask the interrupt to prevent spurious interrupts
1624 * that would occur while the pin is under control of the
1625 * peripheral. Only SKE does this.
1627 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1629 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1630 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1631 clk_disable(nmk_chip->clk);
1634 * Call PRCM GPIOCR config function in case ALTC
1635 * has been selected:
1636 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1638 * - If selection is pure ALTC and previous selection was ALTCx,
1639 * then some bits in PRCM GPIOCR registers must be cleared.
1641 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1642 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1643 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1646 /* When all pins are successfully reconfigured we get here */
1651 nmk_gpio_glitch_slpm_restore(slpm);
1652 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1658 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1659 unsigned function, unsigned group)
1661 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1662 const struct nmk_pingroup *g;
1664 g = &npct->soc->groups[group];
1666 if (g->altsetting < 0)
1669 /* Poke out the mux, set the pin to some default state? */
1670 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1673 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1674 struct pinctrl_gpio_range *range,
1677 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1678 struct nmk_gpio_chip *nmk_chip;
1679 struct gpio_chip *chip;
1683 dev_err(npct->dev, "invalid range\n");
1687 dev_err(npct->dev, "missing GPIO chip in range\n");
1691 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1693 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1695 clk_enable(nmk_chip->clk);
1696 bit = offset % NMK_GPIO_PER_CHIP;
1697 /* There is no glitch when converting any pin to GPIO */
1698 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1699 clk_disable(nmk_chip->clk);
1704 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1705 struct pinctrl_gpio_range *range,
1708 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1710 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1711 /* Set the pin to some default state, GPIO is usually default */
1714 static struct pinmux_ops nmk_pinmux_ops = {
1715 .get_functions_count = nmk_pmx_get_funcs_cnt,
1716 .get_function_name = nmk_pmx_get_func_name,
1717 .get_function_groups = nmk_pmx_get_func_groups,
1718 .enable = nmk_pmx_enable,
1719 .disable = nmk_pmx_disable,
1720 .gpio_request_enable = nmk_gpio_request_enable,
1721 .gpio_disable_free = nmk_gpio_disable_free,
1724 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1725 unsigned long *config)
1727 /* Not implemented */
1731 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1732 unsigned long config)
1734 static const char *pullnames[] = {
1735 [NMK_GPIO_PULL_NONE] = "none",
1736 [NMK_GPIO_PULL_UP] = "up",
1737 [NMK_GPIO_PULL_DOWN] = "down",
1738 [3] /* illegal */ = "??"
1740 static const char *slpmnames[] = {
1741 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1742 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1744 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1745 struct nmk_gpio_chip *nmk_chip;
1746 struct pinctrl_gpio_range *range;
1747 struct gpio_chip *chip;
1751 * The pin config contains pin number and altfunction fields, here
1752 * we just ignore that part. It's being handled by the framework and
1753 * pinmux callback respectively.
1755 pin_cfg_t cfg = (pin_cfg_t) config;
1756 int pull = PIN_PULL(cfg);
1757 int slpm = PIN_SLPM(cfg);
1758 int output = PIN_DIR(cfg);
1759 int val = PIN_VAL(cfg);
1760 bool lowemi = PIN_LOWEMI(cfg);
1761 bool gpiomode = PIN_GPIOMODE(cfg);
1762 bool sleep = PIN_SLEEPMODE(cfg);
1764 range = nmk_match_gpio_range(pctldev, pin);
1766 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1770 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1775 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1778 int slpm_pull = PIN_SLPM_PULL(cfg);
1779 int slpm_output = PIN_SLPM_DIR(cfg);
1780 int slpm_val = PIN_SLPM_VAL(cfg);
1782 /* All pins go into GPIO mode at sleep */
1786 * The SLPM_* values are normal values + 1 to allow zero to
1787 * mean "same as normal".
1790 pull = slpm_pull - 1;
1792 output = slpm_output - 1;
1796 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1798 slpm_pull ? pullnames[pull] : "same",
1799 slpm_output ? (output ? "output" : "input") : "same",
1800 slpm_val ? (val ? "high" : "low") : "same");
1803 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1804 pin, cfg, pullnames[pull], slpmnames[slpm],
1805 output ? "output " : "input",
1806 output ? (val ? "high" : "low") : "",
1807 lowemi ? "on" : "off" );
1809 clk_enable(nmk_chip->clk);
1810 bit = pin % NMK_GPIO_PER_CHIP;
1812 /* No glitch when going to GPIO mode */
1813 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1815 __nmk_gpio_make_output(nmk_chip, bit, val);
1817 __nmk_gpio_make_input(nmk_chip, bit);
1818 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1820 /* TODO: isn't this only applicable on output pins? */
1821 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1823 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1824 clk_disable(nmk_chip->clk);
1828 static struct pinconf_ops nmk_pinconf_ops = {
1829 .pin_config_get = nmk_pin_config_get,
1830 .pin_config_set = nmk_pin_config_set,
1833 static struct pinctrl_desc nmk_pinctrl_desc = {
1834 .name = "pinctrl-nomadik",
1835 .pctlops = &nmk_pinctrl_ops,
1836 .pmxops = &nmk_pinmux_ops,
1837 .confops = &nmk_pinconf_ops,
1838 .owner = THIS_MODULE,
1841 static const struct of_device_id nmk_pinctrl_match[] = {
1843 .compatible = "stericsson,nmk_pinctrl",
1844 .data = (void *)PINCTRL_NMK_DB8500,
1849 static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1851 const struct platform_device_id *platid = platform_get_device_id(pdev);
1852 struct device_node *np = pdev->dev.of_node;
1853 struct nmk_pinctrl *npct;
1854 struct resource *res;
1855 unsigned int version = 0;
1858 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1863 version = platid->driver_data;
1865 const struct of_device_id *match;
1867 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1870 version = (unsigned int) match->data;
1873 /* Poke in other ASIC variants here */
1874 if (version == PINCTRL_NMK_STN8815)
1875 nmk_pinctrl_stn8815_init(&npct->soc);
1876 if (version == PINCTRL_NMK_DB8500)
1877 nmk_pinctrl_db8500_init(&npct->soc);
1878 if (version == PINCTRL_NMK_DB8540)
1879 nmk_pinctrl_db8540_init(&npct->soc);
1881 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1883 npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
1884 resource_size(res));
1885 if (!npct->prcm_base) {
1887 "failed to ioremap PRCM registers\n");
1891 dev_info(&pdev->dev,
1892 "No PRCM base, assume no ALT-Cx control is available\n");
1896 * We need all the GPIO drivers to probe FIRST, or we will not be able
1897 * to obtain references to the struct gpio_chip * for them, and we
1898 * need this to proceed.
1900 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1901 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
1902 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1903 return -EPROBE_DEFER;
1905 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
1908 nmk_pinctrl_desc.pins = npct->soc->pins;
1909 nmk_pinctrl_desc.npins = npct->soc->npins;
1910 npct->dev = &pdev->dev;
1912 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1914 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1918 /* We will handle a range of GPIO pins */
1919 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1920 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1922 platform_set_drvdata(pdev, npct);
1923 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1928 static const struct of_device_id nmk_gpio_match[] = {
1929 { .compatible = "st,nomadik-gpio", },
1933 static struct platform_driver nmk_gpio_driver = {
1935 .owner = THIS_MODULE,
1937 .of_match_table = nmk_gpio_match,
1939 .probe = nmk_gpio_probe,
1942 static const struct platform_device_id nmk_pinctrl_id[] = {
1943 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1944 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1945 { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1949 static struct platform_driver nmk_pinctrl_driver = {
1951 .owner = THIS_MODULE,
1952 .name = "pinctrl-nomadik",
1953 .of_match_table = nmk_pinctrl_match,
1955 .probe = nmk_pinctrl_probe,
1956 .id_table = nmk_pinctrl_id,
1959 static int __init nmk_gpio_init(void)
1963 ret = platform_driver_register(&nmk_gpio_driver);
1966 return platform_driver_register(&nmk_pinctrl_driver);
1969 core_initcall(nmk_gpio_init);
1971 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1972 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1973 MODULE_LICENSE("GPL");