2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29 #include <linux/of_address.h>
30 #include <linux/pinctrl/machine.h>
31 #include <linux/pinctrl/pinctrl.h>
32 #include <linux/pinctrl/pinmux.h>
33 #include <linux/pinctrl/pinconf.h>
34 /* Since we request GPIOs from ourself */
35 #include <linux/pinctrl/consumer.h>
36 #include "pinctrl-nomadik.h"
40 * The GPIO module in the Nomadik family of Systems-on-Chip is an
41 * AMBA device, managing 32 pins and alternate functions. The logic block
42 * is currently used in the Nomadik and ux500.
44 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
48 * pin configurations are represented by 32-bit integers:
50 * bit 0.. 8 - Pin Number (512 Pins Maximum)
51 * bit 9..10 - Alternate Function Selection
52 * bit 11..12 - Pull up/down state
53 * bit 13 - Sleep mode behaviour
55 * bit 15 - Value (if output)
56 * bit 16..18 - SLPM pull up/down state
57 * bit 19..20 - SLPM direction
58 * bit 21..22 - SLPM Value (if output)
59 * bit 23..25 - PDIS value (if input)
63 * to facilitate the definition, the following macros are provided
65 * PIN_CFG_DEFAULT - default config (0):
66 * pull up/down = disabled
67 * sleep mode = input/wakeup
70 * SLPM direction = same as normal
71 * SLPM pull = same as normal
72 * SLPM value = same as normal
74 * PIN_CFG - default config with alternate function
77 typedef unsigned long pin_cfg_t;
79 #define PIN_NUM_MASK 0x1ff
80 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
82 #define PIN_ALT_SHIFT 9
83 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
84 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
85 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
86 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
87 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
88 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
90 #define PIN_PULL_SHIFT 11
91 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
92 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
93 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
94 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
95 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
97 #define PIN_SLPM_SHIFT 13
98 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
99 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
100 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
101 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
102 /* These two replace the above in DB8500v2+ */
103 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
104 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
105 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
107 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
108 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
110 #define PIN_DIR_SHIFT 14
111 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
112 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
113 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
114 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
116 #define PIN_VAL_SHIFT 15
117 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
118 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
119 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
120 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
122 #define PIN_SLPM_PULL_SHIFT 16
123 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
124 #define PIN_SLPM_PULL(x) \
125 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
126 #define PIN_SLPM_PULL_NONE \
127 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
128 #define PIN_SLPM_PULL_UP \
129 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
130 #define PIN_SLPM_PULL_DOWN \
131 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
133 #define PIN_SLPM_DIR_SHIFT 19
134 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
135 #define PIN_SLPM_DIR(x) \
136 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
137 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
138 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
140 #define PIN_SLPM_VAL_SHIFT 21
141 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
142 #define PIN_SLPM_VAL(x) \
143 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
144 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
145 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
147 #define PIN_SLPM_PDIS_SHIFT 23
148 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
149 #define PIN_SLPM_PDIS(x) \
150 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
151 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
152 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
153 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
155 #define PIN_LOWEMI_SHIFT 25
156 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
157 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
158 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
159 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
161 #define PIN_GPIOMODE_SHIFT 26
162 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
163 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
164 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
165 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
167 #define PIN_SLEEPMODE_SHIFT 27
168 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
169 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
170 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
171 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
174 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
175 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
176 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
177 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
178 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
179 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
181 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
182 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
183 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
184 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
185 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
187 #define PIN_CFG_DEFAULT (0)
189 #define PIN_CFG(num, alt) \
191 (PIN_NUM(num) | PIN_##alt))
193 #define PIN_CFG_INPUT(num, alt, pull) \
195 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
197 #define PIN_CFG_OUTPUT(num, alt, val) \
199 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
202 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
203 * the "gpio" namespace for generic and cross-machine functions
206 #define GPIO_BLOCK_SHIFT 5
207 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
209 /* Register in the logic block */
210 #define NMK_GPIO_DAT 0x00
211 #define NMK_GPIO_DATS 0x04
212 #define NMK_GPIO_DATC 0x08
213 #define NMK_GPIO_PDIS 0x0c
214 #define NMK_GPIO_DIR 0x10
215 #define NMK_GPIO_DIRS 0x14
216 #define NMK_GPIO_DIRC 0x18
217 #define NMK_GPIO_SLPC 0x1c
218 #define NMK_GPIO_AFSLA 0x20
219 #define NMK_GPIO_AFSLB 0x24
220 #define NMK_GPIO_LOWEMI 0x28
222 #define NMK_GPIO_RIMSC 0x40
223 #define NMK_GPIO_FIMSC 0x44
224 #define NMK_GPIO_IS 0x48
225 #define NMK_GPIO_IC 0x4c
226 #define NMK_GPIO_RWIMSC 0x50
227 #define NMK_GPIO_FWIMSC 0x54
228 #define NMK_GPIO_WKS 0x58
229 /* These appear in DB8540 and later ASICs */
230 #define NMK_GPIO_EDGELEVEL 0x5C
231 #define NMK_GPIO_LEVEL 0x60
234 /* Pull up/down values */
244 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
245 NMK_GPIO_SLPM_NOCHANGE,
246 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
249 struct nmk_gpio_chip {
250 struct gpio_chip chip;
251 struct irq_domain *domain;
255 unsigned int parent_irq;
256 int latent_parent_irq;
257 u32 (*get_latent_status)(unsigned int bank);
258 void (*set_ioforce)(bool enable);
261 /* Keep track of configured edges */
274 * struct nmk_pinctrl - state container for the Nomadik pin controller
275 * @dev: containing device pointer
276 * @pctl: corresponding pin controller device
277 * @soc: SoC data for this specific chip
278 * @prcm_base: PRCM register range virtual base
282 struct pinctrl_dev *pctl;
283 const struct nmk_pinctrl_soc_data *soc;
284 void __iomem *prcm_base;
287 static struct nmk_gpio_chip *
288 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
290 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
292 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
294 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
295 unsigned offset, int gpio_mode)
297 u32 bit = 1 << offset;
300 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
301 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
302 if (gpio_mode & NMK_GPIO_ALT_A)
304 if (gpio_mode & NMK_GPIO_ALT_B)
306 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
307 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
310 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
311 unsigned offset, enum nmk_gpio_slpm mode)
313 u32 bit = 1 << offset;
316 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
317 if (mode == NMK_GPIO_SLPM_NOCHANGE)
321 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
324 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
325 unsigned offset, enum nmk_gpio_pull pull)
327 u32 bit = 1 << offset;
330 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
331 if (pull == NMK_GPIO_PULL_NONE) {
333 nmk_chip->pull_up &= ~bit;
338 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
340 if (pull == NMK_GPIO_PULL_UP) {
341 nmk_chip->pull_up |= bit;
342 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
343 } else if (pull == NMK_GPIO_PULL_DOWN) {
344 nmk_chip->pull_up &= ~bit;
345 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
349 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
350 unsigned offset, bool lowemi)
352 u32 bit = BIT(offset);
353 bool enabled = nmk_chip->lowemi & bit;
355 if (lowemi == enabled)
359 nmk_chip->lowemi |= bit;
361 nmk_chip->lowemi &= ~bit;
363 writel_relaxed(nmk_chip->lowemi,
364 nmk_chip->addr + NMK_GPIO_LOWEMI);
367 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
370 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
373 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
374 unsigned offset, int val)
377 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
379 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
382 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
383 unsigned offset, int val)
385 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
386 __nmk_gpio_set_output(nmk_chip, offset, val);
389 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
390 unsigned offset, int gpio_mode,
393 u32 rwimsc = nmk_chip->rwimsc;
394 u32 fwimsc = nmk_chip->fwimsc;
396 if (glitch && nmk_chip->set_ioforce) {
397 u32 bit = BIT(offset);
399 /* Prevent spurious wakeups */
400 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
401 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
403 nmk_chip->set_ioforce(true);
406 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
408 if (glitch && nmk_chip->set_ioforce) {
409 nmk_chip->set_ioforce(false);
411 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
412 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
417 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
419 u32 falling = nmk_chip->fimsc & BIT(offset);
420 u32 rising = nmk_chip->rimsc & BIT(offset);
421 int gpio = nmk_chip->chip.base + offset;
422 int irq = irq_find_mapping(nmk_chip->domain, offset);
423 struct irq_data *d = irq_get_irq_data(irq);
425 if (!rising && !falling)
428 if (!d || !irqd_irq_disabled(d))
432 nmk_chip->rimsc &= ~BIT(offset);
433 writel_relaxed(nmk_chip->rimsc,
434 nmk_chip->addr + NMK_GPIO_RIMSC);
438 nmk_chip->fimsc &= ~BIT(offset);
439 writel_relaxed(nmk_chip->fimsc,
440 nmk_chip->addr + NMK_GPIO_FIMSC);
443 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
446 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
451 val = ((val & ~mask) | (value & mask));
455 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
456 unsigned offset, unsigned alt_num)
462 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
463 const u16 *gpiocr_regs;
465 if (!npct->prcm_base)
468 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
469 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
474 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
475 if (npct->soc->altcx_pins[i].pin == offset)
478 if (i == npct->soc->npins_altcx) {
479 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
484 pin_desc = npct->soc->altcx_pins + i;
485 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
488 * If alt_num is NULL, just clear current ALTCx selection
489 * to make sure we come back to a pure ALTC selection
492 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
493 if (pin_desc->altcx[i].used == true) {
494 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
495 bit = pin_desc->altcx[i].control_bit;
496 if (readl(npct->prcm_base + reg) & BIT(bit)) {
497 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
499 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
507 alt_index = alt_num - 1;
508 if (pin_desc->altcx[alt_index].used == false) {
510 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
516 * Check if any other ALTCx functions are activated on this pin
517 * and disable it first.
519 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
522 if (pin_desc->altcx[i].used == true) {
523 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
524 bit = pin_desc->altcx[i].control_bit;
525 if (readl(npct->prcm_base + reg) & BIT(bit)) {
526 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
528 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
534 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
535 bit = pin_desc->altcx[alt_index].control_bit;
536 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
537 offset, alt_index+1);
538 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
542 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
543 * - Save SLPM registers
544 * - Set SLPM=0 for the IOs you want to switch and others to 1
545 * - Configure the GPIO registers for the IOs that are being switched
547 * - Modify the AFLSA/B registers for the IOs that are being switched
549 * - Restore SLPM registers
550 * - Any spurious wake up event during switch sequence to be ignored and
553 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
557 for (i = 0; i < NUM_BANKS; i++) {
558 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
559 unsigned int temp = slpm[i];
564 clk_enable(chip->clk);
566 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
567 writel(temp, chip->addr + NMK_GPIO_SLPC);
571 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
575 for (i = 0; i < NUM_BANKS; i++) {
576 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
581 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
583 clk_disable(chip->clk);
587 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
592 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
593 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
594 const u16 *gpiocr_regs;
596 if (!npct->prcm_base)
597 return NMK_GPIO_ALT_C;
599 for (i = 0; i < npct->soc->npins_altcx; i++) {
600 if (npct->soc->altcx_pins[i].pin == gpio)
603 if (i == npct->soc->npins_altcx)
604 return NMK_GPIO_ALT_C;
606 pin_desc = npct->soc->altcx_pins + i;
607 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
608 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
609 if (pin_desc->altcx[i].used == true) {
610 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
611 bit = pin_desc->altcx[i].control_bit;
612 if (readl(npct->prcm_base + reg) & BIT(bit))
613 return NMK_GPIO_ALT_C+i+1;
616 return NMK_GPIO_ALT_C;
619 int nmk_gpio_get_mode(int gpio)
621 struct nmk_gpio_chip *nmk_chip;
622 u32 afunc, bfunc, bit;
624 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
628 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
630 clk_enable(nmk_chip->clk);
632 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
633 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
635 clk_disable(nmk_chip->clk);
637 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
639 EXPORT_SYMBOL(nmk_gpio_get_mode);
643 static inline int nmk_gpio_get_bitmask(int gpio)
645 return 1 << (gpio % NMK_GPIO_PER_CHIP);
648 static void nmk_gpio_irq_ack(struct irq_data *d)
650 struct nmk_gpio_chip *nmk_chip;
652 nmk_chip = irq_data_get_irq_chip_data(d);
656 clk_enable(nmk_chip->clk);
657 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
658 clk_disable(nmk_chip->clk);
661 enum nmk_gpio_irq_type {
666 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
667 int gpio, enum nmk_gpio_irq_type which,
670 u32 bitmask = nmk_gpio_get_bitmask(gpio);
676 if (which == NORMAL) {
677 rimscreg = NMK_GPIO_RIMSC;
678 fimscreg = NMK_GPIO_FIMSC;
679 rimscval = &nmk_chip->rimsc;
680 fimscval = &nmk_chip->fimsc;
682 rimscreg = NMK_GPIO_RWIMSC;
683 fimscreg = NMK_GPIO_FWIMSC;
684 rimscval = &nmk_chip->rwimsc;
685 fimscval = &nmk_chip->fwimsc;
688 /* we must individually set/clear the two edges */
689 if (nmk_chip->edge_rising & bitmask) {
691 *rimscval |= bitmask;
693 *rimscval &= ~bitmask;
694 writel(*rimscval, nmk_chip->addr + rimscreg);
696 if (nmk_chip->edge_falling & bitmask) {
698 *fimscval |= bitmask;
700 *fimscval &= ~bitmask;
701 writel(*fimscval, nmk_chip->addr + fimscreg);
705 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
709 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
710 * disabled, since setting SLPM to 1 increases power consumption, and
711 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
713 if (nmk_chip->sleepmode && on) {
714 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
715 NMK_GPIO_SLPM_WAKEUP_ENABLE);
718 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
721 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
723 struct nmk_gpio_chip *nmk_chip;
727 nmk_chip = irq_data_get_irq_chip_data(d);
728 bitmask = nmk_gpio_get_bitmask(d->hwirq);
732 clk_enable(nmk_chip->clk);
733 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
734 spin_lock(&nmk_chip->lock);
736 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
738 if (!(nmk_chip->real_wake & bitmask))
739 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
741 spin_unlock(&nmk_chip->lock);
742 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
743 clk_disable(nmk_chip->clk);
748 static void nmk_gpio_irq_mask(struct irq_data *d)
750 nmk_gpio_irq_maskunmask(d, false);
753 static void nmk_gpio_irq_unmask(struct irq_data *d)
755 nmk_gpio_irq_maskunmask(d, true);
758 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
760 struct nmk_gpio_chip *nmk_chip;
764 nmk_chip = irq_data_get_irq_chip_data(d);
767 bitmask = nmk_gpio_get_bitmask(d->hwirq);
769 clk_enable(nmk_chip->clk);
770 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
771 spin_lock(&nmk_chip->lock);
773 if (irqd_irq_disabled(d))
774 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
777 nmk_chip->real_wake |= bitmask;
779 nmk_chip->real_wake &= ~bitmask;
781 spin_unlock(&nmk_chip->lock);
782 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
783 clk_disable(nmk_chip->clk);
788 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
790 bool enabled = !irqd_irq_disabled(d);
791 bool wake = irqd_is_wakeup_set(d);
792 struct nmk_gpio_chip *nmk_chip;
796 nmk_chip = irq_data_get_irq_chip_data(d);
797 bitmask = nmk_gpio_get_bitmask(d->hwirq);
800 if (type & IRQ_TYPE_LEVEL_HIGH)
802 if (type & IRQ_TYPE_LEVEL_LOW)
805 clk_enable(nmk_chip->clk);
806 spin_lock_irqsave(&nmk_chip->lock, flags);
809 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
812 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
814 nmk_chip->edge_rising &= ~bitmask;
815 if (type & IRQ_TYPE_EDGE_RISING)
816 nmk_chip->edge_rising |= bitmask;
818 nmk_chip->edge_falling &= ~bitmask;
819 if (type & IRQ_TYPE_EDGE_FALLING)
820 nmk_chip->edge_falling |= bitmask;
823 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
826 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
828 spin_unlock_irqrestore(&nmk_chip->lock, flags);
829 clk_disable(nmk_chip->clk);
834 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
836 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
838 clk_enable(nmk_chip->clk);
839 nmk_gpio_irq_unmask(d);
843 static void nmk_gpio_irq_shutdown(struct irq_data *d)
845 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
847 nmk_gpio_irq_mask(d);
848 clk_disable(nmk_chip->clk);
851 static int nmk_gpio_irq_reqres(struct irq_data *d)
853 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
855 if (gpio_lock_as_irq(&nmk_chip->chip, d->hwirq)) {
856 dev_err(nmk_chip->chip.dev,
857 "unable to lock HW IRQ %lu for IRQ\n",
864 static void nmk_gpio_irq_relres(struct irq_data *d)
866 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
868 gpio_unlock_as_irq(&nmk_chip->chip, d->hwirq);
871 static struct irq_chip nmk_gpio_irq_chip = {
872 .name = "Nomadik-GPIO",
873 .irq_ack = nmk_gpio_irq_ack,
874 .irq_mask = nmk_gpio_irq_mask,
875 .irq_unmask = nmk_gpio_irq_unmask,
876 .irq_set_type = nmk_gpio_irq_set_type,
877 .irq_set_wake = nmk_gpio_irq_set_wake,
878 .irq_startup = nmk_gpio_irq_startup,
879 .irq_shutdown = nmk_gpio_irq_shutdown,
880 .irq_request_resources = nmk_gpio_irq_reqres,
881 .irq_release_resources = nmk_gpio_irq_relres,
882 .flags = IRQCHIP_MASK_ON_SUSPEND,
885 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
888 struct nmk_gpio_chip *nmk_chip;
889 struct irq_chip *host_chip = irq_get_chip(irq);
891 chained_irq_enter(host_chip, desc);
893 nmk_chip = irq_get_handler_data(irq);
895 int bit = __ffs(status);
897 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
901 chained_irq_exit(host_chip, desc);
904 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
906 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
909 clk_enable(nmk_chip->clk);
910 status = readl(nmk_chip->addr + NMK_GPIO_IS);
911 clk_disable(nmk_chip->clk);
913 __nmk_gpio_irq_handler(irq, desc, status);
916 static void nmk_gpio_latent_irq_handler(unsigned int irq,
917 struct irq_desc *desc)
919 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
920 u32 status = nmk_chip->get_latent_status(nmk_chip->bank);
922 __nmk_gpio_irq_handler(irq, desc, status);
925 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
927 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
928 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
930 if (nmk_chip->latent_parent_irq >= 0) {
931 irq_set_chained_handler(nmk_chip->latent_parent_irq,
932 nmk_gpio_latent_irq_handler);
933 irq_set_handler_data(nmk_chip->latent_parent_irq, nmk_chip);
941 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
944 * Map back to global GPIO space and request muxing, the direction
945 * parameter does not matter for this controller.
947 int gpio = chip->base + offset;
949 return pinctrl_request_gpio(gpio);
952 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
954 int gpio = chip->base + offset;
956 pinctrl_free_gpio(gpio);
959 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
961 struct nmk_gpio_chip *nmk_chip =
962 container_of(chip, struct nmk_gpio_chip, chip);
964 clk_enable(nmk_chip->clk);
966 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
968 clk_disable(nmk_chip->clk);
973 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
975 struct nmk_gpio_chip *nmk_chip =
976 container_of(chip, struct nmk_gpio_chip, chip);
977 u32 bit = 1 << offset;
980 clk_enable(nmk_chip->clk);
982 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
984 clk_disable(nmk_chip->clk);
989 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
992 struct nmk_gpio_chip *nmk_chip =
993 container_of(chip, struct nmk_gpio_chip, chip);
995 clk_enable(nmk_chip->clk);
997 __nmk_gpio_set_output(nmk_chip, offset, val);
999 clk_disable(nmk_chip->clk);
1002 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
1005 struct nmk_gpio_chip *nmk_chip =
1006 container_of(chip, struct nmk_gpio_chip, chip);
1008 clk_enable(nmk_chip->clk);
1010 __nmk_gpio_make_output(nmk_chip, offset, val);
1012 clk_disable(nmk_chip->clk);
1017 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1019 struct nmk_gpio_chip *nmk_chip =
1020 container_of(chip, struct nmk_gpio_chip, chip);
1022 return irq_create_mapping(nmk_chip->domain, offset);
1025 #ifdef CONFIG_DEBUG_FS
1027 #include <linux/seq_file.h>
1029 static void nmk_gpio_dbg_show_one(struct seq_file *s,
1030 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
1031 unsigned offset, unsigned gpio)
1033 const char *label = gpiochip_is_requested(chip, offset);
1034 struct nmk_gpio_chip *nmk_chip =
1035 container_of(chip, struct nmk_gpio_chip, chip);
1039 u32 bit = 1 << offset;
1040 const char *modes[] = {
1041 [NMK_GPIO_ALT_GPIO] = "gpio",
1042 [NMK_GPIO_ALT_A] = "altA",
1043 [NMK_GPIO_ALT_B] = "altB",
1044 [NMK_GPIO_ALT_C] = "altC",
1045 [NMK_GPIO_ALT_C+1] = "altC1",
1046 [NMK_GPIO_ALT_C+2] = "altC2",
1047 [NMK_GPIO_ALT_C+3] = "altC3",
1048 [NMK_GPIO_ALT_C+4] = "altC4",
1051 clk_enable(nmk_chip->clk);
1052 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1053 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1054 mode = nmk_gpio_get_mode(gpio);
1055 if ((mode == NMK_GPIO_ALT_C) && pctldev)
1056 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1058 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
1059 gpio, label ?: "(none)",
1060 is_out ? "out" : "in ",
1062 ? (chip->get(chip, offset) ? "hi" : "lo")
1064 (mode < 0) ? "unknown" : modes[mode],
1065 pull ? "pull" : "none");
1068 int irq = gpio_to_irq(gpio);
1069 struct irq_desc *desc = irq_to_desc(irq);
1071 /* This races with request_irq(), set_irq_type(),
1072 * and set_irq_wake() ... but those are "rare".
1074 if (irq > 0 && desc && desc->action) {
1076 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1078 if (nmk_chip->edge_rising & bitmask)
1079 trigger = "edge-rising";
1080 else if (nmk_chip->edge_falling & bitmask)
1081 trigger = "edge-falling";
1083 trigger = "edge-undefined";
1085 seq_printf(s, " irq-%d %s%s",
1087 irqd_is_wakeup_set(&desc->irq_data)
1091 clk_disable(nmk_chip->clk);
1094 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1097 unsigned gpio = chip->base;
1099 for (i = 0; i < chip->ngpio; i++, gpio++) {
1100 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1101 seq_printf(s, "\n");
1106 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1107 struct pinctrl_dev *pctldev,
1108 struct gpio_chip *chip,
1109 unsigned offset, unsigned gpio)
1112 #define nmk_gpio_dbg_show NULL
1115 /* This structure is replicated for each GPIO block allocated at probe time */
1116 static struct gpio_chip nmk_gpio_template = {
1117 .request = nmk_gpio_request,
1118 .free = nmk_gpio_free,
1119 .direction_input = nmk_gpio_make_input,
1120 .get = nmk_gpio_get_input,
1121 .direction_output = nmk_gpio_make_output,
1122 .set = nmk_gpio_set_output,
1123 .to_irq = nmk_gpio_to_irq,
1124 .dbg_show = nmk_gpio_dbg_show,
1128 void nmk_gpio_clocks_enable(void)
1132 for (i = 0; i < NUM_BANKS; i++) {
1133 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1138 clk_enable(chip->clk);
1142 void nmk_gpio_clocks_disable(void)
1146 for (i = 0; i < NUM_BANKS; i++) {
1147 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1152 clk_disable(chip->clk);
1157 * Called from the suspend/resume path to only keep the real wakeup interrupts
1158 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1159 * and not the rest of the interrupts which we needed to have as wakeups for
1162 * PM ops are not used since this needs to be done at the end, after all the
1163 * other drivers are done with their suspend callbacks.
1165 void nmk_gpio_wakeups_suspend(void)
1169 for (i = 0; i < NUM_BANKS; i++) {
1170 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1175 clk_enable(chip->clk);
1177 writel(chip->rwimsc & chip->real_wake,
1178 chip->addr + NMK_GPIO_RWIMSC);
1179 writel(chip->fwimsc & chip->real_wake,
1180 chip->addr + NMK_GPIO_FWIMSC);
1182 clk_disable(chip->clk);
1186 void nmk_gpio_wakeups_resume(void)
1190 for (i = 0; i < NUM_BANKS; i++) {
1191 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1196 clk_enable(chip->clk);
1198 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1199 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1201 clk_disable(chip->clk);
1206 * Read the pull up/pull down status.
1207 * A bit set in 'pull_up' means that pull up
1208 * is selected if pull is enabled in PDIS register.
1209 * Note: only pull up/down set via this driver can
1210 * be detected due to HW limitations.
1212 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1214 if (gpio_bank < NUM_BANKS) {
1215 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1220 *pull_up = chip->pull_up;
1224 static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1225 irq_hw_number_t hwirq)
1227 struct nmk_gpio_chip *nmk_chip = d->host_data;
1232 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1233 set_irq_flags(irq, IRQF_VALID);
1234 irq_set_chip_data(irq, nmk_chip);
1235 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1240 static const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1241 .map = nmk_gpio_irq_map,
1242 .xlate = irq_domain_xlate_twocell,
1245 static int nmk_gpio_probe(struct platform_device *dev)
1247 struct device_node *np = dev->dev.of_node;
1248 struct nmk_gpio_chip *nmk_chip;
1249 struct gpio_chip *chip;
1250 struct resource *res;
1253 bool supports_sleepmode;
1258 if (of_get_property(np, "st,supports-sleepmode", NULL))
1259 supports_sleepmode = true;
1261 supports_sleepmode = false;
1263 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1264 dev_err(&dev->dev, "gpio-bank property not found\n");
1268 irq = platform_get_irq(dev, 0);
1272 /* It's OK for this IRQ not to be present */
1273 latent_irq = platform_get_irq(dev, 1);
1275 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1276 base = devm_ioremap_resource(&dev->dev, res);
1278 return PTR_ERR(base);
1280 clk = devm_clk_get(&dev->dev, NULL);
1282 return PTR_ERR(clk);
1285 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1290 * The virt address in nmk_chip->addr is in the nomadik register space,
1291 * so we can simply convert the resource address, without remapping
1293 nmk_chip->bank = dev->id;
1294 nmk_chip->clk = clk;
1295 nmk_chip->addr = base;
1296 nmk_chip->chip = nmk_gpio_template;
1297 nmk_chip->parent_irq = irq;
1298 nmk_chip->latent_parent_irq = latent_irq;
1299 nmk_chip->sleepmode = supports_sleepmode;
1300 spin_lock_init(&nmk_chip->lock);
1302 chip = &nmk_chip->chip;
1303 chip->base = dev->id * NMK_GPIO_PER_CHIP;
1304 chip->ngpio = NMK_GPIO_PER_CHIP;
1305 chip->label = dev_name(&dev->dev);
1306 chip->dev = &dev->dev;
1307 chip->owner = THIS_MODULE;
1309 clk_enable(nmk_chip->clk);
1310 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1311 clk_disable(nmk_chip->clk);
1314 ret = gpiochip_add(&nmk_chip->chip);
1318 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1320 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1322 platform_set_drvdata(dev, nmk_chip);
1324 nmk_chip->domain = irq_domain_add_simple(np,
1325 NMK_GPIO_PER_CHIP, 0,
1326 &nmk_gpio_irq_simple_ops, nmk_chip);
1327 if (!nmk_chip->domain) {
1328 dev_err(&dev->dev, "failed to create irqdomain\n");
1329 /* Just do this, no matter if it fails */
1330 ret = gpiochip_remove(&nmk_chip->chip);
1334 nmk_gpio_init_irq(nmk_chip);
1336 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1341 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1343 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1345 return npct->soc->ngroups;
1348 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1351 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1353 return npct->soc->groups[selector].name;
1356 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1357 const unsigned **pins,
1360 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1362 *pins = npct->soc->groups[selector].pins;
1363 *num_pins = npct->soc->groups[selector].npins;
1367 static struct pinctrl_gpio_range *
1368 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1370 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1373 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1374 struct pinctrl_gpio_range *range;
1376 range = &npct->soc->gpio_ranges[i];
1377 if (offset >= range->pin_base &&
1378 offset <= (range->pin_base + range->npins - 1))
1384 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1387 struct pinctrl_gpio_range *range;
1388 struct gpio_chip *chip;
1390 range = nmk_match_gpio_range(pctldev, offset);
1391 if (!range || !range->gc) {
1392 seq_printf(s, "invalid pin offset");
1396 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1399 static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1400 struct pinctrl_map *map, unsigned num_maps)
1404 for (i = 0; i < num_maps; i++)
1405 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1406 kfree(map[i].data.configs.configs);
1410 static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
1411 unsigned *num_maps, unsigned reserve)
1413 unsigned old_num = *reserved_maps;
1414 unsigned new_num = *num_maps + reserve;
1415 struct pinctrl_map *new_map;
1417 if (old_num >= new_num)
1420 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1424 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1427 *reserved_maps = new_num;
1432 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1433 unsigned *num_maps, const char *group,
1434 const char *function)
1436 if (*num_maps == *reserved_maps)
1439 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1440 (*map)[*num_maps].data.mux.group = group;
1441 (*map)[*num_maps].data.mux.function = function;
1447 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1448 unsigned *reserved_maps,
1449 unsigned *num_maps, const char *group,
1450 unsigned long *configs, unsigned num_configs)
1452 unsigned long *dup_configs;
1454 if (*num_maps == *reserved_maps)
1457 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1462 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1464 (*map)[*num_maps].data.configs.group_or_pin = group;
1465 (*map)[*num_maps].data.configs.configs = dup_configs;
1466 (*map)[*num_maps].data.configs.num_configs = num_configs;
1472 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1473 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1474 .size = ARRAY_SIZE(y), }
1476 static const unsigned long nmk_pin_input_modes[] = {
1482 static const unsigned long nmk_pin_output_modes[] = {
1488 static const unsigned long nmk_pin_sleep_modes[] = {
1489 PIN_SLEEPMODE_DISABLED,
1490 PIN_SLEEPMODE_ENABLED,
1493 static const unsigned long nmk_pin_sleep_input_modes[] = {
1494 PIN_SLPM_INPUT_NOPULL,
1495 PIN_SLPM_INPUT_PULLUP,
1496 PIN_SLPM_INPUT_PULLDOWN,
1500 static const unsigned long nmk_pin_sleep_output_modes[] = {
1501 PIN_SLPM_OUTPUT_LOW,
1502 PIN_SLPM_OUTPUT_HIGH,
1503 PIN_SLPM_DIR_OUTPUT,
1506 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1507 PIN_SLPM_WAKEUP_DISABLE,
1508 PIN_SLPM_WAKEUP_ENABLE,
1511 static const unsigned long nmk_pin_gpio_modes[] = {
1512 PIN_GPIOMODE_DISABLED,
1513 PIN_GPIOMODE_ENABLED,
1516 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1517 PIN_SLPM_PDIS_DISABLED,
1518 PIN_SLPM_PDIS_ENABLED,
1521 struct nmk_cfg_param {
1522 const char *property;
1523 unsigned long config;
1524 const unsigned long *choice;
1528 static const struct nmk_cfg_param nmk_cfg_params[] = {
1529 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1530 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1531 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1532 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1533 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1534 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1535 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1536 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1539 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1543 if (nmk_cfg_params[index].choice == NULL)
1544 *config = nmk_cfg_params[index].config;
1546 /* test if out of range */
1547 if (val < nmk_cfg_params[index].size) {
1548 *config = nmk_cfg_params[index].config |
1549 nmk_cfg_params[index].choice[val];
1555 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1558 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1560 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1561 for (i = 0; i < npct->soc->npins; i++)
1562 if (npct->soc->pins[i].number == pin_number)
1563 return npct->soc->pins[i].name;
1567 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1568 unsigned long *configs)
1570 bool has_config = 0;
1571 unsigned long cfg = 0;
1574 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1575 ret = of_property_read_u32(np,
1576 nmk_cfg_params[i].property, &val);
1577 if (ret != -EINVAL) {
1578 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1588 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1589 struct device_node *np,
1590 struct pinctrl_map **map,
1591 unsigned *reserved_maps,
1595 const char *function = NULL;
1596 unsigned long configs = 0;
1597 bool has_config = 0;
1598 unsigned reserve = 0;
1599 struct property *prop;
1600 const char *group, *gpio_name;
1601 struct device_node *np_config;
1603 ret = of_property_read_string(np, "ste,function", &function);
1607 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1609 np_config = of_parse_phandle(np, "ste,config", 0);
1611 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1613 ret = of_property_count_strings(np, "ste,pins");
1622 ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
1626 of_property_for_each_string(np, "ste,pins", prop, group) {
1628 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1634 gpio_name = nmk_find_pin_name(pctldev, group);
1636 ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
1637 gpio_name, &configs, 1);
1647 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1648 struct device_node *np_config,
1649 struct pinctrl_map **map, unsigned *num_maps)
1651 unsigned reserved_maps;
1652 struct device_node *np;
1659 for_each_child_of_node(np_config, np) {
1660 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1661 &reserved_maps, num_maps);
1663 nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
1671 static const struct pinctrl_ops nmk_pinctrl_ops = {
1672 .get_groups_count = nmk_get_groups_cnt,
1673 .get_group_name = nmk_get_group_name,
1674 .get_group_pins = nmk_get_group_pins,
1675 .pin_dbg_show = nmk_pin_dbg_show,
1676 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1677 .dt_free_map = nmk_pinctrl_dt_free_map,
1680 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1682 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1684 return npct->soc->nfunctions;
1687 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1690 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1692 return npct->soc->functions[function].name;
1695 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1697 const char * const **groups,
1698 unsigned * const num_groups)
1700 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1702 *groups = npct->soc->functions[function].groups;
1703 *num_groups = npct->soc->functions[function].ngroups;
1708 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1711 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1712 const struct nmk_pingroup *g;
1713 static unsigned int slpm[NUM_BANKS];
1714 unsigned long flags = 0;
1719 g = &npct->soc->groups[group];
1721 if (g->altsetting < 0)
1724 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1727 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1728 * we may pass through an undesired state. In this case we take
1731 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1732 * - Save SLPM registers (since we have a shadow register in the
1733 * nmk_chip we're using that as backup)
1734 * - Set SLPM=0 for the IOs you want to switch and others to 1
1735 * - Configure the GPIO registers for the IOs that are being switched
1737 * - Modify the AFLSA/B registers for the IOs that are being switched
1739 * - Restore SLPM registers
1740 * - Any spurious wake up event during switch sequence to be ignored
1743 * We REALLY need to save ALL slpm registers, because the external
1744 * IOFORCE will switch *all* ports to their sleepmode setting to as
1745 * to avoid glitches. (Not just one port!)
1747 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1750 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1752 /* Initially don't put any pins to sleep when switching */
1753 memset(slpm, 0xff, sizeof(slpm));
1756 * Then mask the pins that need to be sleeping now when we're
1757 * switching to the ALT C function.
1759 for (i = 0; i < g->npins; i++)
1760 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1761 nmk_gpio_glitch_slpm_init(slpm);
1764 for (i = 0; i < g->npins; i++) {
1765 struct pinctrl_gpio_range *range;
1766 struct nmk_gpio_chip *nmk_chip;
1767 struct gpio_chip *chip;
1770 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1773 "invalid pin offset %d in group %s at index %d\n",
1774 g->pins[i], g->name, i);
1778 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1779 g->pins[i], g->name, i);
1783 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1784 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1786 clk_enable(nmk_chip->clk);
1787 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1789 * If the pin is switching to altfunc, and there was an
1790 * interrupt installed on it which has been lazy disabled,
1791 * actually mask the interrupt to prevent spurious interrupts
1792 * that would occur while the pin is under control of the
1793 * peripheral. Only SKE does this.
1795 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1797 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1798 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1799 clk_disable(nmk_chip->clk);
1802 * Call PRCM GPIOCR config function in case ALTC
1803 * has been selected:
1804 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1806 * - If selection is pure ALTC and previous selection was ALTCx,
1807 * then some bits in PRCM GPIOCR registers must be cleared.
1809 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1810 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1811 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1814 /* When all pins are successfully reconfigured we get here */
1819 nmk_gpio_glitch_slpm_restore(slpm);
1820 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1826 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1827 unsigned function, unsigned group)
1829 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1830 const struct nmk_pingroup *g;
1832 g = &npct->soc->groups[group];
1834 if (g->altsetting < 0)
1837 /* Poke out the mux, set the pin to some default state? */
1838 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1841 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1842 struct pinctrl_gpio_range *range,
1845 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1846 struct nmk_gpio_chip *nmk_chip;
1847 struct gpio_chip *chip;
1851 dev_err(npct->dev, "invalid range\n");
1855 dev_err(npct->dev, "missing GPIO chip in range\n");
1859 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1861 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1863 clk_enable(nmk_chip->clk);
1864 bit = offset % NMK_GPIO_PER_CHIP;
1865 /* There is no glitch when converting any pin to GPIO */
1866 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1867 clk_disable(nmk_chip->clk);
1872 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1873 struct pinctrl_gpio_range *range,
1876 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1878 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1879 /* Set the pin to some default state, GPIO is usually default */
1882 static const struct pinmux_ops nmk_pinmux_ops = {
1883 .get_functions_count = nmk_pmx_get_funcs_cnt,
1884 .get_function_name = nmk_pmx_get_func_name,
1885 .get_function_groups = nmk_pmx_get_func_groups,
1886 .enable = nmk_pmx_enable,
1887 .disable = nmk_pmx_disable,
1888 .gpio_request_enable = nmk_gpio_request_enable,
1889 .gpio_disable_free = nmk_gpio_disable_free,
1892 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1893 unsigned long *config)
1895 /* Not implemented */
1899 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1900 unsigned long *configs, unsigned num_configs)
1902 static const char *pullnames[] = {
1903 [NMK_GPIO_PULL_NONE] = "none",
1904 [NMK_GPIO_PULL_UP] = "up",
1905 [NMK_GPIO_PULL_DOWN] = "down",
1906 [3] /* illegal */ = "??"
1908 static const char *slpmnames[] = {
1909 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1910 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1912 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1913 struct nmk_gpio_chip *nmk_chip;
1914 struct pinctrl_gpio_range *range;
1915 struct gpio_chip *chip;
1918 int pull, slpm, output, val, i;
1919 bool lowemi, gpiomode, sleep;
1921 range = nmk_match_gpio_range(pctldev, pin);
1923 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1927 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1932 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1934 for (i = 0; i < num_configs; i++) {
1936 * The pin config contains pin number and altfunction fields,
1937 * here we just ignore that part. It's being handled by the
1938 * framework and pinmux callback respectively.
1940 cfg = (pin_cfg_t) configs[i];
1941 pull = PIN_PULL(cfg);
1942 slpm = PIN_SLPM(cfg);
1943 output = PIN_DIR(cfg);
1945 lowemi = PIN_LOWEMI(cfg);
1946 gpiomode = PIN_GPIOMODE(cfg);
1947 sleep = PIN_SLEEPMODE(cfg);
1950 int slpm_pull = PIN_SLPM_PULL(cfg);
1951 int slpm_output = PIN_SLPM_DIR(cfg);
1952 int slpm_val = PIN_SLPM_VAL(cfg);
1954 /* All pins go into GPIO mode at sleep */
1958 * The SLPM_* values are normal values + 1 to allow zero
1959 * to mean "same as normal".
1962 pull = slpm_pull - 1;
1964 output = slpm_output - 1;
1968 dev_dbg(nmk_chip->chip.dev,
1969 "pin %d: sleep pull %s, dir %s, val %s\n",
1971 slpm_pull ? pullnames[pull] : "same",
1972 slpm_output ? (output ? "output" : "input")
1974 slpm_val ? (val ? "high" : "low") : "same");
1977 dev_dbg(nmk_chip->chip.dev,
1978 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1979 pin, cfg, pullnames[pull], slpmnames[slpm],
1980 output ? "output " : "input",
1981 output ? (val ? "high" : "low") : "",
1982 lowemi ? "on" : "off");
1984 clk_enable(nmk_chip->clk);
1985 bit = pin % NMK_GPIO_PER_CHIP;
1987 /* No glitch when going to GPIO mode */
1988 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1990 __nmk_gpio_make_output(nmk_chip, bit, val);
1992 __nmk_gpio_make_input(nmk_chip, bit);
1993 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1995 /* TODO: isn't this only applicable on output pins? */
1996 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1998 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1999 clk_disable(nmk_chip->clk);
2000 } /* for each config */
2005 static const struct pinconf_ops nmk_pinconf_ops = {
2006 .pin_config_get = nmk_pin_config_get,
2007 .pin_config_set = nmk_pin_config_set,
2010 static struct pinctrl_desc nmk_pinctrl_desc = {
2011 .name = "pinctrl-nomadik",
2012 .pctlops = &nmk_pinctrl_ops,
2013 .pmxops = &nmk_pinmux_ops,
2014 .confops = &nmk_pinconf_ops,
2015 .owner = THIS_MODULE,
2018 static const struct of_device_id nmk_pinctrl_match[] = {
2020 .compatible = "stericsson,stn8815-pinctrl",
2021 .data = (void *)PINCTRL_NMK_STN8815,
2024 .compatible = "stericsson,db8500-pinctrl",
2025 .data = (void *)PINCTRL_NMK_DB8500,
2028 .compatible = "stericsson,db8540-pinctrl",
2029 .data = (void *)PINCTRL_NMK_DB8540,
2034 static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
2036 struct nmk_pinctrl *npct;
2038 npct = platform_get_drvdata(pdev);
2042 return pinctrl_force_sleep(npct->pctl);
2045 static int nmk_pinctrl_resume(struct platform_device *pdev)
2047 struct nmk_pinctrl *npct;
2049 npct = platform_get_drvdata(pdev);
2053 return pinctrl_force_default(npct->pctl);
2056 static int nmk_pinctrl_probe(struct platform_device *pdev)
2058 const struct of_device_id *match;
2059 struct device_node *np = pdev->dev.of_node;
2060 struct device_node *prcm_np;
2061 struct nmk_pinctrl *npct;
2062 unsigned int version = 0;
2065 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
2069 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
2072 version = (unsigned int) match->data;
2074 /* Poke in other ASIC variants here */
2075 if (version == PINCTRL_NMK_STN8815)
2076 nmk_pinctrl_stn8815_init(&npct->soc);
2077 if (version == PINCTRL_NMK_DB8500)
2078 nmk_pinctrl_db8500_init(&npct->soc);
2079 if (version == PINCTRL_NMK_DB8540)
2080 nmk_pinctrl_db8540_init(&npct->soc);
2082 prcm_np = of_parse_phandle(np, "prcm", 0);
2084 npct->prcm_base = of_iomap(prcm_np, 0);
2085 if (!npct->prcm_base) {
2086 if (version == PINCTRL_NMK_STN8815) {
2087 dev_info(&pdev->dev,
2089 "assuming no ALT-Cx control is available\n");
2091 dev_err(&pdev->dev, "missing PRCM base address\n");
2097 * We need all the GPIO drivers to probe FIRST, or we will not be able
2098 * to obtain references to the struct gpio_chip * for them, and we
2099 * need this to proceed.
2101 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
2102 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
2103 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
2104 return -EPROBE_DEFER;
2106 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
2109 nmk_pinctrl_desc.pins = npct->soc->pins;
2110 nmk_pinctrl_desc.npins = npct->soc->npins;
2111 npct->dev = &pdev->dev;
2113 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
2115 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
2119 /* We will handle a range of GPIO pins */
2120 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
2121 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
2123 platform_set_drvdata(pdev, npct);
2124 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
2129 static const struct of_device_id nmk_gpio_match[] = {
2130 { .compatible = "st,nomadik-gpio", },
2134 static struct platform_driver nmk_gpio_driver = {
2136 .owner = THIS_MODULE,
2138 .of_match_table = nmk_gpio_match,
2140 .probe = nmk_gpio_probe,
2143 static struct platform_driver nmk_pinctrl_driver = {
2145 .owner = THIS_MODULE,
2146 .name = "pinctrl-nomadik",
2147 .of_match_table = nmk_pinctrl_match,
2149 .probe = nmk_pinctrl_probe,
2151 .suspend = nmk_pinctrl_suspend,
2152 .resume = nmk_pinctrl_resume,
2156 static int __init nmk_gpio_init(void)
2160 ret = platform_driver_register(&nmk_gpio_driver);
2163 return platform_driver_register(&nmk_pinctrl_driver);
2166 core_initcall(nmk_gpio_init);
2168 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
2169 MODULE_DESCRIPTION("Nomadik GPIO Driver");
2170 MODULE_LICENSE("GPL");