drivers/pinctrl/pinctrl-rk3368.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/bitops.h>
  31 #include <linux/gpio.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_irq.h>
  34 #include <linux/pinctrl/machine.h>
  35 #include <linux/pinctrl/pinconf.h>
  36 #include <linux/pinctrl/pinctrl.h>
  37 #include <linux/pinctrl/pinmux.h>
  38 #include <linux/pinctrl/pinconf-generic.h>
  39 #include <linux/irqchip/chained_irq.h>
  40 #include <linux/clk.h>
  41 #include <linux/regmap.h>
  42 #include <linux/mfd/syscon.h>
  43 #include <linux/syscore_ops.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45
  46 #include "core.h"
  47 #include "pinconf.h"
  48
  49
  50 #if 0
  51 #define pinctrl_dbg(dev, format, arg...)            \
  52         dev_printk(KERN_INFO , dev , format , ## arg)
  53 #else
  54 #define pinctrl_dbg(dev, format, arg...)
  55 #endif
  56
  57
  58 /* GPIO control registers */
  59 #define GPIO_SWPORT_DR          0x00
  60 #define GPIO_SWPORT_DDR         0x04
  61 #define GPIO_INTEN              0x30
  62 #define GPIO_INTMASK            0x34
  63 #define GPIO_INTTYPE_LEVEL      0x38
  64 #define GPIO_INT_POLARITY       0x3c
  65 #define GPIO_INT_STATUS         0x40
  66 #define GPIO_INT_RAWSTATUS      0x44
  67 #define GPIO_DEBOUNCE           0x48
  68 #define GPIO_PORTS_EOI          0x4c
  69 #define GPIO_EXT_PORT           0x50
  70 #define GPIO_LS_SYNC            0x60
  71
  72 enum rockchip_pinctrl_type {
  73         RK2928,
  74         RK3066B,
  75         RK3188,
  76         RK3288,
  77         RK3368,
  78 };
  79
  80 /**
  81  * Encode variants of iomux registers into a type variable
  82  */
  83 #define IOMUX_GPIO_ONLY         BIT(0)
  84 #define IOMUX_WIDTH_4BIT        BIT(1)
  85 #define IOMUX_SOURCE_PMU        BIT(2)
  86 #define IOMUX_UNROUTED          BIT(3)
  87
  88 /**
  89  * @type: iomux variant using IOMUX_* constants
  90  * @offset: if initialized to -1 it will be autocalculated, by specifying
  91  *          an initial offset value the relevant source offset can be reset
  92  *          to a new value for autocalculating the following iomux registers.
  93  */
  94 struct rockchip_iomux {
  95         int                             type;
  96         int                             offset;
  97 };
  98
  99 /**
 100  * @reg_base: register base of the gpio bank
 101  * @reg_pull: optional separate register for additional pull settings
 102  * @clk: clock of the gpio bank
 103  * @irq: interrupt of the gpio bank
 104  * @pin_base: first pin number
 105  * @nr_pins: number of pins in this bank
 106  * @name: name of the bank
 107  * @bank_num: number of the bank, to account for holes
 108  * @iomux: array describing the 4 iomux sources of the bank
 109  * @valid: are all necessary informations present
 110  * @of_node: dt node of this bank
 111  * @drvdata: common pinctrl basedata
 112  * @domain: irqdomain of the gpio bank
 113  * @gpio_chip: gpiolib chip
 114  * @grange: gpio range
 115  * @slock: spinlock for the gpio bank
 116  */
 117 struct rockchip_pin_bank {
 118         void __iomem                    *reg_base;
 119         struct regmap                   *regmap_pull;
 120         struct clk                      *clk;
 121         int                             irq;
 122         u32                             pin_base;
 123         u8                              nr_pins;
 124         char                            *name;
 125         u8                              bank_num;
 126         struct rockchip_iomux           iomux[4];
 127         bool                            valid;
 128         struct device_node              *of_node;
 129         struct rockchip_pinctrl         *drvdata;
 130         struct irq_domain               *domain;
 131         struct gpio_chip                gpio_chip;
 132         struct pinctrl_gpio_range       grange;
 133         spinlock_t                      slock;
 134         u32                             toggle_edge_mode;
 135         u32                             suspend_wakeup;
 136         u32                             saved_wakeup;
 137 };
 138
 139 #define PIN_BANK(id, pins, label)                       \
 140         {                                               \
 141                 .bank_num       = id,                   \
 142                 .nr_pins        = pins,                 \
 143                 .name           = label,                \
 144                 .iomux          = {                     \
 145                         { .offset = -1 },               \
 146                         { .offset = -1 },               \
 147                         { .offset = -1 },               \
 148                         { .offset = -1 },               \
 149                 },                                      \
 150         }
 151
 152 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 153         {                                                               \
 154                 .bank_num       = id,                                   \
 155                 .nr_pins        = pins,                                 \
 156                 .name           = label,                                \
 157                 .iomux          = {                                     \
 158                         { .type = iom0, .offset = -1 },                 \
 159                         { .type = iom1, .offset = -1 },                 \
 160                         { .type = iom2, .offset = -1 },                 \
 161                         { .type = iom3, .offset = -1 },                 \
 162                 },                                                      \
 163         }
 164
 165 /**
 166  */
 167 struct rockchip_pin_ctrl {
 168         struct rockchip_pin_bank        *pin_banks;
 169         u32                             nr_banks;
 170         u32                             nr_pins;
 171         char                            *label;
 172         enum rockchip_pinctrl_type      type;
 173         int                             grf_mux_offset;
 174         int                             pmu_mux_offset;
 175         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 176                                     int pin_num, struct regmap **regmap,
 177                                     int *reg, u8 *bit);
 178 };
 179
 180 struct rockchip_pin_config {
 181         unsigned int            func;
 182         unsigned long           *configs;
 183         unsigned int            nconfigs;
 184 };
 185
 186 /**
 187  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 188  * @name: name of the pin group, used to lookup the group.
 189  * @pins: the pins included in this group.
 190  * @npins: number of pins included in this group.
 191  * @func: the mux function number to be programmed when selected.
 192  * @configs: the config values to be set for each pin
 193  * @nconfigs: number of configs for each pin
 194  */
 195 struct rockchip_pin_group {
 196         const char                      *name;
 197         unsigned int                    npins;
 198         unsigned int                    *pins;
 199         struct rockchip_pin_config      *data;
 200 };
 201
 202 /**
 203  * struct rockchip_pmx_func: represent a pin function.
 204  * @name: name of the pin function, used to lookup the function.
 205  * @groups: one or more names of pin groups that provide this function.
 206  * @num_groups: number of groups included in @groups.
 207  */
 208 struct rockchip_pmx_func {
 209         const char              *name;
 210         const char              **groups;
 211         u8                      ngroups;
 212 };
 213
 214 struct rockchip_pinctrl {
 215         struct regmap                   *regmap_base;
 216         int                             reg_size;
 217         struct regmap                   *regmap_pull;
 218         struct regmap                   *regmap_pmu;
 219         struct device                   *dev;
 220         struct rockchip_pin_ctrl        *ctrl;
 221         struct pinctrl_desc             pctl;
 222         struct pinctrl_dev              *pctl_dev;
 223         struct rockchip_pin_group       *groups;
 224         unsigned int                    ngroups;
 225         struct rockchip_pmx_func        *functions;
 226         unsigned int                    nfunctions;
 227 };
 228
 229 static struct regmap_config rockchip_regmap_config = {
 230         .reg_bits = 32,
 231         .val_bits = 32,
 232         .reg_stride = 4,
 233 };
 234 static struct rockchip_pinctrl *g_info;
 235
 236 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 237 {
 238         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 239 }
 240
 241 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 242                                         const struct rockchip_pinctrl *info,
 243                                         const char *name)
 244 {
 245         int i;
 246
 247         for (i = 0; i < info->ngroups; i++) {
 248                 if (!strcmp(info->groups[i].name, name))
 249                         return &info->groups[i];
 250         }
 251
 252         return NULL;
 253 }
 254
 255 /*
 256  * given a pin number that is local to a pin controller, find out the pin bank
 257  * and the register base of the pin bank.
 258  */
 259 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 260                                                                 unsigned pin)
 261 {
 262         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 263
 264         while (pin >= (b->pin_base + b->nr_pins))
 265                 b++;
 266
 267         return b;
 268 }
 269
 270 static struct rockchip_pin_bank *bank_num_to_bank(
 271                                         struct rockchip_pinctrl *info,
 272                                         unsigned num)
 273 {
 274         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 275         int i;
 276
 277         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 278                 if (b->bank_num == num)
 279                         return b;
 280         }
 281
 282         return ERR_PTR(-EINVAL);
 283 }
 284
 285 /*
 286  * Pinctrl_ops handling
 287  */
 288
 289 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 290 {
 291         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 292
 293         return info->ngroups;
 294 }
 295
 296 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 297                                                         unsigned selector)
 298 {
 299         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 300
 301         return info->groups[selector].name;
 302 }
 303
 304 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 305                                       unsigned selector, const unsigned **pins,
 306                                       unsigned *npins)
 307 {
 308         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 309
 310         if (selector >= info->ngroups)
 311                 return -EINVAL;
 312
 313         *pins = info->groups[selector].pins;
 314         *npins = info->groups[selector].npins;
 315
 316         return 0;
 317 }
 318
 319 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 320                                  struct device_node *np,
 321                                  struct pinctrl_map **map, unsigned *num_maps)
 322 {
 323         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 324         const struct rockchip_pin_group *grp;
 325         struct pinctrl_map *new_map;
 326         struct device_node *parent;
 327         int map_num = 1;
 328         int i;
 329
 330         /*
 331          * first find the group of this node and check if we need to create
 332          * config maps for pins
 333          */
 334         grp = pinctrl_name_to_group(info, np->name);
 335         if (!grp) {
 336                 dev_err(info->dev, "unable to find group for node %s\n",
 337                         np->name);
 338                 return -EINVAL;
 339         }
 340
 341         map_num += grp->npins;
 342         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 343                                                                 GFP_KERNEL);
 344         if (!new_map)
 345                 return -ENOMEM;
 346
 347         *map = new_map;
 348         *num_maps = map_num;
 349
 350         /* create mux map */
 351         parent = of_get_parent(np);
 352         if (!parent) {
 353                 devm_kfree(pctldev->dev, new_map);
 354                 return -EINVAL;
 355         }
 356         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 357         new_map[0].data.mux.function = parent->name;
 358         new_map[0].data.mux.group = np->name;
 359         of_node_put(parent);
 360
 361         /* create config map */
 362         new_map++;
 363         for (i = 0; i < grp->npins; i++) {
 364                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 365                 new_map[i].data.configs.group_or_pin =
 366                                 pin_get_name(pctldev, grp->pins[i]);
 367                 new_map[i].data.configs.configs = grp->data[i].configs;
 368                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 369         }
 370
 371         pinctrl_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 372                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 373
 374         return 0;
 375 }
 376
 377 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 378                                     struct pinctrl_map *map, unsigned num_maps)
 379 {
 380 }
 381
 382 static const struct pinctrl_ops rockchip_pctrl_ops = {
 383         .get_groups_count       = rockchip_get_groups_count,
 384         .get_group_name         = rockchip_get_group_name,
 385         .get_group_pins         = rockchip_get_group_pins,
 386         .dt_node_to_map         = rockchip_dt_node_to_map,
 387         .dt_free_map            = rockchip_dt_free_map,
 388 };
 389
 390 /*
 391  * Hardware access
 392  */
 393
 394 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 395 {
 396         struct rockchip_pinctrl *info = bank->drvdata;
 397         int iomux_num = (pin / 8);
 398         struct regmap *regmap;
 399         unsigned int val;
 400         int reg, ret, mask;
 401         u8 bit;
 402
 403         if (iomux_num > 3)
 404                 return -EINVAL;
 405
 406         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 407                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 408                 return -EINVAL;
 409         }
 410
 411         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 412                 return RK_FUNC_GPIO;
 413
 414         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 415                                 ? info->regmap_pmu : info->regmap_base;
 416
 417         /* get basic quadrupel of mux registers and the correct reg inside */
 418         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 419         reg = bank->iomux[iomux_num].offset;
 420         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 421                 if ((pin % 8) >= 4)
 422                         reg += 0x4;
 423                 bit = (pin % 4) * 4;
 424         } else {
 425                 bit = (pin % 8) * 2;
 426         }
 427
 428         ret = regmap_read(regmap, reg, &val);
 429         if (ret)
 430                 return ret;
 431
 432         return ((val >> bit) & mask);
 433 }
 434
 435 /*
 436  * Set a new mux function for a pin.
 437  *
 438  * The register is divided into the upper and lower 16 bit. When changing
 439  * a value, the previous register value is not read and changed. Instead
 440  * it seems the changed bits are marked in the upper 16 bit, while the
 441  * changed value gets set in the same offset in the lower 16 bit.
 442  * All pin settings seem to be 2 bit wide in both the upper and lower
 443  * parts.
 444  * @bank: pin bank to change
 445  * @pin: pin to change
 446  * @mux: new mux function to set
 447  */
 448 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 449 {
 450         struct rockchip_pinctrl *info = bank->drvdata;
 451         int iomux_num = (pin / 8);
 452         struct regmap *regmap;
 453         int reg, ret, mask;
 454         unsigned long flags;
 455         u8 bit;
 456         u32 data, rmask;
 457
 458         if (iomux_num > 3)
 459                 return -EINVAL;
 460
 461         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 462                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 463                 return -EINVAL;
 464         }
 465
 466         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 467                 if (mux != RK_FUNC_GPIO) {
 468                         dev_err(info->dev,
 469                                 "pin %d only supports a gpio mux\n", pin);
 470                         return -ENOTSUPP;
 471                 } else {
 472                         return 0;
 473                 }
 474         }
 475
 476         pinctrl_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 477                                                 bank->bank_num, pin, mux);
 478
 479         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 480                                 ? info->regmap_pmu : info->regmap_base;
 481
 482         /* get basic quadrupel of mux registers and the correct reg inside */
 483         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 484         reg = bank->iomux[iomux_num].offset;
 485         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 486                 if ((pin % 8) >= 4)
 487                         reg += 0x4;
 488                 bit = (pin % 4) * 4;
 489         } else {
 490                 bit = (pin % 8) * 2;
 491         }
 492
 493         spin_lock_irqsave(&bank->slock, flags);
 494
 495         data = (mask << (bit + 16));
 496         rmask = data | (data >> 16);
 497         data |= (mux & mask) << bit;
 498         ret = regmap_update_bits(regmap, reg, rmask, data);
 499
 500         spin_unlock_irqrestore(&bank->slock, flags);
 501
 502         return ret;
 503 }
 504
 505 #define RK2928_PULL_OFFSET              0x118
 506 #define RK2928_PULL_PINS_PER_REG        16
 507 #define RK2928_PULL_BANK_STRIDE         8
 508
 509 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 510                                     int pin_num, struct regmap **regmap,
 511                                     int *reg, u8 *bit)
 512 {
 513         struct rockchip_pinctrl *info = bank->drvdata;
 514
 515         *regmap = info->regmap_base;
 516         *reg = RK2928_PULL_OFFSET;
 517         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 518         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 519
 520         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 521 };
 522
 523 #define RK3188_PULL_OFFSET              0x164
 524 #define RK3188_PULL_BITS_PER_PIN        2
 525 #define RK3188_PULL_PINS_PER_REG        8
 526 #define RK3188_PULL_BANK_STRIDE         16
 527 #define RK3188_PULL_PMU_OFFSET          0x64
 528
 529 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 530                                     int pin_num, struct regmap **regmap,
 531                                     int *reg, u8 *bit)
 532 {
 533         struct rockchip_pinctrl *info = bank->drvdata;
 534
 535         /* The first 12 pins of the first bank are located elsewhere */
 536         if (bank->bank_num == 0 && pin_num < 12) {
 537                 *regmap = info->regmap_pmu ? info->regmap_pmu
 538                                            : bank->regmap_pull;
 539                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
 540                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 541                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 542                 *bit *= RK3188_PULL_BITS_PER_PIN;
 543         } else {
 544                 *regmap = info->regmap_pull ? info->regmap_pull
 545                                             : info->regmap_base;
 546                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
 547
 548                 /* correct the offset, as it is the 2nd pull register */
 549                 *reg -= 4;
 550                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 551                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 552
 553                 /*
 554                  * The bits in these registers have an inverse ordering
 555                  * with the lowest pin being in bits 15:14 and the highest
 556                  * pin in bits 1:0
 557                  */
 558                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 559                 *bit *= RK3188_PULL_BITS_PER_PIN;
 560         }
 561 }
 562
 563 #define RK3288_PULL_OFFSET              0x140
 564 #define RK3368_PULL_PMU_OFFSET 0x10
 565 #define RK3368_PULL_OFFSET              0x100
 566
 567 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 568                                     int pin_num, struct regmap **regmap,
 569                                     int *reg, u8 *bit)
 570 {
 571         struct rockchip_pinctrl *info = bank->drvdata;
 572         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 573
 574         /* The first 24 pins of the first bank are located in PMU */
 575         if (bank->bank_num == 0) {
 576                 *regmap = info->regmap_pmu;
 577                 if(ctrl->type == RK3288)
 578                         *reg = RK3188_PULL_PMU_OFFSET;
 579                 else if (ctrl->type == RK3368)
 580                         *reg = RK3368_PULL_PMU_OFFSET;
 581
 582                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 583                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 584                 *bit *= RK3188_PULL_BITS_PER_PIN;
 585         } else {
 586                 *regmap = info->regmap_base;
 587                 if(ctrl->type == RK3288)
 588                         *reg = RK3288_PULL_OFFSET;
 589                 else if (ctrl->type == RK3368)
 590                         *reg = RK3368_PULL_OFFSET;
 591
 592                 /* correct the offset, as we're starting with the 2nd bank */
 593                 *reg -= 0x10;
 594                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 595                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 596
 597                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 598                 *bit *= RK3188_PULL_BITS_PER_PIN;
 599         }
 600 }
 601
 602 #define RK3288_DRV_PMU_OFFSET           0x70
 603 #define RK3288_DRV_GRF_OFFSET           0x1c0
 604 #define RK3288_DRV_BITS_PER_PIN         2
 605 #define RK3288_DRV_PINS_PER_REG         8
 606 #define RK3288_DRV_BANK_STRIDE          16
 607 static int rk3288_drv_list[] = { 2, 4, 8, 12 };
 608
 609 #define RK3368_DRV_PMU_OFFSET           0x20
 610 #define RK3368_DRV_GRF_OFFSET           0x200
 611
 612
 613 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 614                                     int pin_num, struct regmap **regmap,
 615                                     int *reg, u8 *bit)
 616 {
 617         struct rockchip_pinctrl *info = bank->drvdata;
 618         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 619
 620         /* The first 24 pins of the first bank are located in PMU */
 621         if (bank->bank_num == 0) {
 622                 *regmap = info->regmap_pmu;
 623                 if(ctrl->type == RK3288)
 624                         *reg = RK3288_DRV_PMU_OFFSET;
 625                 else if (ctrl->type == RK3368)
 626                         *reg = RK3368_DRV_PMU_OFFSET;
 627
 628                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 629                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 630                 *bit *= RK3288_DRV_BITS_PER_PIN;
 631         } else {
 632                 *regmap = info->regmap_base;
 633                 if(ctrl->type == RK3288)
 634                         *reg = RK3288_DRV_GRF_OFFSET;
 635                 else if (ctrl->type == RK3368)
 636                         *reg = RK3368_DRV_GRF_OFFSET;
 637
 638
 639                 /* correct the offset, as we're starting with the 2nd bank */
 640                 *reg -= 0x10;
 641                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 642                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 643
 644                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 645                 *bit *= RK3288_DRV_BITS_PER_PIN;
 646         }
 647 }
 648
 649 static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
 650 {
 651         struct regmap *regmap;
 652         int reg, ret;
 653         u32 data;
 654         u8 bit;
 655
 656         rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 657
 658         ret = regmap_read(regmap, reg, &data);
 659         if (ret)
 660                 return ret;
 661
 662         data >>= bit;
 663         data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
 664
 665         return rk3288_drv_list[data];
 666 }
 667
 668 static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
 669                             int strength)
 670 {
 671         struct rockchip_pinctrl *info = bank->drvdata;
 672         struct regmap *regmap;
 673         unsigned long flags;
 674         int reg, ret, i;
 675         u32 data, rmask;
 676         u8 bit;
 677
 678         rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 679
 680         ret = -EINVAL;
 681         for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
 682                 if (rk3288_drv_list[i] == strength) {
 683                         ret = i;
 684                         break;
 685                 }
 686         }
 687
 688         if (ret < 0) {
 689                 dev_err(info->dev, "unsupported driver strength %d\n",
 690                         strength);
 691                 return ret;
 692         }
 693
 694         spin_lock_irqsave(&bank->slock, flags);
 695
 696         /* enable the write to the equivalent lower bits */
 697         data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
 698         rmask = data | (data >> 16);
 699         data |= (ret << bit);
 700
 701         ret = regmap_update_bits(regmap, reg, rmask, data);
 702         spin_unlock_irqrestore(&bank->slock, flags);
 703
 704         return ret;
 705 }
 706
 707 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 708 {
 709         struct rockchip_pinctrl *info = bank->drvdata;
 710         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 711         struct regmap *regmap;
 712         int reg, ret;
 713         u8 bit;
 714         u32 data;
 715
 716         /* rk3066b does support any pulls */
 717         if (ctrl->type == RK3066B)
 718                 return PIN_CONFIG_BIAS_DISABLE;
 719
 720         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 721
 722         ret = regmap_read(regmap, reg, &data);
 723         if (ret)
 724                 return ret;
 725
 726         switch (ctrl->type) {
 727         case RK2928:
 728                 return !(data & BIT(bit))
 729                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 730                                 : PIN_CONFIG_BIAS_DISABLE;
 731         case RK3188:
 732         case RK3288:
 733         case RK3368:
 734                 data >>= bit;
 735                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 736
 737                 switch (data) {
 738                 case 0:
 739                         return PIN_CONFIG_BIAS_DISABLE;
 740                 case 1:
 741                         return PIN_CONFIG_BIAS_PULL_UP;
 742                 case 2:
 743                         return PIN_CONFIG_BIAS_PULL_DOWN;
 744                 case 3:
 745                         return PIN_CONFIG_BIAS_BUS_HOLD;
 746                 }
 747
 748                 dev_err(info->dev, "unknown pull setting\n");
 749                 return -EIO;
 750         default:
 751                 dev_err(info->dev, "unsupported pinctrl type\n");
 752                 return -EINVAL;
 753         };
 754 }
 755
 756 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 757                                         int pin_num, int pull)
 758 {
 759         struct rockchip_pinctrl *info = bank->drvdata;
 760         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 761         struct regmap *regmap;
 762         int reg, ret;
 763         unsigned long flags;
 764         u8 bit;
 765         u32 data, rmask;
 766
 767         pinctrl_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 768                  bank->bank_num, pin_num, pull);
 769
 770         /* rk3066b does support any pulls */
 771         if (ctrl->type == RK3066B)
 772                 return pull ? -EINVAL : 0;
 773
 774         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 775
 776         switch (ctrl->type) {
 777         case RK2928:
 778                 spin_lock_irqsave(&bank->slock, flags);
 779
 780                 data = BIT(bit + 16);
 781                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 782                         data |= BIT(bit);
 783                 ret = regmap_write(regmap, reg, data);
 784
 785                 spin_unlock_irqrestore(&bank->slock, flags);
 786                 break;
 787         case RK3188:
 788         case RK3288:
 789         case RK3368:
 790                 spin_lock_irqsave(&bank->slock, flags);
 791
 792                 /* enable the write to the equivalent lower bits */
 793                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 794                 rmask = data | (data >> 16);
 795
 796                 switch (pull) {
 797                 case PIN_CONFIG_BIAS_DISABLE:
 798                         break;
 799                 case PIN_CONFIG_BIAS_PULL_UP:
 800                         data |= (1 << bit);
 801                         break;
 802                 case PIN_CONFIG_BIAS_PULL_DOWN:
 803                         data |= (2 << bit);
 804                         break;
 805                 case PIN_CONFIG_BIAS_BUS_HOLD:
 806                         data |= (3 << bit);
 807                         break;
 808                 default:
 809                         spin_unlock_irqrestore(&bank->slock, flags);
 810                         dev_err(info->dev, "unsupported pull setting %d\n",
 811                                 pull);
 812                         return -EINVAL;
 813                 }
 814
 815                 ret = regmap_update_bits(regmap, reg, rmask, data);
 816
 817                 spin_unlock_irqrestore(&bank->slock, flags);
 818                 break;
 819         default:
 820                 dev_err(info->dev, "unsupported pinctrl type\n");
 821                 return -EINVAL;
 822         }
 823
 824         return ret;
 825 }
 826
 827 /*
 828  * Pinmux_ops handling
 829  */
 830
 831 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 832 {
 833         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 834
 835         return info->nfunctions;
 836 }
 837
 838 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 839                                           unsigned selector)
 840 {
 841         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 842
 843         return info->functions[selector].name;
 844 }
 845
 846 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 847                                 unsigned selector, const char * const **groups,
 848                                 unsigned * const num_groups)
 849 {
 850         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 851
 852         *groups = info->functions[selector].groups;
 853         *num_groups = info->functions[selector].ngroups;
 854
 855         return 0;
 856 }
 857
 858 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 859                                                             unsigned group)
 860 {
 861         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 862         const unsigned int *pins = info->groups[group].pins;
 863         const struct rockchip_pin_config *data = info->groups[group].data;
 864         struct rockchip_pin_bank *bank;
 865         int cnt, ret = 0;
 866
 867         pinctrl_dbg(info->dev, "enable function %s group %s\n",
 868                 info->functions[selector].name, info->groups[group].name);
 869
 870         /*
 871          * for each pin in the pin group selected, program the correspoding pin
 872          * pin function number in the config register.
 873          */
 874         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 875                 bank = pin_to_bank(info, pins[cnt]);
 876                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 877                                        data[cnt].func);
 878                 if (ret)
 879                         break;
 880         }
 881
 882         if (ret) {
 883                 /* revert the already done pin settings */
 884                 for (cnt--; cnt >= 0; cnt--)
 885                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 886
 887                 return ret;
 888         }
 889
 890         return 0;
 891 }
 892
 893 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 894                                         unsigned selector, unsigned group)
 895 {
 896         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 897         const unsigned int *pins = info->groups[group].pins;
 898         struct rockchip_pin_bank *bank;
 899         int cnt;
 900
 901         pinctrl_dbg(info->dev, "disable function %s group %s\n",
 902                 info->functions[selector].name, info->groups[group].name);
 903
 904         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 905                 bank = pin_to_bank(info, pins[cnt]);
 906                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 907         }
 908 }
 909
 910 /*
 911  * The calls to gpio_direction_output() and gpio_direction_input()
 912  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 913  * function called from the gpiolib interface).
 914  */
 915 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 916                                               struct pinctrl_gpio_range *range,
 917                                               unsigned offset, bool input)
 918 {
 919         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 920         struct rockchip_pin_bank *bank;
 921         struct gpio_chip *chip;
 922         int pin, ret;
 923         u32 data;
 924
 925         chip = range->gc;
 926         bank = gc_to_pin_bank(chip);
 927         pin = offset - chip->base;
 928
 929         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 930                  offset, range->name, pin, input ? "input" : "output");
 931
 932         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 933         if (ret < 0)
 934                 return ret;
 935
 936         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 937         /* set bit to 1 for output, 0 for input */
 938         if (!input)
 939                 data |= BIT(pin);
 940         else
 941                 data &= ~BIT(pin);
 942         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 943
 944         return 0;
 945 }
 946
 947 static const struct pinmux_ops rockchip_pmx_ops = {
 948         .get_functions_count    = rockchip_pmx_get_funcs_count,
 949         .get_function_name      = rockchip_pmx_get_func_name,
 950         .get_function_groups    = rockchip_pmx_get_groups,
 951         .enable                 = rockchip_pmx_enable,
 952         .disable                = rockchip_pmx_disable,
 953         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 954 };
 955
 956 /*
 957  * Pinconf_ops handling
 958  */
 959
 960 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 961                                         enum pin_config_param pull)
 962 {
 963         switch (ctrl->type) {
 964         case RK2928:
 965                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 966                                         pull == PIN_CONFIG_BIAS_DISABLE);
 967         case RK3066B:
 968                 return pull ? false : true;
 969         case RK3188:
 970         case RK3288:
 971         case RK3368:
 972                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 973         }
 974
 975         return false;
 976 }
 977
 978 static int rockchip_gpio_direction_output(
 979         struct gpio_chip *gc, unsigned offset, int value);
 980 static int rockchip_gpio_direction_input(
 981         struct gpio_chip *gc, unsigned offset);
 982 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
 983
 984 /* set the pin config settings for a specified pin */
 985 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 986                                 unsigned long configs)
 987 {
 988         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 989         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 990         enum pin_config_param param;
 991         u16 arg;
 992         //int i;
 993         int rc;
 994
 995         //for (i = 0; i < num_configs; i++) {
 996                 param = pinconf_to_config_param(configs);
 997                 arg = pinconf_to_config_argument(configs);
 998
 999                 switch (param) {
1000                 case PIN_CONFIG_BIAS_DISABLE:
1001                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
1002                                 param);
1003                         if (rc)
1004                                 return rc;
1005                         break;
1006                 case PIN_CONFIG_BIAS_PULL_UP:
1007                 case PIN_CONFIG_BIAS_PULL_DOWN:
1008                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1009                 case PIN_CONFIG_BIAS_BUS_HOLD:
1010                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1011                                 return -ENOTSUPP;
1012
1013                         if (!arg)
1014                                 return -EINVAL;
1015
1016                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
1017                                 param);
1018                         if (rc)
1019                                 return rc;
1020                         break;
1021                 case PIN_CONFIG_OUTPUT:
1022                         rc = rockchip_gpio_direction_output(&bank->gpio_chip,
1023                                                             pin - bank->pin_base,
1024                                                             arg);
1025                         if (rc)
1026                                 return rc;
1027                         break;
1028
1029                 case PIN_CONFIG_INPUT_ENABLE:
1030                         if (arg == 1) {
1031                                 rc = rockchip_gpio_direction_input(
1032                                         &bank->gpio_chip, pin - bank->pin_base);
1033                                 if (rc)
1034                                         return rc;
1035                         }
1036                         break;
1037
1038                 case PIN_CONFIG_DRIVE_STRENGTH:
1039                         /* rk3288 RK3368 is the first with per-pin drive-strength */
1040                         if ((info->ctrl->type != RK3288) && ((info->ctrl->type != RK3368)))
1041                                 return -ENOTSUPP;
1042
1043                         rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
1044                         if (rc < 0)
1045                                 return rc;
1046                         break;
1047                 default:
1048                         return -ENOTSUPP;
1049                         break;
1050                 }
1051         //} /* for each config */
1052
1053         return 0;
1054 }
1055
1056 /* get the pin config settings for a specified pin */
1057 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1058                                                         unsigned long *config)
1059 {
1060         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1061         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1062         enum pin_config_param param = pinconf_to_config_param(*config);
1063         u16 arg;
1064         int rc;
1065
1066         switch (param) {
1067         case PIN_CONFIG_BIAS_DISABLE:
1068                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1069                         return -EINVAL;
1070
1071                 arg = 0;
1072                 break;
1073         case PIN_CONFIG_BIAS_PULL_UP:
1074         case PIN_CONFIG_BIAS_PULL_DOWN:
1075         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1076         case PIN_CONFIG_BIAS_BUS_HOLD:
1077                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1078                         return -ENOTSUPP;
1079
1080                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1081                         return -EINVAL;
1082
1083                 arg = 1;
1084                 break;
1085         case PIN_CONFIG_OUTPUT:
1086                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1087                 if (rc != RK_FUNC_GPIO)
1088                         return -EINVAL;
1089
1090                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1091                 if (rc < 0)
1092                         return rc;
1093
1094                 arg = rc ? 1 : 0;
1095                 break;
1096         case PIN_CONFIG_DRIVE_STRENGTH:
1097                 /* rk3288 RK3368 is the first with per-pin drive-strength */
1098                 if ((info->ctrl->type != RK3288) && ((info->ctrl->type != RK3368)))
1099                         return -ENOTSUPP;
1100
1101                 rc = rk3288_get_drive(bank, pin - bank->pin_base);
1102                 if (rc < 0)
1103                         return rc;
1104
1105                 arg = rc;
1106                 break;
1107         default:
1108                 return -ENOTSUPP;
1109                 break;
1110         }
1111
1112         *config = pinconf_to_config_packed(param, arg);
1113
1114         return 0;
1115 }
1116
1117 static const struct pinconf_ops rockchip_pinconf_ops = {
1118         .pin_config_get                 = rockchip_pinconf_get,
1119         .pin_config_set                 = rockchip_pinconf_set,
1120         .is_generic                     = true,
1121 };
1122
1123 static const struct of_device_id rockchip_bank_match[] = {
1124         { .compatible = "rockchip,gpio-bank" },
1125         { .compatible = "rockchip,rk3188-gpio-bank0" },
1126         {},
1127 };
1128
1129 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1130                                                 struct device_node *np)
1131 {
1132         struct device_node *child;
1133
1134         for_each_child_of_node(np, child) {
1135                 if (of_match_node(rockchip_bank_match, child))
1136                         continue;
1137
1138                 info->nfunctions++;
1139                 info->ngroups += of_get_child_count(child);
1140         }
1141 }
1142
1143 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1144                                               struct rockchip_pin_group *grp,
1145                                               struct rockchip_pinctrl *info,
1146                                               u32 index)
1147 {
1148         struct rockchip_pin_bank *bank;
1149         int size;
1150         const __be32 *list;
1151         int num;
1152         int i, j;
1153         int ret;
1154
1155         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1156
1157         /* Initialise group */
1158         grp->name = np->name;
1159
1160         /*
1161          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1162          * do sanity check and calculate pins number
1163          */
1164         list = of_get_property(np, "rockchip,pins", &size);
1165         /* we do not check return since it's safe node passed down */
1166         size /= sizeof(*list);
1167         if (!size || size % 4) {
1168                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1169                 return -EINVAL;
1170         }
1171
1172         grp->npins = size / 4;
1173
1174         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1175                                                 GFP_KERNEL);
1176         grp->data = devm_kzalloc(info->dev, grp->npins *
1177                                           sizeof(struct rockchip_pin_config),
1178                                         GFP_KERNEL);
1179         if (!grp->pins || !grp->data)
1180                 return -ENOMEM;
1181
1182         for (i = 0, j = 0; i < size; i += 4, j++) {
1183                 const __be32 *phandle;
1184                 struct device_node *np_config;
1185
1186                 num = be32_to_cpu(*list++);
1187                 bank = bank_num_to_bank(info, num);
1188                 if (IS_ERR(bank))
1189                         return PTR_ERR(bank);
1190
1191                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1192                 grp->data[j].func = be32_to_cpu(*list++);
1193
1194                 phandle = list++;
1195                 if (!phandle)
1196                         return -EINVAL;
1197
1198                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1199                 ret = pinconf_generic_parse_dt_config(np_config,
1200                                 &grp->data[j].configs, &grp->data[j].nconfigs);
1201                 if (ret)
1202                         return ret;
1203         }
1204
1205         return 0;
1206 }
1207
1208 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1209                                                 struct rockchip_pinctrl *info,
1210                                                 u32 index)
1211 {
1212         struct device_node *child;
1213         struct rockchip_pmx_func *func;
1214         struct rockchip_pin_group *grp;
1215         int ret;
1216         static u32 grp_index;
1217         u32 i = 0;
1218
1219         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1220
1221         func = &info->functions[index];
1222
1223         /* Initialise function */
1224         func->name = np->name;
1225         func->ngroups = of_get_child_count(np);
1226         if (func->ngroups <= 0)
1227                 return 0;
1228
1229         func->groups = devm_kzalloc(info->dev,
1230                         func->ngroups * sizeof(char *), GFP_KERNEL);
1231         if (!func->groups)
1232                 return -ENOMEM;
1233
1234         for_each_child_of_node(np, child) {
1235                 func->groups[i] = child->name;
1236                 grp = &info->groups[grp_index++];
1237                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1238                 if (ret)
1239                         return ret;
1240         }
1241
1242         return 0;
1243 }
1244
1245 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1246                                               struct rockchip_pinctrl *info)
1247 {
1248         struct device *dev = &pdev->dev;
1249         struct device_node *np = dev->of_node;
1250         struct device_node *child;
1251         int ret;
1252         int i;
1253
1254         rockchip_pinctrl_child_count(info, np);
1255
1256         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1257         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1258
1259         info->functions = devm_kzalloc(dev, info->nfunctions *
1260                                               sizeof(struct rockchip_pmx_func),
1261                                               GFP_KERNEL);
1262         if (!info->functions) {
1263                 dev_err(dev, "failed to allocate memory for function list\n");
1264                 return -EINVAL;
1265         }
1266
1267         info->groups = devm_kzalloc(dev, info->ngroups *
1268                                             sizeof(struct rockchip_pin_group),
1269                                             GFP_KERNEL);
1270         if (!info->groups) {
1271                 dev_err(dev, "failed allocate memory for ping group list\n");
1272                 return -EINVAL;
1273         }
1274
1275         i = 0;
1276
1277         for_each_child_of_node(np, child) {
1278                 if (of_match_node(rockchip_bank_match, child))
1279                         continue;
1280
1281                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1282                 if (ret) {
1283                         dev_err(&pdev->dev, "failed to parse function\n");
1284                         return ret;
1285                 }
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int rockchip_pinctrl_register(struct platform_device *pdev,
1292                                         struct rockchip_pinctrl *info)
1293 {
1294         struct pinctrl_desc *ctrldesc = &info->pctl;
1295         struct pinctrl_pin_desc *pindesc, *pdesc;
1296         struct rockchip_pin_bank *pin_bank;
1297         int pin, bank, ret;
1298         int k;
1299
1300         ctrldesc->name = "rockchip-pinctrl";
1301         ctrldesc->owner = THIS_MODULE;
1302         ctrldesc->pctlops = &rockchip_pctrl_ops;
1303         ctrldesc->pmxops = &rockchip_pmx_ops;
1304         ctrldesc->confops = &rockchip_pinconf_ops;
1305
1306         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1307                         info->ctrl->nr_pins, GFP_KERNEL);
1308         if (!pindesc) {
1309                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1310                 return -ENOMEM;
1311         }
1312         ctrldesc->pins = pindesc;
1313         ctrldesc->npins = info->ctrl->nr_pins;
1314
1315         pdesc = pindesc;
1316         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1317                 pin_bank = &info->ctrl->pin_banks[bank];
1318                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1319                         pdesc->number = k;
1320                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1321                                                 pin_bank->name, pin);
1322                         pdesc++;
1323                 }
1324         }
1325
1326         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1327         if (!info->pctl_dev) {
1328                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1329                 return -EINVAL;
1330         }
1331
1332         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1333                 pin_bank = &info->ctrl->pin_banks[bank];
1334                 pin_bank->grange.name = pin_bank->name;
1335                 pin_bank->grange.id = bank;
1336                 pin_bank->grange.pin_base = pin_bank->pin_base;
1337                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1338                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1339                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1340                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1341         }
1342
1343         ret = rockchip_pinctrl_parse_dt(pdev, info);
1344         if (ret) {
1345                 pinctrl_unregister(info->pctl_dev);
1346                 return ret;
1347         }
1348
1349         return 0;
1350 }
1351
1352 /*
1353  * GPIO handling
1354  */
1355
1356 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1357 {
1358         return pinctrl_request_gpio(chip->base + offset);
1359 }
1360
1361 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1362 {
1363         pinctrl_free_gpio(chip->base + offset);
1364 }
1365
1366 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1367 {
1368         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1369         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1370         unsigned long flags;
1371         u32 data;
1372
1373         spin_lock_irqsave(&bank->slock, flags);
1374
1375         data = readl(reg);
1376         data &= ~BIT(offset);
1377         if (value)
1378                 data |= BIT(offset);
1379         writel(data, reg);
1380
1381         spin_unlock_irqrestore(&bank->slock, flags);
1382 }
1383
1384 /*
1385  * Returns the level of the pin for input direction and setting of the DR
1386  * register for output gpios.
1387  */
1388 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1389 {
1390         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1391         u32 data;
1392
1393         data = readl(bank->reg_base + GPIO_EXT_PORT);
1394         data >>= offset;
1395         data &= 1;
1396         return data;
1397 }
1398
1399 /*
1400  * gpiolib gpio_direction_input callback function. The setting of the pin
1401  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1402  * interface.
1403  */
1404 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1405 {
1406         return pinctrl_gpio_direction_input(gc->base + offset);
1407 }
1408
1409 /*
1410  * gpiolib gpio_direction_output callback function. The setting of the pin
1411  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1412  * interface.
1413  */
1414 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1415                                           unsigned offset, int value)
1416 {
1417         rockchip_gpio_set(gc, offset, value);
1418         return pinctrl_gpio_direction_output(gc->base + offset);
1419 }
1420
1421 /*
1422  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1423  * and a virtual IRQ, if not already present.
1424  */
1425 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1426 {
1427         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1428         unsigned int virq;
1429
1430         if (!bank->domain)
1431                 return -ENXIO;
1432
1433         virq = irq_create_mapping(bank->domain, offset);
1434
1435         return (virq) ? : -ENXIO;
1436 }
1437
1438 static const struct gpio_chip rockchip_gpiolib_chip = {
1439         .request = rockchip_gpio_request,
1440         .free = rockchip_gpio_free,
1441         .set = rockchip_gpio_set,
1442         .get = rockchip_gpio_get,
1443         .direction_input = rockchip_gpio_direction_input,
1444         .direction_output = rockchip_gpio_direction_output,
1445         .to_irq = rockchip_gpio_to_irq,
1446         .owner = THIS_MODULE,
1447 };
1448
1449 /*
1450  * Interrupt handling
1451  */
1452
1453 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1454 {
1455         struct irq_chip *chip = irq_get_chip(irq);
1456         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1457         u32 polarity = 0, data = 0;
1458         u32 pend;
1459         bool edge_changed = false;
1460
1461         pinctrl_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1462
1463         chained_irq_enter(chip, desc);
1464
1465         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1466
1467         if (bank->toggle_edge_mode) {
1468                 polarity = readl_relaxed(bank->reg_base +
1469                                          GPIO_INT_POLARITY);
1470                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1471         }
1472
1473         while (pend) {
1474                 unsigned int virq;
1475
1476                 irq = __ffs(pend);
1477                 pend &= ~BIT(irq);
1478                 virq = irq_linear_revmap(bank->domain, irq);
1479
1480                 if (!virq) {
1481                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1482                         continue;
1483                 }
1484
1485                 pinctrl_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1486
1487                 /*
1488                  * Triggering IRQ on both rising and falling edge
1489                  * needs manual intervention.
1490                  */
1491                 if (bank->toggle_edge_mode & BIT(irq)) {
1492                         if (data & BIT(irq))
1493                                 polarity &= ~BIT(irq);
1494                         else
1495                                 polarity |= BIT(irq);
1496
1497                         edge_changed = true;
1498                 }
1499
1500                 generic_handle_irq(virq);
1501         }
1502
1503         if (bank->toggle_edge_mode && edge_changed) {
1504                 /* Interrupt params should only be set with ints disabled */
1505                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1506                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1507                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1508                 writel(data, bank->reg_base + GPIO_INTEN);
1509         }
1510
1511         chained_irq_exit(chip, desc);
1512 }
1513
1514 static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1515 {
1516         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1517         //struct rockchip_pinctrl *info = bank->drvdata;
1518         u32 mask = BIT(d->hwirq);
1519         u32 polarity;
1520         u32 level;
1521         u32 data;
1522         int ret;
1523         unsigned long flags;
1524
1525         /* make sure the pin is configured as gpio input */
1526         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1527         if (ret < 0)
1528                 return ret;
1529
1530         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1531         data &= ~mask;
1532         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1533
1534         if (type & IRQ_TYPE_EDGE_BOTH)
1535                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1536         else
1537                 __irq_set_handler_locked(d->irq, handle_level_irq);
1538
1539         spin_lock_irqsave(&bank->slock, flags);
1540
1541         level = readl_relaxed(bank->reg_base + GPIO_INTTYPE_LEVEL);
1542         polarity = readl_relaxed(bank->reg_base + GPIO_INT_POLARITY);
1543
1544         switch (type) {
1545         case IRQ_TYPE_EDGE_BOTH:
1546                 bank->toggle_edge_mode |= mask;
1547                 level |= mask;
1548
1549                 /*
1550                  * Determine gpio state. If 1 next interrupt should be falling
1551                  * otherwise rising.
1552                  */
1553                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1554                 if (data & mask)
1555                         polarity &= ~mask;
1556                 else
1557                         polarity |= mask;
1558                 break;
1559         case IRQ_TYPE_EDGE_RISING:
1560                 bank->toggle_edge_mode &= ~mask;
1561                 level |= mask;
1562                 polarity |= mask;
1563                 break;
1564         case IRQ_TYPE_EDGE_FALLING:
1565                 bank->toggle_edge_mode &= ~mask;
1566                 level |= mask;
1567                 polarity &= ~mask;
1568                 break;
1569         case IRQ_TYPE_LEVEL_HIGH:
1570                 bank->toggle_edge_mode &= ~mask;
1571                 level &= ~mask;
1572                 polarity |= mask;
1573                 break;
1574         case IRQ_TYPE_LEVEL_LOW:
1575                 bank->toggle_edge_mode &= ~mask;
1576                 level &= ~mask;
1577                 polarity &= ~mask;
1578                 break;
1579         default:
1580                 //irq_gc_unlock(gc);
1581                 return -EINVAL;
1582         }
1583
1584         writel_relaxed(level, bank->reg_base + GPIO_INTTYPE_LEVEL);
1585         writel_relaxed(polarity, bank->reg_base + GPIO_INT_POLARITY);
1586
1587         spin_unlock_irqrestore(&bank->slock, flags);
1588
1589         //DBG_PINCTRL("%s:type=%d,irq=%d,hwirq=%d,ok\n",__func__,type, d->irq, (int)d->hwirq);
1590         return 0;
1591 }
1592
1593 static inline void rockchip_gpio_bit_op(void __iomem *reg_base
1594         , unsigned int offset, u32 bit, unsigned char flag)
1595 {
1596         u32 val = __raw_readl(reg_base + offset);
1597         if (flag)
1598                 val |= BIT(bit);
1599         else
1600                 val &= ~BIT(bit);
1601
1602
1603         __raw_writel(val, reg_base + offset);
1604 }
1605
1606 static inline unsigned gpio_to_bit(struct rockchip_pin_bank *bank, unsigned gpio)
1607 {
1608         while (gpio >= (bank->pin_base + bank->nr_pins))
1609                 bank++;
1610
1611         return gpio - bank->pin_base;
1612 }
1613
1614 static inline unsigned offset_to_bit(unsigned offset)
1615 {
1616         return 1u << offset;
1617 }
1618
1619 static void GPIOEnableIntr(void __iomem *reg_base, unsigned int bit)
1620 {
1621         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 1);
1622 }
1623
1624 static void GPIODisableIntr(void __iomem *reg_base, unsigned int bit)
1625 {
1626         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 0);
1627 }
1628
1629 static void GPIOAckIntr(void __iomem *reg_base, unsigned int bit)
1630 {
1631         rockchip_gpio_bit_op(reg_base, GPIO_PORTS_EOI, bit, 1);
1632 }
1633
1634 static int rockchip_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1635 {
1636         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1637         //struct rockchip_pinctrl *info = bank->drvdata;
1638         u32 bit = d->hwirq;
1639         unsigned long flags;
1640         //int pin = d->hwirq;
1641
1642         spin_lock_irqsave(&bank->slock, flags);
1643
1644         if (on)
1645         {
1646                 bank->suspend_wakeup |= BIT(bit);
1647         }
1648         else
1649         {
1650                 bank->suspend_wakeup &= ~BIT(bit);
1651         }
1652         spin_unlock_irqrestore(&bank->slock, flags);
1653
1654         //DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n"
1655                 //, __func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
1656         return 0;
1657 }
1658
1659 static void rockchip_gpio_irq_unmask(struct irq_data *d)
1660 {
1661         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1662         //struct rockchip_pinctrl *info = bank->drvdata;
1663         u32 bit = d->hwirq;
1664         unsigned long flags;
1665         //int pin = d->hwirq;
1666
1667         spin_lock_irqsave(&bank->slock, flags);
1668         GPIOEnableIntr(bank->reg_base, bit);
1669         spin_unlock_irqrestore(&bank->slock, flags);
1670
1671         //DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n"
1672                 //, __func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
1673 }
1674
1675 static void rockchip_gpio_irq_mask(struct irq_data *d)
1676 {
1677         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1678         //struct rockchip_pinctrl *info = bank->drvdata;
1679         //u32 bit = gpio_to_bit(bank, d->irq);
1680         u32 bit = d->hwirq;
1681         unsigned long flags;
1682         //int pin = d->hwirq;
1683
1684         spin_lock_irqsave(&bank->slock, flags);
1685         GPIODisableIntr(bank->reg_base, bit);
1686         spin_unlock_irqrestore(&bank->slock, flags);
1687
1688         //DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n"
1689                 //, __func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
1690 }
1691
1692 static void rockchip_gpio_irq_ack(struct irq_data *d)
1693 {
1694         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1695         //struct rockchip_pinctrl *info = bank->drvdata;
1696         //u32 bit = gpio_to_bit(bank, d->irq);
1697         u32 bit = d->hwirq;
1698         //int pin = d->hwirq;
1699
1700         GPIOAckIntr(bank->reg_base, bit);
1701
1702         //DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n"
1703                 //, __func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
1704 }
1705
1706 static struct irq_chip rockchip_gpio_irq_chip = {
1707         .name           = "ROCKCHIP_GPIO_CHIP",
1708         .irq_ack                = rockchip_gpio_irq_ack,
1709         .irq_disable    = rockchip_gpio_irq_mask,
1710         .irq_mask       = rockchip_gpio_irq_mask,
1711         .irq_unmask     = rockchip_gpio_irq_unmask,
1712         .irq_set_type   = rockchip_gpio_irq_set_type,
1713         .irq_set_wake   = rockchip_gpio_irq_set_wake,
1714 };
1715
1716 static int rockchip_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1717                                 irq_hw_number_t hwirq)
1718 {
1719         struct rockchip_pin_bank *bank = d->host_data;
1720         //struct rockchip_pinctrl *info = bank->drvdata;
1721         struct irq_data *irq_data = irq_get_irq_data(irq);
1722         //int pin = hwirq;
1723
1724         if (!bank)
1725         {
1726                 printk("%s:bank=0x%p,irq=%d\n",__func__,bank, irq);
1727                 return -EINVAL;
1728         }
1729
1730         irq_set_chip_and_handler(irq, &rockchip_gpio_irq_chip, handle_level_irq);
1731         irq_set_chip_data(irq, bank);
1732         set_irq_flags(irq, IRQF_VALID);
1733
1734         irq_data->hwirq = hwirq;
1735         irq_data->irq = irq;
1736
1737         pinctrl_dbg(bank->drvdata->dev, "%s:irq = %d, hwirq =%ld\n",__func__,irq, hwirq);
1738         return 0;
1739 }
1740
1741 static const struct irq_domain_ops rockchip_gpio_irq_ops = {
1742         .map = rockchip_gpio_irq_map,
1743         .xlate = irq_domain_xlate_twocell,
1744 };
1745
1746 static int rockchip_interrupts_register(struct platform_device *pdev,
1747                                                 struct rockchip_pinctrl *info)
1748 {
1749         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1750         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1751         //unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1752         int i;
1753
1754         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1755                 if (!bank->valid) {
1756                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1757                                  bank->name);
1758                         continue;
1759                 }
1760
1761                 __raw_writel(0, bank->reg_base + GPIO_INTEN);
1762
1763                 bank->drvdata = info;
1764                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1765                                 &rockchip_gpio_irq_ops, bank);
1766                 if (!bank->domain) {
1767                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1768                                  bank->name);
1769                         continue;
1770                 }
1771
1772                 //if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
1773                         //printk("%s:bank_num=%d\n",__func__,bank->bank_num);
1774
1775                 irq_set_handler_data(bank->irq, bank);
1776                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1777         }
1778
1779         return 0;
1780 }
1781
1782 static int rockchip_gpiolib_register(struct platform_device *pdev,
1783                                                 struct rockchip_pinctrl *info)
1784 {
1785         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1786         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1787         struct gpio_chip *gc;
1788         int ret;
1789         int i;
1790
1791         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1792                 if (!bank->valid) {
1793                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1794                                  bank->name);
1795                         continue;
1796                 }
1797
1798                 bank->gpio_chip = rockchip_gpiolib_chip;
1799
1800                 gc = &bank->gpio_chip;
1801                 gc->base = bank->pin_base;
1802                 gc->ngpio = bank->nr_pins;
1803                 gc->dev = &pdev->dev;
1804                 gc->of_node = bank->of_node;
1805                 gc->label = bank->name;
1806
1807                 ret = gpiochip_add(gc);
1808                 if (ret) {
1809                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1810                                                         gc->label, ret);
1811                         goto fail;
1812                 }
1813         }
1814
1815         rockchip_interrupts_register(pdev, info);
1816
1817         return 0;
1818
1819 fail:
1820         for (--i, --bank; i >= 0; --i, --bank) {
1821                 if (!bank->valid)
1822                         continue;
1823
1824                 if (gpiochip_remove(&bank->gpio_chip))
1825                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1826                                                         bank->gpio_chip.label);
1827         }
1828         return ret;
1829 }
1830
1831 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1832                                                 struct rockchip_pinctrl *info)
1833 {
1834         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1835         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1836         int ret = 0;
1837         int i;
1838
1839         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1840                 if (!bank->valid)
1841                         continue;
1842
1843                 ret = gpiochip_remove(&bank->gpio_chip);
1844         }
1845
1846         if (ret)
1847                 dev_err(&pdev->dev, "gpio chip remove failed\n");
1848
1849         return ret;
1850 }
1851
1852 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1853                                   struct rockchip_pinctrl *info)
1854 {
1855         struct resource res;
1856         void __iomem *base;
1857
1858         if (of_address_to_resource(bank->of_node, 0, &res)) {
1859                 dev_err(info->dev, "cannot find IO resource for bank\n");
1860                 return -ENOENT;
1861         }
1862
1863         bank->reg_base = devm_ioremap_resource(info->dev, &res);
1864         if (IS_ERR(bank->reg_base))
1865                 return PTR_ERR(bank->reg_base);
1866
1867         /*
1868          * special case, where parts of the pull setting-registers are
1869          * part of the PMU register space
1870          */
1871         if (of_device_is_compatible(bank->of_node,
1872                                     "rockchip,rk3188-gpio-bank0")) {
1873                 struct device_node *node;
1874
1875                 node = of_parse_phandle(bank->of_node->parent,
1876                                         "rockchip,pmugrf", 0);
1877                 if (!node) {
1878                         if (of_address_to_resource(bank->of_node, 1, &res)) {
1879                                 dev_err(info->dev, "cannot find IO resource for bank\n");
1880                                 return -ENOENT;
1881                         }
1882
1883                         base = devm_ioremap_resource(info->dev, &res);
1884                         if (IS_ERR(base))
1885                                 return PTR_ERR(base);
1886                         rockchip_regmap_config.max_register =
1887                                                     resource_size(&res) - 4;
1888                         rockchip_regmap_config.name =
1889                                             "rockchip,rk3188-gpio-bank0-pull";
1890                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1891                                                     base,
1892                                                     &rockchip_regmap_config);
1893                 }
1894         }
1895
1896         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1897
1898         bank->clk = of_clk_get(bank->of_node, 0);
1899         if (IS_ERR(bank->clk))
1900                 return PTR_ERR(bank->clk);
1901
1902         return clk_prepare_enable(bank->clk);
1903 }
1904
1905 static const struct of_device_id rockchip_pinctrl_dt_match[];
1906
1907 /* retrieve the soc specific data */
1908 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1909                                                 struct rockchip_pinctrl *d,
1910                                                 struct platform_device *pdev)
1911 {
1912         const struct of_device_id *match;
1913         struct device_node *node = pdev->dev.of_node;
1914         struct device_node *np;
1915         struct rockchip_pin_ctrl *ctrl;
1916         struct rockchip_pin_bank *bank;
1917         int grf_offs, pmu_offs, i, j;
1918
1919         match = of_match_node(rockchip_pinctrl_dt_match, node);
1920         ctrl = (struct rockchip_pin_ctrl *)match->data;
1921
1922         for_each_child_of_node(node, np) {
1923                 if (!of_find_property(np, "gpio-controller", NULL))
1924                         continue;
1925
1926                 bank = ctrl->pin_banks;
1927                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1928                         if (!strcmp(bank->name, np->name)) {
1929                                 bank->of_node = np;
1930
1931                                 if (!rockchip_get_bank_data(bank, d))
1932                                         bank->valid = true;
1933
1934                                 break;
1935                         }
1936                 }
1937         }
1938
1939         grf_offs = ctrl->grf_mux_offset;
1940         pmu_offs = ctrl->pmu_mux_offset;
1941         bank = ctrl->pin_banks;
1942         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1943                 int bank_pins = 0;
1944
1945                 spin_lock_init(&bank->slock);
1946                 bank->drvdata = d;
1947                 bank->pin_base = ctrl->nr_pins;
1948                 ctrl->nr_pins += bank->nr_pins;
1949
1950                 /* calculate iomux offsets */
1951                 for (j = 0; j < 4; j++) {
1952                         struct rockchip_iomux *iom = &bank->iomux[j];
1953                         int inc;
1954
1955                         if (bank_pins >= bank->nr_pins)
1956                                 break;
1957
1958                         /* preset offset value, set new start value */
1959                         if (iom->offset >= 0) {
1960                                 if (iom->type & IOMUX_SOURCE_PMU)
1961                                         pmu_offs = iom->offset;
1962                                 else
1963                                         grf_offs = iom->offset;
1964                         } else { /* set current offset */
1965                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1966                                                         pmu_offs : grf_offs;
1967                         }
1968
1969                         pinctrl_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1970                                  i, j, iom->offset);
1971
1972                         /*
1973                          * Increase offset according to iomux width.
1974                          * 4bit iomux'es are spread over two registers.
1975                          */
1976                         inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1977                         if (iom->type & IOMUX_SOURCE_PMU)
1978                                 pmu_offs += inc;
1979                         else
1980                                 grf_offs += inc;
1981
1982                         bank_pins += 8;
1983                 }
1984         }
1985
1986         return ctrl;
1987 }
1988
1989 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1990 {
1991         struct rockchip_pinctrl *info;
1992         struct device *dev = &pdev->dev;
1993         struct rockchip_pin_ctrl *ctrl;
1994         struct device_node *np = pdev->dev.of_node, *node;
1995         struct resource *res;
1996         void __iomem *base;
1997         int ret;
1998
1999         if (!dev->of_node) {
2000                 dev_err(dev, "device tree node not found\n");
2001                 return -ENODEV;
2002         }
2003
2004         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2005         if (!info)
2006                 return -ENOMEM;
2007
2008         info->dev = dev;
2009
2010         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2011         if (!ctrl) {
2012                 dev_err(dev, "driver data not available\n");
2013                 return -EINVAL;
2014         }
2015         info->ctrl = ctrl;
2016         g_info = info;
2017
2018         node = of_parse_phandle(np, "rockchip,grf", 0);
2019         if (node) {
2020                 info->regmap_base = syscon_node_to_regmap(node);
2021                 if (IS_ERR(info->regmap_base))
2022                         return PTR_ERR(info->regmap_base);
2023         } else {
2024                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2025                 base = devm_ioremap_resource(&pdev->dev, res);
2026                 if (IS_ERR(base))
2027                         return PTR_ERR(base);
2028
2029                 rockchip_regmap_config.max_register = resource_size(res) - 4;
2030                 rockchip_regmap_config.name = "rockchip,pinctrl";
2031                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2032                                                     &rockchip_regmap_config);
2033
2034                 /* to check for the old dt-bindings */
2035                 info->reg_size = resource_size(res);
2036
2037                 /* Honor the old binding, with pull registers as 2nd resource */
2038                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2039                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2040                         base = devm_ioremap_resource(&pdev->dev, res);
2041                         if (IS_ERR(base))
2042                                 return PTR_ERR(base);
2043
2044                         rockchip_regmap_config.max_register =
2045                                                         resource_size(res) - 4;
2046                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2047                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2048                                                     base,
2049                                                     &rockchip_regmap_config);
2050                 }
2051         }
2052
2053         /* try to find the optional reference to the pmu syscon */
2054         node = of_parse_phandle(np, "rockchip,pmugrf", 0);
2055         if (node) {
2056                 info->regmap_pmu = syscon_node_to_regmap(node);
2057                 if (IS_ERR(info->regmap_pmu))
2058                         return PTR_ERR(info->regmap_pmu);
2059         }
2060
2061         ret = rockchip_gpiolib_register(pdev, info);
2062         if (ret)
2063                 return ret;
2064
2065         ret = rockchip_pinctrl_register(pdev, info);
2066         if (ret) {
2067                 rockchip_gpiolib_unregister(pdev, info);
2068                 return ret;
2069         }
2070
2071         platform_set_drvdata(pdev, info);
2072         printk("%s:init ok\n",__func__);
2073
2074         return 0;
2075 }
2076
2077 #ifdef CONFIG_PM
2078 static int rockchip_pinctrl_suspend(void)
2079 {
2080         struct rockchip_pinctrl *info = g_info;
2081         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2082         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2083         int n;
2084         //int value = 0;
2085
2086         for(n=0; n<ctrl->nr_banks; n++)
2087         {
2088 #if 0
2089                 int i;
2090                 for(i=0; i<0x60; i=i+4)
2091                 {
2092                         value = readl_relaxed(bank->reg_base + i);
2093                         printk("%s:bank_num=%d,reg[0x%x+0x%x]=0x%x,bank_name=%s\n",__func__,bank->bank_num, bank->reg_base, i, value, bank->name);
2094                 }
2095 #endif
2096                 bank->saved_wakeup = __raw_readl(bank->reg_base + GPIO_INTEN);
2097                 __raw_writel(bank->suspend_wakeup, bank->reg_base + GPIO_INTEN);
2098
2099                 if (!bank->suspend_wakeup)
2100                 clk_disable_unprepare(bank->clk);
2101
2102                 //if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
2103                         //printk("%s:bank_num=%d, suspend_wakeup=0x%x\n"
2104                                 //,__func__, bank->bank_num, bank->suspend_wakeup);
2105                 bank++;
2106         }
2107
2108
2109         return 0;
2110 }
2111
2112 static void rockchip_pinctrl_resume(void)
2113 {
2114         struct rockchip_pinctrl *info = g_info;
2115         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2116         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2117         int n;
2118         u32 isr;
2119
2120         for(n=0; n<ctrl->nr_banks; n++)
2121         {
2122 #if 0
2123                 int i;
2124                 for(i=0; i<0x60; i=i+4)
2125                 {
2126                         u32 value = readl_relaxed(bank->reg_base + i);
2127                         printk("%s:bank_num=%d,reg[0x%x+0x%x]=0x%x,bank_name=%s\n",__func__,bank->bank_num, bank->reg_base, i, value, bank->name);
2128                 }
2129 #endif
2130                 if (!bank->suspend_wakeup)
2131                 clk_prepare_enable(bank->clk);
2132
2133                 /* keep enable for resume irq */
2134                  isr = __raw_readl(bank->reg_base + GPIO_INT_STATUS);
2135                         __raw_writel(bank->saved_wakeup | (bank->suspend_wakeup & isr)
2136                                         , bank->reg_base + GPIO_INTEN);
2137
2138                 //if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
2139                         //printk("%s:bank_num=%d, suspend_wakeup=0x%x\n",__func__
2140                                  //bank->bank_num, bank->saved_wakeup | (bank->suspend_wakeup & isr));
2141
2142                 bank++;
2143         }
2144
2145 }
2146 #endif
2147
2148 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2149         PIN_BANK(0, 32, "gpio0"),
2150         PIN_BANK(1, 32, "gpio1"),
2151         PIN_BANK(2, 32, "gpio2"),
2152         PIN_BANK(3, 32, "gpio3"),
2153 };
2154
2155 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2156                 .pin_banks              = rk2928_pin_banks,
2157                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2158                 .label                  = "RK2928-GPIO",
2159                 .type                   = RK2928,
2160                 .grf_mux_offset         = 0xa8,
2161                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2162 };
2163
2164 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2165         PIN_BANK(0, 32, "gpio0"),
2166         PIN_BANK(1, 32, "gpio1"),
2167         PIN_BANK(2, 32, "gpio2"),
2168         PIN_BANK(3, 32, "gpio3"),
2169         PIN_BANK(4, 32, "gpio4"),
2170         PIN_BANK(6, 16, "gpio6"),
2171 };
2172
2173 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2174                 .pin_banks              = rk3066a_pin_banks,
2175                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2176                 .label                  = "RK3066a-GPIO",
2177                 .type                   = RK2928,
2178                 .grf_mux_offset         = 0xa8,
2179                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2180 };
2181
2182 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2183         PIN_BANK(0, 32, "gpio0"),
2184         PIN_BANK(1, 32, "gpio1"),
2185         PIN_BANK(2, 32, "gpio2"),
2186         PIN_BANK(3, 32, "gpio3"),
2187 };
2188
2189 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2190                 .pin_banks      = rk3066b_pin_banks,
2191                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2192                 .label          = "RK3066b-GPIO",
2193                 .type           = RK3066B,
2194                 .grf_mux_offset = 0x60,
2195 };
2196
2197 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2198         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2199         PIN_BANK(1, 32, "gpio1"),
2200         PIN_BANK(2, 32, "gpio2"),
2201         PIN_BANK(3, 32, "gpio3"),
2202 };
2203
2204 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2205                 .pin_banks              = rk3188_pin_banks,
2206                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2207                 .label                  = "RK3188-GPIO",
2208                 .type                   = RK3188,
2209                 .grf_mux_offset         = 0x60,
2210                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2211 };
2212
2213 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2214         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2215                                              IOMUX_SOURCE_PMU,
2216                                              IOMUX_SOURCE_PMU,
2217                                              IOMUX_UNROUTED
2218                             ),
2219         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2220                                              IOMUX_UNROUTED,
2221                                              IOMUX_UNROUTED,
2222                                              0
2223                             ),
2224         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2225         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2226         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2227                                              IOMUX_WIDTH_4BIT,
2228                                              0,
2229                                              0
2230                             ),
2231         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2232                                              0,
2233                                              0,
2234                                              IOMUX_UNROUTED
2235                             ),
2236         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2237         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2238                                              0,
2239                                              IOMUX_WIDTH_4BIT,
2240                                              IOMUX_UNROUTED
2241                             ),
2242         PIN_BANK(8, 16, "gpio8"),
2243 };
2244
2245 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2246                 .pin_banks              = rk3288_pin_banks,
2247                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
2248                 .label                  = "RK3288-GPIO",
2249                 .type                   = RK3288,
2250                 .grf_mux_offset         = 0x0,
2251                 .pmu_mux_offset         = 0x84,
2252                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
2253 };
2254
2255 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2256         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2257                                              IOMUX_SOURCE_PMU,
2258                                              IOMUX_SOURCE_PMU,
2259                                              IOMUX_SOURCE_PMU),
2260         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2261         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2262         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2263 };
2264
2265 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2266                 .pin_banks              = rk3368_pin_banks,
2267                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
2268                 .label                  = "RK3368-GPIO",
2269                 .type                   = RK3368,
2270                 .grf_mux_offset         = 0x0,
2271                 .pmu_mux_offset         = 0x0,
2272                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
2273 };
2274
2275 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2276         { .compatible = "rockchip,rk2928-pinctrl",
2277                 .data = (void *)&rk2928_pin_ctrl },
2278         { .compatible = "rockchip,rk3066a-pinctrl",
2279                 .data = (void *)&rk3066a_pin_ctrl },
2280         { .compatible = "rockchip,rk3066b-pinctrl",
2281                 .data = (void *)&rk3066b_pin_ctrl },
2282         { .compatible = "rockchip,rk3188-pinctrl",
2283                 .data = (void *)&rk3188_pin_ctrl },
2284         { .compatible = "rockchip,rk3288-pinctrl",
2285                 .data = (void *)&rk3288_pin_ctrl },
2286         { .compatible = "rockchip,rk3368-pinctrl",
2287                 .data = (void *)&rk3368_pin_ctrl },
2288         {},
2289 };
2290 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2291
2292 static struct platform_driver rockchip_pinctrl_driver = {
2293         .probe          = rockchip_pinctrl_probe,
2294         .driver = {
2295                 .name   = "rockchip-pinctrl",
2296                 .owner  = THIS_MODULE,
2297                 .of_match_table = rockchip_pinctrl_dt_match,
2298         },
2299 };
2300
2301 #ifdef CONFIG_PM
2302 static struct syscore_ops rockchip_gpio_syscore_ops = {
2303         .suspend        = rockchip_pinctrl_suspend,
2304         .resume         = rockchip_pinctrl_resume,
2305 };
2306 #endif
2307
2308 static int __init rockchip_pinctrl_drv_register(void)
2309 {
2310 #ifdef CONFIG_PM
2311                 register_syscore_ops(&rockchip_gpio_syscore_ops);
2312 #endif
2313         return platform_driver_register(&rockchip_pinctrl_driver);
2314 }
2315 postcore_initcall(rockchip_pinctrl_drv_register);
2316
2317 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2318 MODULE_DESCRIPTION("Rockchip pinctrl driver");
2319 MODULE_LICENSE("GPL v2");