drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         RK2928,
  63         RK3066B,
  64         RK3188,
  65         RK3288,
  66         RK3366,
  67         RK3368,
  68         RK3399,
  69 };
  70
  71 /**
  72  * Encode variants of iomux registers into a type variable
  73  */
  74 #define IOMUX_GPIO_ONLY         BIT(0)
  75 #define IOMUX_WIDTH_4BIT        BIT(1)
  76 #define IOMUX_SOURCE_PMU        BIT(2)
  77 #define IOMUX_UNROUTED          BIT(3)
  78 #define IOMUX_WIDTH_3BIT        BIT(4)
  79 #define IOMUX_RECALCED          BIT(5)
  80
  81 /**
  82  * @type: iomux variant using IOMUX_* constants
  83  * @offset: if initialized to -1 it will be autocalculated, by specifying
  84  *          an initial offset value the relevant source offset can be reset
  85  *          to a new value for autocalculating the following iomux registers.
  86  */
  87 struct rockchip_iomux {
  88         int                             type;
  89         int                             offset;
  90 };
  91
  92 /**
  93  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  94  */
  95 enum rockchip_pin_drv_type {
  96         DRV_TYPE_IO_DEFAULT = 0,
  97         DRV_TYPE_IO_1V8_OR_3V0,
  98         DRV_TYPE_IO_1V8_ONLY,
  99         DRV_TYPE_IO_1V8_3V0_AUTO,
 100         DRV_TYPE_IO_3V3_ONLY,
 101         DRV_TYPE_IO_WIDE_LEVEL,
 102         DRV_TYPE_IO_NARROW_LEVEL,
 103         DRV_TYPE_MAX
 104 };
 105
 106 /**
 107  * enum type index corresponding to rockchip_pull_list arrays index.
 108  */
 109 enum rockchip_pin_pull_type {
 110         PULL_TYPE_IO_DEFAULT = 0,
 111         PULL_TYPE_IO_1V8_ONLY,
 112         PULL_TYPE_MAX
 113 };
 114
 115 /**
 116  * enum type of pin extra drive alignment.
 117  */
 118 enum rockchip_pin_extra_drv_type {
 119         DRV_TYPE_EXTRA_DEFAULT = 0,
 120         DRV_TYPE_EXTRA_SAME_OFFSET,
 121         DRV_TYPE_EXTRA_SAME_BITS
 122 };
 123
 124 /**
 125  * @drv_type: drive strength variant using rockchip_pin_drv_type
 126  * @offset: if initialized to -1 it will be autocalculated, by specifying
 127  *          an initial offset value the relevant source offset can be reset
 128  *          to a new value for autocalculating the following drive strength
 129  *          registers. if used chips own cal_drv func instead to calculate
 130  *          registers offset, the variant could be ignored.
 131  */
 132 struct rockchip_drv {
 133         enum rockchip_pin_drv_type      drv_type;
 134         int                             offset;
 135 };
 136
 137 /**
 138  * @reg_base: register base of the gpio bank
 139  * @reg_pull: optional separate register for additional pull settings
 140  * @clk: clock of the gpio bank
 141  * @irq: interrupt of the gpio bank
 142  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 143  * @pin_base: first pin number
 144  * @nr_pins: number of pins in this bank
 145  * @name: name of the bank
 146  * @bank_num: number of the bank, to account for holes
 147  * @iomux: array describing the 4 iomux sources of the bank
 148  * @drv: array describing the 4 drive strength sources of the bank
 149  * @pull_type: array describing the 4 pull type sources of the bank
 150  * @valid: are all necessary informations present
 151  * @of_node: dt node of this bank
 152  * @drvdata: common pinctrl basedata
 153  * @domain: irqdomain of the gpio bank
 154  * @gpio_chip: gpiolib chip
 155  * @grange: gpio range
 156  * @slock: spinlock for the gpio bank
 157  * @irq_lock: bus lock for irq chip
 158  * @new_irqs: newly configured irqs which must be muxed as GPIOs in
 159  *      irq_bus_sync_unlock()
 160  * @route_mask: bits describing the routing pins of per bank
 161  */
 162 struct rockchip_pin_bank {
 163         void __iomem                    *reg_base;
 164         struct regmap                   *regmap_pull;
 165         struct clk                      *clk;
 166         int                             irq;
 167         u32                             saved_masks;
 168         u32                             pin_base;
 169         u8                              nr_pins;
 170         char                            *name;
 171         u8                              bank_num;
 172         struct rockchip_iomux           iomux[4];
 173         struct rockchip_drv             drv[4];
 174         enum rockchip_pin_pull_type     pull_type[4];
 175         bool                            valid;
 176         struct device_node              *of_node;
 177         struct rockchip_pinctrl         *drvdata;
 178         struct irq_domain               *domain;
 179         struct gpio_chip                gpio_chip;
 180         struct pinctrl_gpio_range       grange;
 181         raw_spinlock_t                  slock;
 182         u32                             toggle_edge_mode;
 183         struct mutex                    irq_lock;
 184         u32                             new_irqs;
 185         u32                             route_mask;
 186 };
 187
 188 #define PIN_BANK(id, pins, label)                       \
 189         {                                               \
 190                 .bank_num       = id,                   \
 191                 .nr_pins        = pins,                 \
 192                 .name           = label,                \
 193                 .iomux          = {                     \
 194                         { .offset = -1 },               \
 195                         { .offset = -1 },               \
 196                         { .offset = -1 },               \
 197                         { .offset = -1 },               \
 198                 },                                      \
 199         }
 200
 201 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 202         {                                                               \
 203                 .bank_num       = id,                                   \
 204                 .nr_pins        = pins,                                 \
 205                 .name           = label,                                \
 206                 .iomux          = {                                     \
 207                         { .type = iom0, .offset = -1 },                 \
 208                         { .type = iom1, .offset = -1 },                 \
 209                         { .type = iom2, .offset = -1 },                 \
 210                         { .type = iom3, .offset = -1 },                 \
 211                 },                                                      \
 212         }
 213
 214 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 215         {                                                               \
 216                 .bank_num       = id,                                   \
 217                 .nr_pins        = pins,                                 \
 218                 .name           = label,                                \
 219                 .iomux          = {                                     \
 220                         { .offset = -1 },                               \
 221                         { .offset = -1 },                               \
 222                         { .offset = -1 },                               \
 223                         { .offset = -1 },                               \
 224                 },                                                      \
 225                 .drv            = {                                     \
 226                         { .drv_type = type0, .offset = -1 },            \
 227                         { .drv_type = type1, .offset = -1 },            \
 228                         { .drv_type = type2, .offset = -1 },            \
 229                         { .drv_type = type3, .offset = -1 },            \
 230                 },                                                      \
 231         }
 232
 233 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, drv2,\
 234                                       drv3, pull0, pull1, pull2, pull3) \
 235         {                                                               \
 236                 .bank_num       = id,                                   \
 237                 .nr_pins        = pins,                                 \
 238                 .name           = label,                                \
 239                 .iomux          = {                                     \
 240                         { .offset = -1 },                               \
 241                         { .offset = -1 },                               \
 242                         { .offset = -1 },                               \
 243                         { .offset = -1 },                               \
 244                 },                                                      \
 245                 .drv            = {                                     \
 246                         { .drv_type = drv0, .offset = -1 },             \
 247                         { .drv_type = drv1, .offset = -1 },             \
 248                         { .drv_type = drv2, .offset = -1 },             \
 249                         { .drv_type = drv3, .offset = -1 },             \
 250                 },                                                      \
 251                 .pull_type[0] = pull0,                                  \
 252                 .pull_type[1] = pull1,                                  \
 253                 .pull_type[2] = pull2,                                  \
 254                 .pull_type[3] = pull3,                                  \
 255         }
 256
 257 #define PIN_BANK_IOMUX_DRV_FLAGS(id, pins, label, iom0, iom1, iom2,     \
 258                                 iom3, drv0, drv1, drv2, drv3)           \
 259         {                                                               \
 260                 .bank_num       = id,                                   \
 261                 .nr_pins        = pins,                                 \
 262                 .name           = label,                                \
 263                 .iomux          = {                                     \
 264                         { .type = iom0, .offset = -1 },                 \
 265                         { .type = iom1, .offset = -1 },                 \
 266                         { .type = iom2, .offset = -1 },                 \
 267                         { .type = iom3, .offset = -1 },                 \
 268                 },                                                      \
 269                 .drv            = {                                     \
 270                         { .drv_type = drv0, .offset = -1 },             \
 271                         { .drv_type = drv1, .offset = -1 },             \
 272                         { .drv_type = drv2, .offset = -1 },             \
 273                         { .drv_type = drv3, .offset = -1 },             \
 274                 },                                                      \
 275         }
 276
 277 #define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0,    \
 278                                              iom1, iom2, iom3, offset0, \
 279                                              offset1, offset2, offset3, \
 280                                              drv0, drv1, drv2, drv3)    \
 281         {                                                               \
 282                 .bank_num       = id,                                   \
 283                 .nr_pins        = pins,                                 \
 284                 .name           = label,                                \
 285                 .iomux          = {                                     \
 286                         { .type = iom0, .offset = offset0 },            \
 287                         { .type = iom1, .offset = offset1 },            \
 288                         { .type = iom2, .offset = offset2 },            \
 289                         { .type = iom3, .offset = offset3 },            \
 290                 },                                                      \
 291                 .drv            = {                                     \
 292                         { .drv_type = drv0, .offset = -1 },             \
 293                         { .drv_type = drv1, .offset = -1 },             \
 294                         { .drv_type = drv2, .offset = -1 },             \
 295                         { .drv_type = drv3, .offset = -1 },             \
 296                 },                                                      \
 297         }
 298
 299 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET(id, pins, label, iom0,    \
 300                                               iom1, iom2, iom3, drv0,   \
 301                                               drv1, drv2, drv3, offset0,\
 302                                               offset1, offset2, offset3)\
 303         {                                                               \
 304                 .bank_num       = id,                                   \
 305                 .nr_pins        = pins,                                 \
 306                 .name           = label,                                \
 307                 .iomux          = {                                     \
 308                         { .type = iom0, .offset = -1 },                 \
 309                         { .type = iom1, .offset = -1 },                 \
 310                         { .type = iom2, .offset = -1 },                 \
 311                         { .type = iom3, .offset = -1 },                 \
 312                 },                                                      \
 313                 .drv            = {                                     \
 314                         { .drv_type = drv0, .offset = offset0 },        \
 315                         { .drv_type = drv1, .offset = offset1 },        \
 316                         { .drv_type = drv2, .offset = offset2 },        \
 317                         { .drv_type = drv3, .offset = offset3 },        \
 318                 },                                                      \
 319         }
 320
 321 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 322                                               label, iom0, iom1, iom2,  \
 323                                               iom3, drv0, drv1, drv2,   \
 324                                               drv3, offset0, offset1,   \
 325                                               offset2, offset3, pull0,  \
 326                                               pull1, pull2, pull3)      \
 327         {                                                               \
 328                 .bank_num       = id,                                   \
 329                 .nr_pins        = pins,                                 \
 330                 .name           = label,                                \
 331                 .iomux          = {                                     \
 332                         { .type = iom0, .offset = -1 },                 \
 333                         { .type = iom1, .offset = -1 },                 \
 334                         { .type = iom2, .offset = -1 },                 \
 335                         { .type = iom3, .offset = -1 },                 \
 336                 },                                                      \
 337                 .drv            = {                                     \
 338                         { .drv_type = drv0, .offset = offset0 },        \
 339                         { .drv_type = drv1, .offset = offset1 },        \
 340                         { .drv_type = drv2, .offset = offset2 },        \
 341                         { .drv_type = drv3, .offset = offset3 },        \
 342                 },                                                      \
 343                 .pull_type[0] = pull0,                                  \
 344                 .pull_type[1] = pull1,                                  \
 345                 .pull_type[2] = pull2,                                  \
 346                 .pull_type[3] = pull3,                                  \
 347         }
 348
 349 /**
 350  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 351  * @bank_num: bank number.
 352  * @pin: index at register or used to calc index.
 353  * @func: the min pin.
 354  * @route_offset: the max pin.
 355  * @route_val: the register offset.
 356  */
 357 struct rockchip_mux_route_data {
 358         u8 bank_num;
 359         u8 pin;
 360         u8 func;
 361         u32 route_offset;
 362         u32 route_val;
 363 };
 364
 365 /**
 366  */
 367 struct rockchip_pin_ctrl {
 368         struct rockchip_pin_bank        *pin_banks;
 369         u32                             nr_banks;
 370         u32                             nr_pins;
 371         char                            *label;
 372         enum rockchip_pinctrl_type      type;
 373         int                             grf_mux_offset;
 374         int                             pmu_mux_offset;
 375         int                             grf_drv_offset;
 376         int                             pmu_drv_offset;
 377         struct rockchip_mux_route_data *iomux_routes;
 378         u32                             niomux_routes;
 379
 380         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 381                                  int pin_num, struct regmap **regmap,
 382                                  int *reg, u8 *bit);
 383         enum rockchip_pin_drv_type (*drv_calc_reg)(
 384                                 struct rockchip_pin_bank *bank,
 385                                 int pin_num, struct regmap **regmap,
 386                                 int *reg, u8 *bit);
 387         enum rockchip_pin_extra_drv_type (*drv_calc_extra_reg)(
 388                                       struct rockchip_pin_bank *bank,
 389                                       int pin_num, struct regmap **regmap,
 390                                       int *reg, u8 *bit);
 391         void    (*iomux_recalc)(u8 bank_num, int pin, int *reg,
 392                                 u8 *bit, int *mask);
 393         int     (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
 394                                     int pin_num, struct regmap **regmap,
 395                                     int *reg, u8 *bit);
 396 };
 397
 398 struct rockchip_pin_config {
 399         unsigned int            func;
 400         unsigned long           *configs;
 401         unsigned int            nconfigs;
 402 };
 403
 404 /**
 405  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 406  * @name: name of the pin group, used to lookup the group.
 407  * @pins: the pins included in this group.
 408  * @npins: number of pins included in this group.
 409  * @func: the mux function number to be programmed when selected.
 410  * @configs: the config values to be set for each pin
 411  * @nconfigs: number of configs for each pin
 412  */
 413 struct rockchip_pin_group {
 414         const char                      *name;
 415         unsigned int                    npins;
 416         unsigned int                    *pins;
 417         struct rockchip_pin_config      *data;
 418 };
 419
 420 /**
 421  * struct rockchip_pmx_func: represent a pin function.
 422  * @name: name of the pin function, used to lookup the function.
 423  * @groups: one or more names of pin groups that provide this function.
 424  * @num_groups: number of groups included in @groups.
 425  */
 426 struct rockchip_pmx_func {
 427         const char              *name;
 428         const char              **groups;
 429         u8                      ngroups;
 430 };
 431
 432 struct rockchip_pinctrl {
 433         struct regmap                   *regmap_base;
 434         int                             reg_size;
 435         struct regmap                   *regmap_pull;
 436         struct regmap                   *regmap_pmu;
 437         struct device                   *dev;
 438         struct rockchip_pin_ctrl        *ctrl;
 439         struct pinctrl_desc             pctl;
 440         struct pinctrl_dev              *pctl_dev;
 441         struct rockchip_pin_group       *groups;
 442         unsigned int                    ngroups;
 443         struct rockchip_pmx_func        *functions;
 444         unsigned int                    nfunctions;
 445 };
 446
 447 /**
 448  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 449  * @num: bank number.
 450  * @pin: pin number.
 451  * @bit: index at register.
 452  * @reg: register offset.
 453  * @mask: mask bit
 454  */
 455 struct rockchip_mux_recalced_data {
 456         u8 num;
 457         u8 pin;
 458         u8 reg;
 459         u8 bit;
 460         u8 mask;
 461 };
 462
 463 static struct regmap_config rockchip_regmap_config = {
 464         .reg_bits = 32,
 465         .val_bits = 32,
 466         .reg_stride = 4,
 467 };
 468
 469 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 470 {
 471         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 472 }
 473
 474 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 475                                         const struct rockchip_pinctrl *info,
 476                                         const char *name)
 477 {
 478         int i;
 479
 480         for (i = 0; i < info->ngroups; i++) {
 481                 if (!strcmp(info->groups[i].name, name))
 482                         return &info->groups[i];
 483         }
 484
 485         return NULL;
 486 }
 487
 488 /*
 489  * given a pin number that is local to a pin controller, find out the pin bank
 490  * and the register base of the pin bank.
 491  */
 492 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 493                                                                 unsigned pin)
 494 {
 495         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 496
 497         while (pin >= (b->pin_base + b->nr_pins))
 498                 b++;
 499
 500         return b;
 501 }
 502
 503 static struct rockchip_pin_bank *bank_num_to_bank(
 504                                         struct rockchip_pinctrl *info,
 505                                         unsigned num)
 506 {
 507         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 508         int i;
 509
 510         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 511                 if (b->bank_num == num)
 512                         return b;
 513         }
 514
 515         return ERR_PTR(-EINVAL);
 516 }
 517
 518 /*
 519  * Pinctrl_ops handling
 520  */
 521
 522 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 523 {
 524         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 525
 526         return info->ngroups;
 527 }
 528
 529 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 530                                                         unsigned selector)
 531 {
 532         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 533
 534         return info->groups[selector].name;
 535 }
 536
 537 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 538                                       unsigned selector, const unsigned **pins,
 539                                       unsigned *npins)
 540 {
 541         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 542
 543         if (selector >= info->ngroups)
 544                 return -EINVAL;
 545
 546         *pins = info->groups[selector].pins;
 547         *npins = info->groups[selector].npins;
 548
 549         return 0;
 550 }
 551
 552 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 553                                  struct device_node *np,
 554                                  struct pinctrl_map **map, unsigned *num_maps)
 555 {
 556         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 557         const struct rockchip_pin_group *grp;
 558         struct pinctrl_map *new_map;
 559         struct device_node *parent;
 560         int map_num = 1;
 561         int i;
 562
 563         /*
 564          * first find the group of this node and check if we need to create
 565          * config maps for pins
 566          */
 567         grp = pinctrl_name_to_group(info, np->name);
 568         if (!grp) {
 569                 dev_err(info->dev, "unable to find group for node %s\n",
 570                         np->name);
 571                 return -EINVAL;
 572         }
 573
 574         map_num += grp->npins;
 575         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 576                                                                 GFP_KERNEL);
 577         if (!new_map)
 578                 return -ENOMEM;
 579
 580         *map = new_map;
 581         *num_maps = map_num;
 582
 583         /* create mux map */
 584         parent = of_get_parent(np);
 585         if (!parent) {
 586                 devm_kfree(pctldev->dev, new_map);
 587                 return -EINVAL;
 588         }
 589         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 590         new_map[0].data.mux.function = parent->name;
 591         new_map[0].data.mux.group = np->name;
 592         of_node_put(parent);
 593
 594         /* create config map */
 595         new_map++;
 596         for (i = 0; i < grp->npins; i++) {
 597                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 598                 new_map[i].data.configs.group_or_pin =
 599                                 pin_get_name(pctldev, grp->pins[i]);
 600                 new_map[i].data.configs.configs = grp->data[i].configs;
 601                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 602         }
 603
 604         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 605                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 606
 607         return 0;
 608 }
 609
 610 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 611                                     struct pinctrl_map *map, unsigned num_maps)
 612 {
 613 }
 614
 615 static const struct pinctrl_ops rockchip_pctrl_ops = {
 616         .get_groups_count       = rockchip_get_groups_count,
 617         .get_group_name         = rockchip_get_group_name,
 618         .get_group_pins         = rockchip_get_group_pins,
 619         .dt_node_to_map         = rockchip_dt_node_to_map,
 620         .dt_free_map            = rockchip_dt_free_map,
 621 };
 622
 623 /*
 624  * Hardware access
 625  */
 626
 627 static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 628         {
 629                 .num = 2,
 630                 .pin = 12,
 631                 .reg = 0x24,
 632                 .bit = 8,
 633                 .mask = 0x3
 634         }, {
 635                 .num = 2,
 636                 .pin = 15,
 637                 .reg = 0x28,
 638                 .bit = 0,
 639                 .mask = 0x7
 640         }, {
 641                 .num = 2,
 642                 .pin = 23,
 643                 .reg = 0x30,
 644                 .bit = 14,
 645                 .mask = 0x3
 646         },
 647 };
 648
 649 static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg,
 650                               u8 *bit, int *mask)
 651 {
 652         const struct rockchip_mux_recalced_data *data = NULL;
 653         int i;
 654
 655         for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++)
 656                 if (rk3328_mux_recalced_data[i].num == bank_num &&
 657                     rk3328_mux_recalced_data[i].pin == pin) {
 658                         data = &rk3328_mux_recalced_data[i];
 659                         break;
 660                 }
 661
 662         if (!data)
 663                 return;
 664
 665         *reg = data->reg;
 666         *mask = data->mask;
 667         *bit = data->bit;
 668 }
 669
 670 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 671         {
 672                 /* pwm0-0 */
 673                 .bank_num = 0,
 674                 .pin = 26,
 675                 .func = 1,
 676                 .route_offset = 0x50,
 677                 .route_val = BIT(16),
 678         }, {
 679                 /* pwm0-1 */
 680                 .bank_num = 3,
 681                 .pin = 21,
 682                 .func = 1,
 683                 .route_offset = 0x50,
 684                 .route_val = BIT(16) | BIT(0),
 685         }, {
 686                 /* pwm1-0 */
 687                 .bank_num = 0,
 688                 .pin = 27,
 689                 .func = 1,
 690                 .route_offset = 0x50,
 691                 .route_val = BIT(16 + 1),
 692         }, {
 693                 /* pwm1-1 */
 694                 .bank_num = 0,
 695                 .pin = 30,
 696                 .func = 2,
 697                 .route_offset = 0x50,
 698                 .route_val = BIT(16 + 1) | BIT(1),
 699         }, {
 700                 /* pwm2-0 */
 701                 .bank_num = 0,
 702                 .pin = 28,
 703                 .func = 1,
 704                 .route_offset = 0x50,
 705                 .route_val = BIT(16 + 2),
 706         }, {
 707                 /* pwm2-1 */
 708                 .bank_num = 1,
 709                 .pin = 12,
 710                 .func = 2,
 711                 .route_offset = 0x50,
 712                 .route_val = BIT(16 + 2) | BIT(2),
 713         }, {
 714                 /* pwm3-0 */
 715                 .bank_num = 3,
 716                 .pin = 26,
 717                 .func = 1,
 718                 .route_offset = 0x50,
 719                 .route_val = BIT(16 + 3),
 720         }, {
 721                 /* pwm3-1 */
 722                 .bank_num = 1,
 723                 .pin = 11,
 724                 .func = 2,
 725                 .route_offset = 0x50,
 726                 .route_val = BIT(16 + 3) | BIT(3),
 727         }, {
 728                 /* sdio-0_d0 */
 729                 .bank_num = 1,
 730                 .pin = 1,
 731                 .func = 1,
 732                 .route_offset = 0x50,
 733                 .route_val = BIT(16 + 4),
 734         }, {
 735                 /* sdio-1_d0 */
 736                 .bank_num = 3,
 737                 .pin = 2,
 738                 .func = 1,
 739                 .route_offset = 0x50,
 740                 .route_val = BIT(16 + 4) | BIT(4),
 741         }, {
 742                 /* spi-0_rx */
 743                 .bank_num = 0,
 744                 .pin = 13,
 745                 .func = 2,
 746                 .route_offset = 0x50,
 747                 .route_val = BIT(16 + 5),
 748         }, {
 749                 /* spi-1_rx */
 750                 .bank_num = 2,
 751                 .pin = 0,
 752                 .func = 2,
 753                 .route_offset = 0x50,
 754                 .route_val = BIT(16 + 5) | BIT(5),
 755         }, {
 756                 /* emmc-0_cmd */
 757                 .bank_num = 1,
 758                 .pin = 22,
 759                 .func = 2,
 760                 .route_offset = 0x50,
 761                 .route_val = BIT(16 + 7),
 762         }, {
 763                 /* emmc-1_cmd */
 764                 .bank_num = 2,
 765                 .pin = 4,
 766                 .func = 2,
 767                 .route_offset = 0x50,
 768                 .route_val = BIT(16 + 7) | BIT(7),
 769         }, {
 770                 /* uart2-0_rx */
 771                 .bank_num = 1,
 772                 .pin = 19,
 773                 .func = 2,
 774                 .route_offset = 0x50,
 775                 .route_val = BIT(16 + 8),
 776         }, {
 777                 /* uart2-1_rx */
 778                 .bank_num = 1,
 779                 .pin = 10,
 780                 .func = 2,
 781                 .route_offset = 0x50,
 782                 .route_val = BIT(16 + 8) | BIT(8),
 783         }, {
 784                 /* uart1-0_rx */
 785                 .bank_num = 1,
 786                 .pin = 10,
 787                 .func = 1,
 788                 .route_offset = 0x50,
 789                 .route_val = BIT(16 + 11),
 790         }, {
 791                 /* uart1-1_rx */
 792                 .bank_num = 3,
 793                 .pin = 13,
 794                 .func = 1,
 795                 .route_offset = 0x50,
 796                 .route_val = BIT(16 + 11) | BIT(11),
 797         },
 798 };
 799
 800 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
 801         {
 802                 /* uart2dbg_rxm0 */
 803                 .bank_num = 1,
 804                 .pin = 1,
 805                 .func = 2,
 806                 .route_offset = 0x50,
 807                 .route_val = BIT(16) | BIT(16 + 1),
 808         }, {
 809                 /* uart2dbg_rxm1 */
 810                 .bank_num = 2,
 811                 .pin = 1,
 812                 .func = 1,
 813                 .route_offset = 0x50,
 814                 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
 815         }, {
 816                 /* gmac-m1-optimized_rxd0 */
 817                 .bank_num = 1,
 818                 .pin = 11,
 819                 .func = 2,
 820                 .route_offset = 0x50,
 821                 .route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10),
 822         }, {
 823                 /* pdm_sdi0m0 */
 824                 .bank_num = 2,
 825                 .pin = 19,
 826                 .func = 2,
 827                 .route_offset = 0x50,
 828                 .route_val = BIT(16 + 3),
 829         }, {
 830                 /* pdm_sdi0m1 */
 831                 .bank_num = 1,
 832                 .pin = 23,
 833                 .func = 3,
 834                 .route_offset = 0x50,
 835                 .route_val =  BIT(16 + 3) | BIT(3),
 836         }, {
 837                 /* spi_rxdm2 */
 838                 .bank_num = 3,
 839                 .pin = 2,
 840                 .func = 4,
 841                 .route_offset = 0x50,
 842                 .route_val =  BIT(16 + 4) | BIT(16 + 5) | BIT(5),
 843         }, {
 844                 /* i2s2_sdim0 */
 845                 .bank_num = 1,
 846                 .pin = 24,
 847                 .func = 1,
 848                 .route_offset = 0x50,
 849                 .route_val = BIT(16 + 6),
 850         }, {
 851                 /* i2s2_sdim1 */
 852                 .bank_num = 3,
 853                 .pin = 2,
 854                 .func = 6,
 855                 .route_offset = 0x50,
 856                 .route_val =  BIT(16 + 6) | BIT(6),
 857         }, {
 858                 /* card_iom1 */
 859                 .bank_num = 2,
 860                 .pin = 22,
 861                 .func = 3,
 862                 .route_offset = 0x50,
 863                 .route_val =  BIT(16 + 7) | BIT(7),
 864         }, {
 865                 /* tsp_d5m1 */
 866                 .bank_num = 2,
 867                 .pin = 16,
 868                 .func = 3,
 869                 .route_offset = 0x50,
 870                 .route_val =  BIT(16 + 8) | BIT(8),
 871         }, {
 872                 /* cif_data5m1 */
 873                 .bank_num = 2,
 874                 .pin = 16,
 875                 .func = 4,
 876                 .route_offset = 0x50,
 877                 .route_val =  BIT(16 + 9) | BIT(9),
 878         },
 879 };
 880
 881 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
 882         {
 883                 /* uart2dbga_rx */
 884                 .bank_num = 4,
 885                 .pin = 8,
 886                 .func = 2,
 887                 .route_offset = 0xe21c,
 888                 .route_val = BIT(16 + 10) | BIT(16 + 11),
 889         }, {
 890                 /* uart2dbgb_rx */
 891                 .bank_num = 4,
 892                 .pin = 16,
 893                 .func = 2,
 894                 .route_offset = 0xe21c,
 895                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
 896         }, {
 897                 /* uart2dbgc_rx */
 898                 .bank_num = 4,
 899                 .pin = 19,
 900                 .func = 1,
 901                 .route_offset = 0xe21c,
 902                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
 903         }, {
 904                 /* pcie_clkreqn */
 905                 .bank_num = 2,
 906                 .pin = 26,
 907                 .func = 2,
 908                 .route_offset = 0xe21c,
 909                 .route_val = BIT(16 + 14),
 910         }, {
 911                 /* pcie_clkreqnb */
 912                 .bank_num = 4,
 913                 .pin = 24,
 914                 .func = 1,
 915                 .route_offset = 0xe21c,
 916                 .route_val = BIT(16 + 14) | BIT(14),
 917         },
 918 };
 919
 920 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
 921                                    int mux, u32 *reg, u32 *value)
 922 {
 923         struct rockchip_pinctrl *info = bank->drvdata;
 924         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 925         struct rockchip_mux_route_data *data;
 926         int i;
 927
 928         for (i = 0; i < ctrl->niomux_routes; i++) {
 929                 data = &ctrl->iomux_routes[i];
 930                 if ((data->bank_num == bank->bank_num) &&
 931                     (data->pin == pin) && (data->func == mux))
 932                         break;
 933         }
 934
 935         if (i >= ctrl->niomux_routes)
 936                 return false;
 937
 938         *reg = data->route_offset;
 939         *value = data->route_val;
 940
 941         return true;
 942 }
 943
 944 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 945 {
 946         struct rockchip_pinctrl *info = bank->drvdata;
 947         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 948         int iomux_num = (pin / 8);
 949         struct regmap *regmap;
 950         unsigned int val;
 951         int reg, ret, mask, mux_type;
 952         u8 bit;
 953
 954         if (iomux_num > 3)
 955                 return -EINVAL;
 956
 957         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 958                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 959                 return -EINVAL;
 960         }
 961
 962         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 963                 return RK_FUNC_GPIO;
 964
 965         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 966                                 ? info->regmap_pmu : info->regmap_base;
 967
 968         /* get basic quadrupel of mux registers and the correct reg inside */
 969         mux_type = bank->iomux[iomux_num].type;
 970         reg = bank->iomux[iomux_num].offset;
 971         if (mux_type & IOMUX_WIDTH_4BIT) {
 972                 if ((pin % 8) >= 4)
 973                         reg += 0x4;
 974                 bit = (pin % 4) * 4;
 975                 mask = 0xf;
 976         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 977                 if ((pin % 8) >= 5)
 978                         reg += 0x4;
 979                 bit = (pin % 8 % 5) * 3;
 980                 mask = 0x7;
 981         } else {
 982                 bit = (pin % 8) * 2;
 983                 mask = 0x3;
 984         }
 985
 986         if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
 987                 ctrl->iomux_recalc(bank->bank_num, pin, &reg, &bit, &mask);
 988
 989         ret = regmap_read(regmap, reg, &val);
 990         if (ret)
 991                 return ret;
 992
 993         return ((val >> bit) & mask);
 994 }
 995
 996 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
 997                                int pin, int mux)
 998 {
 999         struct rockchip_pinctrl *info = bank->drvdata;
1000         int iomux_num = (pin / 8);
1001
1002         if (iomux_num > 3)
1003                 return -EINVAL;
1004
1005         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1006                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1007                 return -EINVAL;
1008         }
1009
1010         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1011                 if (mux != RK_FUNC_GPIO) {
1012                         dev_err(info->dev,
1013                                 "pin %d only supports a gpio mux\n", pin);
1014                         return -ENOTSUPP;
1015                 }
1016         }
1017
1018         return 0;
1019 }
1020
1021 /*
1022  * Set a new mux function for a pin.
1023  *
1024  * The register is divided into the upper and lower 16 bit. When changing
1025  * a value, the previous register value is not read and changed. Instead
1026  * it seems the changed bits are marked in the upper 16 bit, while the
1027  * changed value gets set in the same offset in the lower 16 bit.
1028  * All pin settings seem to be 2 bit wide in both the upper and lower
1029  * parts.
1030  * @bank: pin bank to change
1031  * @pin: pin to change
1032  * @mux: new mux function to set
1033  */
1034 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1035 {
1036         struct rockchip_pinctrl *info = bank->drvdata;
1037         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1038         int iomux_num = (pin / 8);
1039         struct regmap *regmap;
1040         int reg, ret, mask, mux_type;
1041         u8 bit;
1042         u32 data, rmask, route_reg, route_val;
1043
1044         ret = rockchip_verify_mux(bank, pin, mux);
1045         if (ret < 0)
1046                 return ret;
1047
1048         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1049                 return 0;
1050
1051         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1052                                                 bank->bank_num, pin, mux);
1053
1054         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1055                                 ? info->regmap_pmu : info->regmap_base;
1056
1057         /* get basic quadrupel of mux registers and the correct reg inside */
1058         mux_type = bank->iomux[iomux_num].type;
1059         reg = bank->iomux[iomux_num].offset;
1060         if (mux_type & IOMUX_WIDTH_4BIT) {
1061                 if ((pin % 8) >= 4)
1062                         reg += 0x4;
1063                 bit = (pin % 4) * 4;
1064                 mask = 0xf;
1065         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1066                 if ((pin % 8) >= 5)
1067                         reg += 0x4;
1068                 bit = (pin % 8 % 5) * 3;
1069                 mask = 0x7;
1070         } else {
1071                 bit = (pin % 8) * 2;
1072                 mask = 0x3;
1073         }
1074
1075         if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
1076                 ctrl->iomux_recalc(bank->bank_num, pin, &reg, &bit, &mask);
1077
1078         if (bank->route_mask & BIT(pin)) {
1079                 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
1080                                            &route_val)) {
1081                         ret = regmap_write(regmap, route_reg, route_val);
1082                         if (ret)
1083                                 return ret;
1084                 }
1085         }
1086
1087         data = (mask << (bit + 16));
1088         rmask = data | (data >> 16);
1089         data |= (mux & mask) << bit;
1090         ret = regmap_update_bits(regmap, reg, rmask, data);
1091
1092         return ret;
1093 }
1094
1095 #define RK2928_PULL_OFFSET              0x118
1096 #define RK2928_PULL_PINS_PER_REG        16
1097 #define RK2928_PULL_BANK_STRIDE         8
1098
1099 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1100                                     int pin_num, struct regmap **regmap,
1101                                     int *reg, u8 *bit)
1102 {
1103         struct rockchip_pinctrl *info = bank->drvdata;
1104
1105         *regmap = info->regmap_base;
1106         *reg = RK2928_PULL_OFFSET;
1107         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1108         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1109
1110         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1111 };
1112
1113 #define RK3188_PULL_OFFSET              0x164
1114 #define RK3188_PULL_BITS_PER_PIN        2
1115 #define RK3188_PULL_PINS_PER_REG        8
1116 #define RK3188_PULL_BANK_STRIDE         16
1117 #define RK3188_PULL_PMU_OFFSET          0x64
1118
1119 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1120                                     int pin_num, struct regmap **regmap,
1121                                     int *reg, u8 *bit)
1122 {
1123         struct rockchip_pinctrl *info = bank->drvdata;
1124
1125         /* The first 12 pins of the first bank are located elsewhere */
1126         if (bank->bank_num == 0 && pin_num < 12) {
1127                 *regmap = info->regmap_pmu ? info->regmap_pmu
1128                                            : bank->regmap_pull;
1129                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1130                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1131                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1132                 *bit *= RK3188_PULL_BITS_PER_PIN;
1133         } else {
1134                 *regmap = info->regmap_pull ? info->regmap_pull
1135                                             : info->regmap_base;
1136                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1137
1138                 /* correct the offset, as it is the 2nd pull register */
1139                 *reg -= 4;
1140                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1141                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1142
1143                 /*
1144                  * The bits in these registers have an inverse ordering
1145                  * with the lowest pin being in bits 15:14 and the highest
1146                  * pin in bits 1:0
1147                  */
1148                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1149                 *bit *= RK3188_PULL_BITS_PER_PIN;
1150         }
1151 }
1152
1153 #define RK3288_PULL_OFFSET              0x140
1154 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1155                                     int pin_num, struct regmap **regmap,
1156                                     int *reg, u8 *bit)
1157 {
1158         struct rockchip_pinctrl *info = bank->drvdata;
1159
1160         /* The first 24 pins of the first bank are located in PMU */
1161         if (bank->bank_num == 0) {
1162                 *regmap = info->regmap_pmu;
1163                 *reg = RK3188_PULL_PMU_OFFSET;
1164
1165                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1166                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1167                 *bit *= RK3188_PULL_BITS_PER_PIN;
1168         } else {
1169                 *regmap = info->regmap_base;
1170                 *reg = RK3288_PULL_OFFSET;
1171
1172                 /* correct the offset, as we're starting with the 2nd bank */
1173                 *reg -= 0x10;
1174                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1175                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1176
1177                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1178                 *bit *= RK3188_PULL_BITS_PER_PIN;
1179         }
1180 }
1181
1182 #define RK3288_DRV_PMU_OFFSET           0x70
1183 #define RK3288_DRV_GRF_OFFSET           0x1c0
1184 #define RK3288_DRV_BITS_PER_PIN         2
1185 #define RK3288_DRV_PINS_PER_REG         8
1186 #define RK3288_DRV_BANK_STRIDE          16
1187
1188 static enum rockchip_pin_drv_type rk3288_calc_drv_reg_and_bit(
1189                                        struct rockchip_pin_bank *bank,
1190                                        int pin_num, struct regmap **regmap,
1191                                        int *reg, u8 *bit)
1192 {
1193         struct rockchip_pinctrl *info = bank->drvdata;
1194
1195         /* The first 24 pins of the first bank are located in PMU */
1196         if (bank->bank_num == 0) {
1197                 *regmap = info->regmap_pmu;
1198                 *reg = RK3288_DRV_PMU_OFFSET;
1199
1200                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1201                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1202                 *bit *= RK3288_DRV_BITS_PER_PIN;
1203         } else {
1204                 *regmap = info->regmap_base;
1205                 *reg = RK3288_DRV_GRF_OFFSET;
1206
1207                 /* correct the offset, as we're starting with the 2nd bank */
1208                 *reg -= 0x10;
1209                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1210                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1211
1212                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1213                 *bit *= RK3288_DRV_BITS_PER_PIN;
1214         }
1215
1216         return DRV_TYPE_IO_DEFAULT;
1217 }
1218
1219 #define RK3228_PULL_OFFSET              0x100
1220
1221 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1222                                     int pin_num, struct regmap **regmap,
1223                                     int *reg, u8 *bit)
1224 {
1225         struct rockchip_pinctrl *info = bank->drvdata;
1226
1227         *regmap = info->regmap_base;
1228         *reg = RK3228_PULL_OFFSET;
1229         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1230         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1231
1232         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1233         *bit *= RK3188_PULL_BITS_PER_PIN;
1234 }
1235
1236 #define RK3228_DRV_GRF_OFFSET           0x200
1237
1238 static enum rockchip_pin_drv_type rk3228_calc_drv_reg_and_bit(
1239                                        struct rockchip_pin_bank *bank,
1240                                        int pin_num, struct regmap **regmap,
1241                                        int *reg, u8 *bit)
1242 {
1243         struct rockchip_pinctrl *info = bank->drvdata;
1244
1245         *regmap = info->regmap_base;
1246         *reg = RK3228_DRV_GRF_OFFSET;
1247         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1248         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1249
1250         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1251         *bit *= RK3288_DRV_BITS_PER_PIN;
1252
1253         return DRV_TYPE_IO_DEFAULT;
1254 }
1255
1256 #define RK3366_PULL_GRF_OFFSET          0x110
1257 #define RK3366_PULL_PMU_OFFSET          0x10
1258
1259 static void rk3366_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1260                                          int pin_num, struct regmap **regmap,
1261                                          int *reg, u8 *bit)
1262 {
1263         struct rockchip_pinctrl *info = bank->drvdata;
1264
1265         /* The bank0:32 and bank1:16 pins are located in PMU */
1266         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1267                 *regmap = info->regmap_pmu;
1268                 *reg = RK3366_PULL_PMU_OFFSET + bank->bank_num * 0x30;
1269
1270                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1271                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1272                 *bit *= RK3188_PULL_BITS_PER_PIN;
1273         } else {
1274                 *regmap = info->regmap_base;
1275                 *reg = RK3366_PULL_GRF_OFFSET;
1276
1277                 /* correct the offset, as we're starting with the 2nd bank */
1278                 *reg -= 0x20;
1279                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1280                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1281
1282                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1283                 *bit *= RK3188_PULL_BITS_PER_PIN;
1284         }
1285 }
1286
1287 #define RK3366_DRV_PMU_OFFSET           0x20
1288 #define RK3366_DRV_GRF_OFFSET           0x210
1289
1290 #define RK3366_DRV_GPIO2B3_OFFSET       0x378
1291 #define RK3366_DRV_GPIO2B3_BITS         4
1292
1293 #define RK3366_DRV_GPIO3A4_OFFSET       0x37c
1294 #define RK3366_DRV_GPIO3A4_BITS         4
1295
1296 static enum rockchip_pin_drv_type rk3366_calc_drv_reg_and_bit(
1297                                        struct rockchip_pin_bank *bank,
1298                                        int pin_num, struct regmap **regmap,
1299                                        int *reg, u8 *bit)
1300 {
1301         struct rockchip_pinctrl *info = bank->drvdata;
1302
1303         /* The bank0:32 and bank1:16 pins are located in PMU */
1304         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1305                 *regmap = info->regmap_pmu;
1306                 *reg = RK3366_DRV_PMU_OFFSET + bank->bank_num * 0x30;
1307
1308                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1309                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1310                 *bit *= RK3288_DRV_BITS_PER_PIN;
1311
1312                 return DRV_TYPE_IO_DEFAULT;
1313         } else if ((bank->bank_num == 2) && (pin_num == 11)) {
1314                 /* GPIO2B3 is a special case in bank2 */
1315                 *regmap = info->regmap_base;
1316                 *reg = RK3366_DRV_GPIO2B3_OFFSET;
1317                 *bit = RK3366_DRV_GPIO2B3_BITS;
1318
1319                 return DRV_TYPE_IO_WIDE_LEVEL;
1320         } else if ((bank->bank_num == 3) && (pin_num == 4)) {
1321                 /* GPIO3A4 is a special case in bank3 */
1322                 *regmap = info->regmap_base;
1323                 *reg = RK3366_DRV_GPIO3A4_OFFSET;
1324                 *bit = RK3366_DRV_GPIO3A4_BITS;
1325
1326                 return DRV_TYPE_IO_WIDE_LEVEL;
1327         }
1328
1329         *regmap = info->regmap_base;
1330         *reg = RK3366_DRV_GRF_OFFSET;
1331
1332         /* correct the offset, as we're starting with the 2nd bank */
1333         *reg -= 0x20;
1334         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1335         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1336
1337         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1338         *bit *= RK3288_DRV_BITS_PER_PIN;
1339
1340         /* special cases need special handle */
1341         if ((bank->bank_num == 2) && (pin_num == 14))
1342                 return DRV_TYPE_IO_WIDE_LEVEL;
1343         else if ((bank->bank_num == 2) && (pin_num == 16))
1344                 return DRV_TYPE_IO_NARROW_LEVEL;
1345         else if ((bank->bank_num == 2) && (pin_num >= 24) && (pin_num <= 26))
1346                 return DRV_TYPE_IO_WIDE_LEVEL;
1347
1348         return DRV_TYPE_IO_DEFAULT;
1349 }
1350
1351 #define RK3366_DRV_GPIO2A_EN_OFFSET     0x360
1352 #define RK3366_DRV_GPIO2A_EP_OFFSET     0x364
1353
1354 #define RK3366_DRV_GPIO2C_EN_OFFSET     0x368
1355 #define RK3366_DRV_GPIO2C_EP_OFFSET     0x36C
1356
1357 #define RK3366_DRV_GPIO2D_EN_OFFSET     0x370
1358 #define RK3366_DRV_GPIO2D_EP_OFFSET     0x374
1359
1360 #define RK3366_DRV_GPIO2B3_E_OFFSET     0x378
1361 #define RK3366_DRV_GPIO2B3_EN_BIT       0
1362 #define RK3366_DRV_GPIO2B3_EP_BIT       2
1363
1364 #define RK3366_DRV_GPIO3A4_E_OFFSET     0x37c
1365 #define RK3366_DRV_GPIO3A4_EN_BIT       0
1366 #define RK3366_DRV_GPIO3A4_EP_BIT       2
1367
1368 #define RK3366_DRV_GPIO2B6_E_OFFSET     0x404
1369 #define RK3366_DRV_GPIO2B6_EN_BIT       12
1370 #define RK3366_DRV_GPIO2B6_EP_BIT       14
1371
1372 static enum rockchip_pin_extra_drv_type rk3366_calc_drv_extra_reg_and_bit(
1373                                              struct rockchip_pin_bank *bank,
1374                                              int pin_num,
1375                                              struct regmap **regmap,
1376                                              int *reg, u8 *bit)
1377 {
1378         struct rockchip_pinctrl *info = bank->drvdata;
1379
1380         *regmap = info->regmap_base;
1381         if (bank->bank_num == 2) {
1382                 switch (pin_num / 8) {
1383                 case 0:
1384                         *reg = RK3366_DRV_GPIO2A_EN_OFFSET;
1385                         break;
1386                 case 1:
1387                         /* special cases need special handle */
1388                         if (pin_num == 11) {
1389                                 *reg = RK3366_DRV_GPIO2B3_E_OFFSET;
1390                                 *bit = RK3366_DRV_GPIO2B3_EN_BIT;
1391                         } else if (pin_num == 14) {
1392                                 *reg = RK3366_DRV_GPIO2B6_E_OFFSET;
1393                                 *bit = RK3366_DRV_GPIO2B6_EN_BIT;
1394                         } else {
1395                                 return -1;
1396                         }
1397
1398                         return DRV_TYPE_EXTRA_SAME_OFFSET;
1399                 case 2:
1400                         *reg = RK3366_DRV_GPIO2C_EN_OFFSET;
1401                         break;
1402                 case 3:
1403                         *reg = RK3366_DRV_GPIO2D_EN_OFFSET;
1404                         break;
1405                 default:
1406                         return -1;
1407                 }
1408
1409                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1410                 *bit *= RK3288_DRV_BITS_PER_PIN;
1411
1412                 return DRV_TYPE_EXTRA_SAME_BITS;
1413         }
1414
1415         /* GPIO3A4 is a special case */
1416         if ((pin_num != 4) && (bank->bank_num != 3))
1417                 return -1;
1418
1419         *reg = RK3366_DRV_GPIO3A4_E_OFFSET;
1420         *bit = RK3366_DRV_GPIO3A4_EN_BIT;
1421
1422         return DRV_TYPE_EXTRA_SAME_OFFSET;
1423 }
1424
1425 #define RK3368_PULL_GRF_OFFSET          0x100
1426 #define RK3368_PULL_PMU_OFFSET          0x10
1427
1428 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1429                                          int pin_num, struct regmap **regmap,
1430                                          int *reg, u8 *bit)
1431 {
1432         struct rockchip_pinctrl *info = bank->drvdata;
1433
1434         /* The first 32 pins of the first bank are located in PMU */
1435         if (bank->bank_num == 0) {
1436                 *regmap = info->regmap_pmu;
1437                 *reg = RK3368_PULL_PMU_OFFSET;
1438
1439                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1440                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1441                 *bit *= RK3188_PULL_BITS_PER_PIN;
1442         } else {
1443                 *regmap = info->regmap_base;
1444                 *reg = RK3368_PULL_GRF_OFFSET;
1445
1446                 /* correct the offset, as we're starting with the 2nd bank */
1447                 *reg -= 0x10;
1448                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1449                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1450
1451                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1452                 *bit *= RK3188_PULL_BITS_PER_PIN;
1453         }
1454 }
1455
1456 #define RK3368_DRV_PMU_OFFSET           0x20
1457 #define RK3368_DRV_GRF_OFFSET           0x200
1458
1459 static enum rockchip_pin_drv_type rk3368_calc_drv_reg_and_bit(
1460                                        struct rockchip_pin_bank *bank,
1461                                        int pin_num, struct regmap **regmap,
1462                                        int *reg, u8 *bit)
1463 {
1464         struct rockchip_pinctrl *info = bank->drvdata;
1465
1466         /* The first 32 pins of the first bank are located in PMU */
1467         if (bank->bank_num == 0) {
1468                 *regmap = info->regmap_pmu;
1469                 *reg = RK3368_DRV_PMU_OFFSET;
1470
1471                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1472                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1473                 *bit *= RK3288_DRV_BITS_PER_PIN;
1474         } else {
1475                 *regmap = info->regmap_base;
1476                 *reg = RK3368_DRV_GRF_OFFSET;
1477
1478                 /* correct the offset, as we're starting with the 2nd bank */
1479                 *reg -= 0x10;
1480                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1481                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1482
1483                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1484                 *bit *= RK3288_DRV_BITS_PER_PIN;
1485         }
1486
1487         return DRV_TYPE_IO_DEFAULT;
1488 }
1489
1490 #define RK3399_PULL_GRF_OFFSET          0xe040
1491 #define RK3399_PULL_PMU_OFFSET          0x40
1492 #define RK3399_DRV_3BITS_PER_PIN        3
1493
1494 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1495                                          int pin_num, struct regmap **regmap,
1496                                          int *reg, u8 *bit)
1497 {
1498         struct rockchip_pinctrl *info = bank->drvdata;
1499
1500         /* The bank0:16 and bank1:32 pins are located in PMU */
1501         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1502                 *regmap = info->regmap_pmu;
1503                 *reg = RK3399_PULL_PMU_OFFSET;
1504
1505                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1506
1507                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1508                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1509                 *bit *= RK3188_PULL_BITS_PER_PIN;
1510         } else {
1511                 *regmap = info->regmap_base;
1512                 *reg = RK3399_PULL_GRF_OFFSET;
1513
1514                 /* correct the offset, as we're starting with the 3rd bank */
1515                 *reg -= 0x20;
1516                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1517                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1518
1519                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1520                 *bit *= RK3188_PULL_BITS_PER_PIN;
1521         }
1522 }
1523
1524 static enum rockchip_pin_drv_type rk3399_calc_drv_reg_and_bit(
1525                                        struct rockchip_pin_bank *bank,
1526                                        int pin_num, struct regmap **regmap,
1527                                        int *reg, u8 *bit)
1528 {
1529         struct rockchip_pinctrl *info = bank->drvdata;
1530         int drv_num = (pin_num / 8);
1531
1532         /*  The bank0:16 and bank1:32 pins are located in PMU */
1533         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1534                 *regmap = info->regmap_pmu;
1535         else
1536                 *regmap = info->regmap_base;
1537
1538         *reg = bank->drv[drv_num].offset;
1539         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1540             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1541                 *bit = (pin_num % 8) * 3;
1542         else
1543                 *bit = (pin_num % 8) * 2;
1544
1545         return DRV_TYPE_IO_DEFAULT;
1546 }
1547
1548 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1549         { 2, 4, 8, 12, -1, -1, -1, -1 },
1550         { 3, 6, 9, 12, -1, -1, -1, -1 },
1551         { 5, 10, 15, 20, -1, -1, -1, -1 },
1552         { 4, 6, 8, 10, 12, 14, 16, 18 },
1553         { 4, 7, 10, 13, 16, 19, 22, 26 },
1554         { 0, 6, 12, 18, -1, -1, -1, -1 },
1555         { 4, 8, 12, 16, -1, -1, -1, -1 }
1556 };
1557
1558 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1559                                      int pin_num)
1560 {
1561         struct rockchip_pinctrl *info = bank->drvdata;
1562         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1563         struct regmap *regmap, *extra_regmap;
1564         int reg, ret, extra_reg;
1565         u32 data, temp, rmask_bits;
1566         u8 bit, extra_bit;
1567         int drv_type;
1568
1569         drv_type = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1570         if (!drv_type)
1571                 drv_type = bank->drv[pin_num / 8].drv_type;
1572
1573         switch (drv_type) {
1574         case DRV_TYPE_IO_1V8_3V0_AUTO:
1575         case DRV_TYPE_IO_3V3_ONLY:
1576                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1577                 switch (bit) {
1578                 case 0 ... 12:
1579                         /* regular case, nothing to do */
1580                         break;
1581                 case 15:
1582                         /*
1583                          * drive-strength offset is special, as it is
1584                          * spread over 2 registers
1585                          */
1586                         ret = regmap_read(regmap, reg, &data);
1587                         if (ret)
1588                                 return ret;
1589
1590                         ret = regmap_read(regmap, reg + 0x4, &temp);
1591                         if (ret)
1592                                 return ret;
1593
1594                         /*
1595                          * the bit data[15] contains bit 0 of the value
1596                          * while temp[1:0] contains bits 2 and 1
1597                          */
1598                         data >>= 15;
1599                         temp &= 0x3;
1600                         temp <<= 1;
1601                         data |= temp;
1602
1603                         return rockchip_perpin_drv_list[drv_type][data];
1604                 case 18 ... 21:
1605                         /* setting fully enclosed in the second register */
1606                         reg += 4;
1607                         bit -= 16;
1608                         break;
1609                 default:
1610                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1611                                 bit, drv_type);
1612                         return -EINVAL;
1613                 }
1614
1615                 break;
1616         case DRV_TYPE_IO_WIDE_LEVEL:
1617                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1618                 /* enable the write to the equivalent lower bits */
1619                 ret = regmap_read(regmap, reg, &data);
1620                 if (ret)
1621                         return ret;
1622                 data >>= bit;
1623                 data &= (1 << rmask_bits) - 1;
1624
1625                 /*
1626                  * assume the drive strength of N channel and
1627                  * P channel are the same.
1628                  */
1629                 if (ctrl->drv_calc_extra_reg)
1630                         ctrl->drv_calc_extra_reg(bank, pin_num,
1631                                                  &extra_regmap,
1632                                                  &extra_reg,
1633                                                  &extra_bit);
1634
1635                 /*
1636                  * It is enough to read one channel drive strength,
1637                  * this is N channel.
1638                  */
1639                 ret = regmap_read(extra_regmap, extra_reg, &temp);
1640                 if (ret)
1641                         return ret;
1642
1643                 temp >>= extra_bit;
1644                 temp &= (1 << rmask_bits) - 1;
1645
1646                 return (rockchip_perpin_drv_list[drv_type][data]) + (temp * 2);
1647         case DRV_TYPE_IO_DEFAULT:
1648         case DRV_TYPE_IO_1V8_OR_3V0:
1649         case DRV_TYPE_IO_1V8_ONLY:
1650         case DRV_TYPE_IO_NARROW_LEVEL:
1651                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1652                 break;
1653         default:
1654                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1655                         drv_type);
1656                 return -EINVAL;
1657         }
1658
1659         ret = regmap_read(regmap, reg, &data);
1660         if (ret)
1661                 return ret;
1662
1663         data >>= bit;
1664         data &= (1 << rmask_bits) - 1;
1665
1666         return rockchip_perpin_drv_list[drv_type][data];
1667 }
1668
1669 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1670                                      int pin_num, int strength)
1671 {
1672         struct rockchip_pinctrl *info = bank->drvdata;
1673         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1674         struct regmap *regmap, *extra_regmap;
1675         int reg, ret, i;
1676         u32 data, temp, rmask, rmask_bits;
1677         u8 bit, extra_bit;
1678         int drv_type, extra_drv_type = 0;
1679         int extra_value, extra_reg;
1680
1681         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1682                 bank->bank_num, pin_num, strength);
1683
1684         drv_type = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1685         if (!drv_type)
1686                 drv_type = bank->drv[pin_num / 8].drv_type;
1687
1688         ret = -EINVAL;
1689
1690         if (drv_type == DRV_TYPE_IO_WIDE_LEVEL) {
1691                 if ((strength % 2 == 0) && (strength <= 24))
1692                         ret = ((strength > 18) ? 18 : strength) / 6;
1693         } else {
1694                 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]);
1695                      i++) {
1696                         if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1697                                 ret = rockchip_perpin_drv_list[drv_type][i];
1698                                 break;
1699                         } else if (rockchip_perpin_drv_list[drv_type][i] ==
1700                                    strength) {
1701                                 ret = i;
1702                                 break;
1703                         }
1704                 }
1705         }
1706
1707         if (ret < 0) {
1708                 dev_err(info->dev, "unsupported driver strength %d\n",
1709                         strength);
1710                 return ret;
1711         }
1712
1713         switch (drv_type) {
1714         case DRV_TYPE_IO_1V8_3V0_AUTO:
1715         case DRV_TYPE_IO_3V3_ONLY:
1716                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1717                 switch (bit) {
1718                 case 0 ... 12:
1719                         /* regular case, nothing to do */
1720                         break;
1721                 case 15:
1722                         /*
1723                          * drive-strength offset is special, as it is spread
1724                          * over 2 registers, the bit data[15] contains bit 0
1725                          * of the value while temp[1:0] contains bits 2 and 1
1726                          */
1727                         data = (ret & 0x1) << 15;
1728                         temp = (ret >> 0x1) & 0x3;
1729
1730                         rmask = BIT(15) | BIT(31);
1731                         data |= BIT(31);
1732                         ret = regmap_update_bits(regmap, reg, rmask, data);
1733                         if (ret)
1734                                 return ret;
1735
1736                         rmask = 0x3 | (0x3 << 16);
1737                         temp |= (0x3 << 16);
1738                         reg += 0x4;
1739                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1740
1741                         return ret;
1742                 case 18 ... 21:
1743                         /* setting fully enclosed in the second register */
1744                         reg += 4;
1745                         bit -= 16;
1746                         break;
1747                 default:
1748                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1749                                 bit, drv_type);
1750                         return -EINVAL;
1751                 }
1752                 break;
1753         case DRV_TYPE_IO_WIDE_LEVEL:
1754                 extra_value = ((strength -
1755                                 rockchip_perpin_drv_list[drv_type][ret])) >> 1;
1756                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1757
1758                 /*
1759                  * assume the drive strength of N channel and
1760                  * P channel are the same.
1761                  */
1762                 if (ctrl->drv_calc_extra_reg)
1763                         extra_drv_type = ctrl->drv_calc_extra_reg(bank, pin_num,
1764                                                                   &extra_regmap,
1765                                                                   &extra_reg,
1766                                                                   &extra_bit);
1767
1768                 /* enable the write to the equivalent lower bits */
1769                 data = ((1 << rmask_bits) - 1) << (extra_bit + 16);
1770                 rmask = data | (data >> 16);
1771                 data |= (extra_value << extra_bit);
1772
1773                 /* write drive strength of N channel */
1774                 if (regmap_update_bits(extra_regmap, extra_reg, rmask, data))
1775                         return -EINVAL;
1776
1777                 if (extra_drv_type == DRV_TYPE_EXTRA_SAME_OFFSET)
1778                         extra_bit += 2;
1779                 else if (extra_drv_type == DRV_TYPE_EXTRA_SAME_BITS)
1780                         extra_reg += 0x4;
1781                 else
1782                         return -EINVAL;
1783
1784                 /* enable the write to the equivalent lower bits */
1785                 data = ((1 << rmask_bits) - 1) << (extra_bit + 16);
1786                 rmask = data | (data >> 16);
1787                 data |= (extra_value << extra_bit);
1788
1789                 /* write drive strength of P channel */
1790                 if (regmap_update_bits(extra_regmap, extra_reg, rmask, data))
1791                         return -EINVAL;
1792
1793                 break;
1794         case DRV_TYPE_IO_DEFAULT:
1795         case DRV_TYPE_IO_1V8_OR_3V0:
1796         case DRV_TYPE_IO_1V8_ONLY:
1797         case DRV_TYPE_IO_NARROW_LEVEL:
1798                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1799                 break;
1800         default:
1801                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1802                         drv_type);
1803                 return -EINVAL;
1804         }
1805
1806         /* enable the write to the equivalent lower bits */
1807         data = ((1 << rmask_bits) - 1) << (bit + 16);
1808         rmask = data | (data >> 16);
1809         data |= (ret << bit);
1810
1811         ret = regmap_update_bits(regmap, reg, rmask, data);
1812
1813         return ret;
1814 }
1815
1816 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1817         {
1818                 PIN_CONFIG_BIAS_DISABLE,
1819                 PIN_CONFIG_BIAS_PULL_UP,
1820                 PIN_CONFIG_BIAS_PULL_DOWN,
1821                 PIN_CONFIG_BIAS_BUS_HOLD
1822         },
1823         {
1824                 PIN_CONFIG_BIAS_DISABLE,
1825                 PIN_CONFIG_BIAS_PULL_DOWN,
1826                 PIN_CONFIG_BIAS_DISABLE,
1827                 PIN_CONFIG_BIAS_PULL_UP
1828         },
1829 };
1830
1831 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1832 {
1833         struct rockchip_pinctrl *info = bank->drvdata;
1834         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1835         struct regmap *regmap;
1836         int reg, ret, pull_type;
1837         u8 bit;
1838         u32 data;
1839
1840         /* rk3066b does support any pulls */
1841         if (ctrl->type == RK3066B)
1842                 return PIN_CONFIG_BIAS_DISABLE;
1843
1844         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1845
1846         ret = regmap_read(regmap, reg, &data);
1847         if (ret)
1848                 return ret;
1849
1850         switch (ctrl->type) {
1851         case RK2928:
1852                 return !(data & BIT(bit))
1853                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1854                                 : PIN_CONFIG_BIAS_DISABLE;
1855         case RK3188:
1856         case RK3288:
1857         case RK3366:
1858         case RK3368:
1859         case RK3399:
1860                 pull_type = bank->pull_type[pin_num / 8];
1861                 data >>= bit;
1862                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1863
1864                 return rockchip_pull_list[pull_type][data];
1865         default:
1866                 dev_err(info->dev, "unsupported pinctrl type\n");
1867                 return -EINVAL;
1868         };
1869 }
1870
1871 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1872                                         int pin_num, int pull)
1873 {
1874         struct rockchip_pinctrl *info = bank->drvdata;
1875         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1876         struct regmap *regmap;
1877         int reg, ret, i, pull_type;
1878         u8 bit;
1879         u32 data, rmask;
1880
1881         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1882                  bank->bank_num, pin_num, pull);
1883
1884         /* rk3066b does support any pulls */
1885         if (ctrl->type == RK3066B)
1886                 return pull ? -EINVAL : 0;
1887
1888         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1889
1890         switch (ctrl->type) {
1891         case RK2928:
1892                 data = BIT(bit + 16);
1893                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1894                         data |= BIT(bit);
1895                 ret = regmap_write(regmap, reg, data);
1896                 break;
1897         case RK3188:
1898         case RK3288:
1899         case RK3366:
1900         case RK3368:
1901         case RK3399:
1902                 pull_type = bank->pull_type[pin_num / 8];
1903                 ret = -EINVAL;
1904                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1905                         i++) {
1906                         if (rockchip_pull_list[pull_type][i] == pull) {
1907                                 ret = i;
1908                                 break;
1909                         }
1910                 }
1911
1912                 if (ret < 0) {
1913                         dev_err(info->dev, "unknown pull setting %d\n", pull);
1914                         return ret;
1915                 }
1916
1917                 /* enable the write to the equivalent lower bits */
1918                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1919                 rmask = data | (data >> 16);
1920                 data |= (ret << bit);
1921
1922                 ret = regmap_update_bits(regmap, reg, rmask, data);
1923                 break;
1924         default:
1925                 dev_err(info->dev, "unsupported pinctrl type\n");
1926                 return -EINVAL;
1927         }
1928
1929         return ret;
1930 }
1931
1932 #define RK3328_SCHMITT_BITS_PER_PIN             1
1933 #define RK3328_SCHMITT_PINS_PER_REG             16
1934 #define RK3328_SCHMITT_BANK_STRIDE              8
1935 #define RK3328_SCHMITT_GRF_OFFSET               0x380
1936
1937 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1938                                            int pin_num,
1939                                            struct regmap **regmap,
1940                                            int *reg, u8 *bit)
1941 {
1942         struct rockchip_pinctrl *info = bank->drvdata;
1943
1944         *regmap = info->regmap_base;
1945         *reg = RK3328_SCHMITT_GRF_OFFSET;
1946
1947         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1948         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1949         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1950
1951         return 0;
1952 }
1953
1954 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1955 {
1956         struct rockchip_pinctrl *info = bank->drvdata;
1957         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1958         struct regmap *regmap;
1959         int reg, ret;
1960         u8 bit;
1961         u32 data;
1962
1963         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1964         if (ret)
1965                 return ret;
1966
1967         ret = regmap_read(regmap, reg, &data);
1968         if (ret)
1969                 return ret;
1970
1971         data >>= bit;
1972         return data & 0x1;
1973 }
1974
1975 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1976                                 int pin_num, int enable)
1977 {
1978         struct rockchip_pinctrl *info = bank->drvdata;
1979         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1980         struct regmap *regmap;
1981         int reg, ret;
1982         u8 bit;
1983         u32 data, rmask;
1984
1985         dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
1986                 bank->bank_num, pin_num, enable);
1987
1988         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1989         if (ret)
1990                 return ret;
1991
1992         /* enable the write to the equivalent lower bits */
1993         data = BIT(bit + 16) | (enable << bit);
1994         rmask = BIT(bit + 16) | BIT(bit);
1995
1996         return regmap_update_bits(regmap, reg, rmask, data);
1997 }
1998
1999 /*
2000  * Pinmux_ops handling
2001  */
2002
2003 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2004 {
2005         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2006
2007         return info->nfunctions;
2008 }
2009
2010 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2011                                           unsigned selector)
2012 {
2013         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2014
2015         return info->functions[selector].name;
2016 }
2017
2018 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2019                                 unsigned selector, const char * const **groups,
2020                                 unsigned * const num_groups)
2021 {
2022         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2023
2024         *groups = info->functions[selector].groups;
2025         *num_groups = info->functions[selector].ngroups;
2026
2027         return 0;
2028 }
2029
2030 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2031                             unsigned group)
2032 {
2033         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2034         const unsigned int *pins = info->groups[group].pins;
2035         const struct rockchip_pin_config *data = info->groups[group].data;
2036         struct rockchip_pin_bank *bank;
2037         int cnt, ret = 0;
2038
2039         dev_dbg(info->dev, "enable function %s group %s\n",
2040                 info->functions[selector].name, info->groups[group].name);
2041
2042         /*
2043          * for each pin in the pin group selected, program the correspoding pin
2044          * pin function number in the config register.
2045          */
2046         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2047                 bank = pin_to_bank(info, pins[cnt]);
2048                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2049                                        data[cnt].func);
2050                 if (ret)
2051                         break;
2052         }
2053
2054         if (ret) {
2055                 /* revert the already done pin settings */
2056                 for (cnt--; cnt >= 0; cnt--)
2057                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2058
2059                 return ret;
2060         }
2061
2062         return 0;
2063 }
2064
2065 /*
2066  * The calls to gpio_direction_output() and gpio_direction_input()
2067  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2068  * function called from the gpiolib interface).
2069  */
2070 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2071                                             int pin, bool input)
2072 {
2073         struct rockchip_pin_bank *bank;
2074         int ret;
2075         unsigned long flags;
2076         u32 data;
2077
2078         bank = gc_to_pin_bank(chip);
2079
2080         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2081         if (ret < 0)
2082                 return ret;
2083
2084         clk_enable(bank->clk);
2085         raw_spin_lock_irqsave(&bank->slock, flags);
2086
2087         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2088         /* set bit to 1 for output, 0 for input */
2089         if (!input)
2090                 data |= BIT(pin);
2091         else
2092                 data &= ~BIT(pin);
2093         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2094
2095         raw_spin_unlock_irqrestore(&bank->slock, flags);
2096         clk_disable(bank->clk);
2097
2098         return 0;
2099 }
2100
2101 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2102                                               struct pinctrl_gpio_range *range,
2103                                               unsigned offset, bool input)
2104 {
2105         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2106         struct gpio_chip *chip;
2107         int pin;
2108
2109         chip = range->gc;
2110         pin = offset - chip->base;
2111         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2112                  offset, range->name, pin, input ? "input" : "output");
2113
2114         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2115                                                 input);
2116 }
2117
2118 static const struct pinmux_ops rockchip_pmx_ops = {
2119         .get_functions_count    = rockchip_pmx_get_funcs_count,
2120         .get_function_name      = rockchip_pmx_get_func_name,
2121         .get_function_groups    = rockchip_pmx_get_groups,
2122         .set_mux                = rockchip_pmx_set,
2123         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
2124 };
2125
2126 /*
2127  * Pinconf_ops handling
2128  */
2129
2130 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2131                                         enum pin_config_param pull)
2132 {
2133         switch (ctrl->type) {
2134         case RK2928:
2135                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2136                                         pull == PIN_CONFIG_BIAS_DISABLE);
2137         case RK3066B:
2138                 return pull ? false : true;
2139         case RK3188:
2140         case RK3288:
2141         case RK3366:
2142         case RK3368:
2143         case RK3399:
2144                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2145         }
2146
2147         return false;
2148 }
2149
2150 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2151 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2152
2153 /* set the pin config settings for a specified pin */
2154 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2155                                 unsigned long *configs, unsigned num_configs)
2156 {
2157         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2158         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2159         enum pin_config_param param;
2160         u16 arg;
2161         int i;
2162         int rc;
2163
2164         for (i = 0; i < num_configs; i++) {
2165                 param = pinconf_to_config_param(configs[i]);
2166                 arg = pinconf_to_config_argument(configs[i]);
2167
2168                 switch (param) {
2169                 case PIN_CONFIG_BIAS_DISABLE:
2170                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2171                                 param);
2172                         if (rc)
2173                                 return rc;
2174                         break;
2175                 case PIN_CONFIG_BIAS_PULL_UP:
2176                 case PIN_CONFIG_BIAS_PULL_DOWN:
2177                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2178                 case PIN_CONFIG_BIAS_BUS_HOLD:
2179                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2180                                 return -ENOTSUPP;
2181
2182                         if (!arg)
2183                                 return -EINVAL;
2184
2185                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
2186                                 param);
2187                         if (rc)
2188                                 return rc;
2189                         break;
2190                 case PIN_CONFIG_OUTPUT:
2191                         rockchip_gpio_set(&bank->gpio_chip,
2192                                           pin - bank->pin_base, arg);
2193                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2194                                           pin - bank->pin_base, false);
2195                         if (rc)
2196                                 return rc;
2197                         break;
2198                 case PIN_CONFIG_DRIVE_STRENGTH:
2199                         /* rk3288 is the first with per-pin drive-strength */
2200                         if (!info->ctrl->drv_calc_reg)
2201                                 return -ENOTSUPP;
2202
2203                         rc = rockchip_set_drive_perpin(bank,
2204                                                 pin - bank->pin_base, arg);
2205                         if (rc < 0)
2206                                 return rc;
2207                         break;
2208                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2209                         if (!info->ctrl->schmitt_calc_reg)
2210                                 return -ENOTSUPP;
2211
2212                         rc = rockchip_set_schmitt(bank,
2213                                                   pin - bank->pin_base, arg);
2214                         if (rc < 0)
2215                                 return rc;
2216                         break;
2217                 default:
2218                         return -ENOTSUPP;
2219                         break;
2220                 }
2221         } /* for each config */
2222
2223         return 0;
2224 }
2225
2226 /* get the pin config settings for a specified pin */
2227 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2228                                                         unsigned long *config)
2229 {
2230         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2231         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2232         enum pin_config_param param = pinconf_to_config_param(*config);
2233         u16 arg;
2234         int rc;
2235
2236         switch (param) {
2237         case PIN_CONFIG_BIAS_DISABLE:
2238                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2239                         return -EINVAL;
2240
2241                 arg = 0;
2242                 break;
2243         case PIN_CONFIG_BIAS_PULL_UP:
2244         case PIN_CONFIG_BIAS_PULL_DOWN:
2245         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2246         case PIN_CONFIG_BIAS_BUS_HOLD:
2247                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2248                         return -ENOTSUPP;
2249
2250                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2251                         return -EINVAL;
2252
2253                 arg = 1;
2254                 break;
2255         case PIN_CONFIG_OUTPUT:
2256                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2257                 if (rc != RK_FUNC_GPIO)
2258                         return -EINVAL;
2259
2260                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2261                 if (rc < 0)
2262                         return rc;
2263
2264                 arg = rc ? 1 : 0;
2265                 break;
2266         case PIN_CONFIG_DRIVE_STRENGTH:
2267                 /* rk3288 is the first with per-pin drive-strength */
2268                 if (!info->ctrl->drv_calc_reg)
2269                         return -ENOTSUPP;
2270
2271                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2272                 if (rc < 0)
2273                         return rc;
2274
2275                 arg = rc;
2276                 break;
2277         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2278                 if (!info->ctrl->schmitt_calc_reg)
2279                         return -ENOTSUPP;
2280
2281                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2282                 if (rc < 0)
2283                         return rc;
2284
2285                 arg = rc;
2286                 break;
2287         default:
2288                 return -ENOTSUPP;
2289                 break;
2290         }
2291
2292         *config = pinconf_to_config_packed(param, arg);
2293
2294         return 0;
2295 }
2296
2297 static const struct pinconf_ops rockchip_pinconf_ops = {
2298         .pin_config_get                 = rockchip_pinconf_get,
2299         .pin_config_set                 = rockchip_pinconf_set,
2300         .is_generic                     = true,
2301 };
2302
2303 static const struct of_device_id rockchip_bank_match[] = {
2304         { .compatible = "rockchip,gpio-bank" },
2305         { .compatible = "rockchip,rk3188-gpio-bank0" },
2306         {},
2307 };
2308
2309 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2310                                                 struct device_node *np)
2311 {
2312         struct device_node *child;
2313
2314         for_each_child_of_node(np, child) {
2315                 if (of_match_node(rockchip_bank_match, child))
2316                         continue;
2317
2318                 info->nfunctions++;
2319                 info->ngroups += of_get_child_count(child);
2320         }
2321 }
2322
2323 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2324                                               struct rockchip_pin_group *grp,
2325                                               struct rockchip_pinctrl *info,
2326                                               u32 index)
2327 {
2328         struct rockchip_pin_bank *bank;
2329         int size;
2330         const __be32 *list;
2331         int num;
2332         int i, j;
2333         int ret;
2334
2335         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
2336
2337         /* Initialise group */
2338         grp->name = np->name;
2339
2340         /*
2341          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2342          * do sanity check and calculate pins number
2343          */
2344         list = of_get_property(np, "rockchip,pins", &size);
2345         /* we do not check return since it's safe node passed down */
2346         size /= sizeof(*list);
2347         if (!size || size % 4) {
2348                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2349                 return -EINVAL;
2350         }
2351
2352         grp->npins = size / 4;
2353
2354         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
2355                                                 GFP_KERNEL);
2356         grp->data = devm_kzalloc(info->dev, grp->npins *
2357                                           sizeof(struct rockchip_pin_config),
2358                                         GFP_KERNEL);
2359         if (!grp->pins || !grp->data)
2360                 return -ENOMEM;
2361
2362         for (i = 0, j = 0; i < size; i += 4, j++) {
2363                 const __be32 *phandle;
2364                 struct device_node *np_config;
2365
2366                 num = be32_to_cpu(*list++);
2367                 bank = bank_num_to_bank(info, num);
2368                 if (IS_ERR(bank))
2369                         return PTR_ERR(bank);
2370
2371                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2372                 grp->data[j].func = be32_to_cpu(*list++);
2373
2374                 phandle = list++;
2375                 if (!phandle)
2376                         return -EINVAL;
2377
2378                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2379                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2380                                 &grp->data[j].configs, &grp->data[j].nconfigs);
2381                 if (ret)
2382                         return ret;
2383         }
2384
2385         return 0;
2386 }
2387
2388 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2389                                                 struct rockchip_pinctrl *info,
2390                                                 u32 index)
2391 {
2392         struct device_node *child;
2393         struct rockchip_pmx_func *func;
2394         struct rockchip_pin_group *grp;
2395         int ret;
2396         static u32 grp_index;
2397         u32 i = 0;
2398
2399         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
2400
2401         func = &info->functions[index];
2402
2403         /* Initialise function */
2404         func->name = np->name;
2405         func->ngroups = of_get_child_count(np);
2406         if (func->ngroups <= 0)
2407                 return 0;
2408
2409         func->groups = devm_kzalloc(info->dev,
2410                         func->ngroups * sizeof(char *), GFP_KERNEL);
2411         if (!func->groups)
2412                 return -ENOMEM;
2413
2414         for_each_child_of_node(np, child) {
2415                 func->groups[i] = child->name;
2416                 grp = &info->groups[grp_index++];
2417                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2418                 if (ret) {
2419                         of_node_put(child);
2420                         return ret;
2421                 }
2422         }
2423
2424         return 0;
2425 }
2426
2427 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2428                                               struct rockchip_pinctrl *info)
2429 {
2430         struct device *dev = &pdev->dev;
2431         struct device_node *np = dev->of_node;
2432         struct device_node *child;
2433         int ret;
2434         int i;
2435
2436         rockchip_pinctrl_child_count(info, np);
2437
2438         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2439         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2440
2441         info->functions = devm_kzalloc(dev, info->nfunctions *
2442                                               sizeof(struct rockchip_pmx_func),
2443                                               GFP_KERNEL);
2444         if (!info->functions) {
2445                 dev_err(dev, "failed to allocate memory for function list\n");
2446                 return -EINVAL;
2447         }
2448
2449         info->groups = devm_kzalloc(dev, info->ngroups *
2450                                             sizeof(struct rockchip_pin_group),
2451                                             GFP_KERNEL);
2452         if (!info->groups) {
2453                 dev_err(dev, "failed allocate memory for ping group list\n");
2454                 return -EINVAL;
2455         }
2456
2457         i = 0;
2458
2459         for_each_child_of_node(np, child) {
2460                 if (of_match_node(rockchip_bank_match, child))
2461                         continue;
2462
2463                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2464                 if (ret) {
2465                         dev_err(&pdev->dev, "failed to parse function\n");
2466                         of_node_put(child);
2467                         return ret;
2468                 }
2469         }
2470
2471         return 0;
2472 }
2473
2474 static int rockchip_pinctrl_register(struct platform_device *pdev,
2475                                         struct rockchip_pinctrl *info)
2476 {
2477         struct pinctrl_desc *ctrldesc = &info->pctl;
2478         struct pinctrl_pin_desc *pindesc, *pdesc;
2479         struct rockchip_pin_bank *pin_bank;
2480         int pin, bank, ret;
2481         int k;
2482
2483         ctrldesc->name = "rockchip-pinctrl";
2484         ctrldesc->owner = THIS_MODULE;
2485         ctrldesc->pctlops = &rockchip_pctrl_ops;
2486         ctrldesc->pmxops = &rockchip_pmx_ops;
2487         ctrldesc->confops = &rockchip_pinconf_ops;
2488
2489         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
2490                         info->ctrl->nr_pins, GFP_KERNEL);
2491         if (!pindesc) {
2492                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
2493                 return -ENOMEM;
2494         }
2495         ctrldesc->pins = pindesc;
2496         ctrldesc->npins = info->ctrl->nr_pins;
2497
2498         pdesc = pindesc;
2499         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2500                 pin_bank = &info->ctrl->pin_banks[bank];
2501                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2502                         pdesc->number = k;
2503                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2504                                                 pin_bank->name, pin);
2505                         pdesc++;
2506                 }
2507         }
2508
2509         ret = rockchip_pinctrl_parse_dt(pdev, info);
2510         if (ret)
2511                 return ret;
2512
2513         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
2514         if (IS_ERR(info->pctl_dev)) {
2515                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2516                 return PTR_ERR(info->pctl_dev);
2517         }
2518
2519         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2520                 pin_bank = &info->ctrl->pin_banks[bank];
2521                 pin_bank->grange.name = pin_bank->name;
2522                 pin_bank->grange.id = bank;
2523                 pin_bank->grange.pin_base = pin_bank->pin_base;
2524                 pin_bank->grange.base = pin_bank->gpio_chip.base;
2525                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2526                 pin_bank->grange.gc = &pin_bank->gpio_chip;
2527                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2528         }
2529
2530         return 0;
2531 }
2532
2533 /*
2534  * GPIO handling
2535  */
2536
2537 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2538 {
2539         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2540         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2541         unsigned long flags;
2542         u32 data;
2543
2544         clk_enable(bank->clk);
2545         raw_spin_lock_irqsave(&bank->slock, flags);
2546
2547         data = readl(reg);
2548         data &= ~BIT(offset);
2549         if (value)
2550                 data |= BIT(offset);
2551         writel(data, reg);
2552
2553         raw_spin_unlock_irqrestore(&bank->slock, flags);
2554         clk_disable(bank->clk);
2555 }
2556
2557 /*
2558  * Returns the level of the pin for input direction and setting of the DR
2559  * register for output gpios.
2560  */
2561 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2562 {
2563         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2564         u32 data;
2565
2566         clk_enable(bank->clk);
2567         data = readl(bank->reg_base + GPIO_EXT_PORT);
2568         clk_disable(bank->clk);
2569         data >>= offset;
2570         data &= 1;
2571         return data;
2572 }
2573
2574 /*
2575  * gpiolib gpio_direction_input callback function. The setting of the pin
2576  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2577  * interface.
2578  */
2579 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2580 {
2581         return pinctrl_gpio_direction_input(gc->base + offset);
2582 }
2583
2584 /*
2585  * gpiolib gpio_direction_output callback function. The setting of the pin
2586  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2587  * interface.
2588  */
2589 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2590                                           unsigned offset, int value)
2591 {
2592         rockchip_gpio_set(gc, offset, value);
2593         return pinctrl_gpio_direction_output(gc->base + offset);
2594 }
2595
2596 /*
2597  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2598  * and a virtual IRQ, if not already present.
2599  */
2600 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2601 {
2602         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2603         unsigned int virq;
2604
2605         if (!bank->domain)
2606                 return -ENXIO;
2607
2608         virq = irq_create_mapping(bank->domain, offset);
2609
2610         return (virq) ? : -ENXIO;
2611 }
2612
2613 static const struct gpio_chip rockchip_gpiolib_chip = {
2614         .request = gpiochip_generic_request,
2615         .free = gpiochip_generic_free,
2616         .set = rockchip_gpio_set,
2617         .get = rockchip_gpio_get,
2618         .direction_input = rockchip_gpio_direction_input,
2619         .direction_output = rockchip_gpio_direction_output,
2620         .to_irq = rockchip_gpio_to_irq,
2621         .owner = THIS_MODULE,
2622 };
2623
2624 /*
2625  * Interrupt handling
2626  */
2627
2628 static void rockchip_irq_demux(struct irq_desc *desc)
2629 {
2630         struct irq_chip *chip = irq_desc_get_chip(desc);
2631         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2632         u32 pend;
2633
2634         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2635
2636         chained_irq_enter(chip, desc);
2637
2638         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2639
2640         while (pend) {
2641                 unsigned int irq, virq;
2642
2643                 irq = __ffs(pend);
2644                 pend &= ~BIT(irq);
2645                 virq = irq_linear_revmap(bank->domain, irq);
2646
2647                 if (!virq) {
2648                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2649                         continue;
2650                 }
2651
2652                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2653
2654                 /*
2655                  * Triggering IRQ on both rising and falling edge
2656                  * needs manual intervention.
2657                  */
2658                 if (bank->toggle_edge_mode & BIT(irq)) {
2659                         u32 data, data_old, polarity;
2660                         unsigned long flags;
2661
2662                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2663                         do {
2664                                 raw_spin_lock_irqsave(&bank->slock, flags);
2665
2666                                 polarity = readl_relaxed(bank->reg_base +
2667                                                          GPIO_INT_POLARITY);
2668                                 if (data & BIT(irq))
2669                                         polarity &= ~BIT(irq);
2670                                 else
2671                                         polarity |= BIT(irq);
2672                                 writel(polarity,
2673                                        bank->reg_base + GPIO_INT_POLARITY);
2674
2675                                 raw_spin_unlock_irqrestore(&bank->slock, flags);
2676
2677                                 data_old = data;
2678                                 data = readl_relaxed(bank->reg_base +
2679                                                      GPIO_EXT_PORT);
2680                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2681                 }
2682
2683                 generic_handle_irq(virq);
2684         }
2685
2686         chained_irq_exit(chip, desc);
2687 }
2688
2689 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2690 {
2691         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2692         struct rockchip_pin_bank *bank = gc->private;
2693         u32 mask = BIT(d->hwirq);
2694         u32 polarity;
2695         u32 level;
2696         u32 data;
2697         unsigned long flags;
2698         int ret;
2699
2700         /* make sure the pin is configured as gpio input */
2701         ret = rockchip_verify_mux(bank, d->hwirq, RK_FUNC_GPIO);
2702         if (ret < 0)
2703                 return ret;
2704
2705         bank->new_irqs |= mask;
2706
2707         raw_spin_lock_irqsave(&bank->slock, flags);
2708
2709         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2710         data &= ~mask;
2711         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2712
2713         raw_spin_unlock_irqrestore(&bank->slock, flags);
2714
2715         if (type & IRQ_TYPE_EDGE_BOTH)
2716                 irq_set_handler_locked(d, handle_edge_irq);
2717         else
2718                 irq_set_handler_locked(d, handle_level_irq);
2719
2720         raw_spin_lock_irqsave(&bank->slock, flags);
2721         irq_gc_lock(gc);
2722
2723         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2724         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2725
2726         switch (type) {
2727         case IRQ_TYPE_EDGE_BOTH:
2728                 bank->toggle_edge_mode |= mask;
2729                 level |= mask;
2730
2731                 /*
2732                  * Determine gpio state. If 1 next interrupt should be falling
2733                  * otherwise rising.
2734                  */
2735                 data = readl(bank->reg_base + GPIO_EXT_PORT);
2736                 if (data & mask)
2737                         polarity &= ~mask;
2738                 else
2739                         polarity |= mask;
2740                 break;
2741         case IRQ_TYPE_EDGE_RISING:
2742                 bank->toggle_edge_mode &= ~mask;
2743                 level |= mask;
2744                 polarity |= mask;
2745                 break;
2746         case IRQ_TYPE_EDGE_FALLING:
2747                 bank->toggle_edge_mode &= ~mask;
2748                 level |= mask;
2749                 polarity &= ~mask;
2750                 break;
2751         case IRQ_TYPE_LEVEL_HIGH:
2752                 bank->toggle_edge_mode &= ~mask;
2753                 level &= ~mask;
2754                 polarity |= mask;
2755                 break;
2756         case IRQ_TYPE_LEVEL_LOW:
2757                 bank->toggle_edge_mode &= ~mask;
2758                 level &= ~mask;
2759                 polarity &= ~mask;
2760                 break;
2761         default:
2762                 irq_gc_unlock(gc);
2763                 raw_spin_unlock_irqrestore(&bank->slock, flags);
2764                 return -EINVAL;
2765         }
2766
2767         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2768         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2769
2770         irq_gc_unlock(gc);
2771         raw_spin_unlock_irqrestore(&bank->slock, flags);
2772
2773         return 0;
2774 }
2775
2776 static void rockchip_irq_suspend(struct irq_data *d)
2777 {
2778         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2779         struct rockchip_pin_bank *bank = gc->private;
2780
2781         clk_enable(bank->clk);
2782         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2783         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2784         clk_disable(bank->clk);
2785 }
2786
2787 static void rockchip_irq_resume(struct irq_data *d)
2788 {
2789         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2790         struct rockchip_pin_bank *bank = gc->private;
2791
2792         clk_enable(bank->clk);
2793         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2794         clk_disable(bank->clk);
2795 }
2796
2797 static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
2798 {
2799         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2800         struct rockchip_pin_bank *bank = gc->private;
2801
2802         clk_enable(bank->clk);
2803         irq_gc_mask_clr_bit(d);
2804 }
2805
2806 void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
2807 {
2808         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2809         struct rockchip_pin_bank *bank = gc->private;
2810
2811         irq_gc_mask_set_bit(d);
2812         clk_disable(bank->clk);
2813 }
2814
2815 static void rockchip_irq_bus_lock(struct irq_data *d)
2816 {
2817         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2818         struct rockchip_pin_bank *bank = gc->private;
2819
2820         clk_enable(bank->clk);
2821         mutex_lock(&bank->irq_lock);
2822 }
2823
2824 static void rockchip_irq_bus_sync_unlock(struct irq_data *d)
2825 {
2826         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2827         struct rockchip_pin_bank *bank = gc->private;
2828
2829         while (bank->new_irqs) {
2830                 unsigned int irq = __ffs(bank->new_irqs);
2831                 int ret;
2832
2833                 ret = rockchip_set_mux(bank, irq, RK_FUNC_GPIO);
2834                 WARN_ON(ret < 0);
2835
2836                 bank->new_irqs &= ~BIT(irq);
2837         }
2838
2839         mutex_unlock(&bank->irq_lock);
2840         clk_disable(bank->clk);
2841 }
2842
2843 static int rockchip_interrupts_register(struct platform_device *pdev,
2844                                                 struct rockchip_pinctrl *info)
2845 {
2846         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2847         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2848         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2849         struct irq_chip_generic *gc;
2850         int ret;
2851         int i, j;
2852
2853         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2854                 if (!bank->valid) {
2855                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2856                                  bank->name);
2857                         continue;
2858                 }
2859
2860                 ret = clk_enable(bank->clk);
2861                 if (ret) {
2862                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2863                                 bank->name);
2864                         continue;
2865                 }
2866
2867                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2868                                                 &irq_generic_chip_ops, NULL);
2869                 if (!bank->domain) {
2870                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2871                                  bank->name);
2872                         clk_disable(bank->clk);
2873                         continue;
2874                 }
2875
2876                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2877                                          bank->name, handle_level_irq,
2878                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
2879                 if (ret) {
2880                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2881                                 bank->name);
2882                         irq_domain_remove(bank->domain);
2883                         clk_disable(bank->clk);
2884                         continue;
2885                 }
2886
2887                 /*
2888                  * Linux assumes that all interrupts start out disabled/masked.
2889                  * Our driver only uses the concept of masked and always keeps
2890                  * things enabled, so for us that's all masked and all enabled.
2891                  */
2892                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2893                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2894
2895                 gc = irq_get_domain_generic_chip(bank->domain, 0);
2896                 gc->reg_base = bank->reg_base;
2897                 gc->private = bank;
2898                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2899                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2900                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2901                 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
2902                 gc->chip_types[0].chip.irq_unmask =
2903                                                   rockchip_irq_gc_mask_clr_bit;
2904                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2905                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2906                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2907                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2908                 gc->chip_types[0].chip.irq_bus_lock = rockchip_irq_bus_lock;
2909                 gc->chip_types[0].chip.irq_bus_sync_unlock =
2910                                                 rockchip_irq_bus_sync_unlock;
2911                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2912
2913                 irq_set_chained_handler_and_data(bank->irq,
2914                                                  rockchip_irq_demux, bank);
2915
2916                 /* map the gpio irqs here, when the clock is still running */
2917                 for (j = 0 ; j < 32 ; j++)
2918                         irq_create_mapping(bank->domain, j);
2919
2920                 clk_disable(bank->clk);
2921         }
2922
2923         return 0;
2924 }
2925
2926 static int rockchip_gpiolib_register(struct platform_device *pdev,
2927                                                 struct rockchip_pinctrl *info)
2928 {
2929         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2930         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2931         struct gpio_chip *gc;
2932         int ret;
2933         int i;
2934
2935         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2936                 if (!bank->valid) {
2937                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2938                                  bank->name);
2939                         continue;
2940                 }
2941
2942                 bank->gpio_chip = rockchip_gpiolib_chip;
2943
2944                 gc = &bank->gpio_chip;
2945                 gc->base = bank->pin_base;
2946                 gc->ngpio = bank->nr_pins;
2947                 gc->dev = &pdev->dev;
2948                 gc->of_node = bank->of_node;
2949                 gc->label = bank->name;
2950
2951                 ret = gpiochip_add(gc);
2952                 if (ret) {
2953                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2954                                                         gc->label, ret);
2955                         goto fail;
2956                 }
2957         }
2958
2959         rockchip_interrupts_register(pdev, info);
2960
2961         return 0;
2962
2963 fail:
2964         for (--i, --bank; i >= 0; --i, --bank) {
2965                 if (!bank->valid)
2966                         continue;
2967                 gpiochip_remove(&bank->gpio_chip);
2968         }
2969         return ret;
2970 }
2971
2972 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2973                                                 struct rockchip_pinctrl *info)
2974 {
2975         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2976         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2977         int i;
2978
2979         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2980                 if (!bank->valid)
2981                         continue;
2982                 gpiochip_remove(&bank->gpio_chip);
2983         }
2984
2985         return 0;
2986 }
2987
2988 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2989                                   struct rockchip_pinctrl *info)
2990 {
2991         struct resource res;
2992         void __iomem *base;
2993
2994         if (of_address_to_resource(bank->of_node, 0, &res)) {
2995                 dev_err(info->dev, "cannot find IO resource for bank\n");
2996                 return -ENOENT;
2997         }
2998
2999         bank->reg_base = devm_ioremap_resource(info->dev, &res);
3000         if (IS_ERR(bank->reg_base))
3001                 return PTR_ERR(bank->reg_base);
3002
3003         /*
3004          * special case, where parts of the pull setting-registers are
3005          * part of the PMU register space
3006          */
3007         if (of_device_is_compatible(bank->of_node,
3008                                     "rockchip,rk3188-gpio-bank0")) {
3009                 struct device_node *node;
3010
3011                 node = of_parse_phandle(bank->of_node->parent,
3012                                         "rockchip,pmu", 0);
3013                 if (!node) {
3014                         if (of_address_to_resource(bank->of_node, 1, &res)) {
3015                                 dev_err(info->dev, "cannot find IO resource for bank\n");
3016                                 return -ENOENT;
3017                         }
3018
3019                         base = devm_ioremap_resource(info->dev, &res);
3020                         if (IS_ERR(base))
3021                                 return PTR_ERR(base);
3022                         rockchip_regmap_config.max_register =
3023                                                     resource_size(&res) - 4;
3024                         rockchip_regmap_config.name =
3025                                             "rockchip,rk3188-gpio-bank0-pull";
3026                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3027                                                     base,
3028                                                     &rockchip_regmap_config);
3029                 }
3030         }
3031
3032         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3033
3034         bank->clk = of_clk_get(bank->of_node, 0);
3035         if (IS_ERR(bank->clk))
3036                 return PTR_ERR(bank->clk);
3037
3038         return clk_prepare(bank->clk);
3039 }
3040
3041 static const struct of_device_id rockchip_pinctrl_dt_match[];
3042
3043 /* retrieve the soc specific data */
3044 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3045                                                 struct rockchip_pinctrl *d,
3046                                                 struct platform_device *pdev)
3047 {
3048         const struct of_device_id *match;
3049         struct device_node *node = pdev->dev.of_node;
3050         struct device_node *np;
3051         struct rockchip_pin_ctrl *ctrl;
3052         struct rockchip_pin_bank *bank;
3053         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3054
3055         match = of_match_node(rockchip_pinctrl_dt_match, node);
3056         ctrl = (struct rockchip_pin_ctrl *)match->data;
3057
3058         for_each_child_of_node(node, np) {
3059                 if (!of_find_property(np, "gpio-controller", NULL))
3060                         continue;
3061
3062                 bank = ctrl->pin_banks;
3063                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3064                         if (!strcmp(bank->name, np->name)) {
3065                                 bank->of_node = np;
3066
3067                                 if (!rockchip_get_bank_data(bank, d))
3068                                         bank->valid = true;
3069
3070                                 break;
3071                         }
3072                 }
3073         }
3074
3075         grf_offs = ctrl->grf_mux_offset;
3076         pmu_offs = ctrl->pmu_mux_offset;
3077         drv_pmu_offs = ctrl->pmu_drv_offset;
3078         drv_grf_offs = ctrl->grf_drv_offset;
3079         bank = ctrl->pin_banks;
3080         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3081                 int bank_pins = 0;
3082
3083                 raw_spin_lock_init(&bank->slock);
3084                 mutex_init(&bank->irq_lock);
3085                 bank->drvdata = d;
3086                 bank->pin_base = ctrl->nr_pins;
3087                 ctrl->nr_pins += bank->nr_pins;
3088
3089                 /* calculate iomux and drv offsets */
3090                 for (j = 0; j < 4; j++) {
3091                         struct rockchip_iomux *iom = &bank->iomux[j];
3092                         struct rockchip_drv *drv = &bank->drv[j];
3093                         int inc;
3094
3095                         if (bank_pins >= bank->nr_pins)
3096                                 break;
3097
3098                         /* preset iomux offset value, set new start value */
3099                         if (iom->offset >= 0) {
3100                                 if (iom->type & IOMUX_SOURCE_PMU)
3101                                         pmu_offs = iom->offset;
3102                                 else
3103                                         grf_offs = iom->offset;
3104                         } else { /* set current iomux offset */
3105                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3106                                                         pmu_offs : grf_offs;
3107                         }
3108
3109                         /* preset drv offset value, set new start value */
3110                         if (drv->offset >= 0) {
3111                                 if (iom->type & IOMUX_SOURCE_PMU)
3112                                         drv_pmu_offs = drv->offset;
3113                                 else
3114                                         drv_grf_offs = drv->offset;
3115                         } else { /* set current drv offset */
3116                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3117                                                 drv_pmu_offs : drv_grf_offs;
3118                         }
3119
3120                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3121                                 i, j, iom->offset, drv->offset);
3122
3123                         /*
3124                          * Increase offset according to iomux width.
3125                          * 4bit iomux'es are spread over two registers.
3126                          */
3127                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
3128                                             IOMUX_WIDTH_3BIT)) ? 8 : 4;
3129                         if (iom->type & IOMUX_SOURCE_PMU)
3130                                 pmu_offs += inc;
3131                         else
3132                                 grf_offs += inc;
3133
3134                         /*
3135                          * Increase offset according to drv width.
3136                          * 3bit drive-strenth'es are spread over two registers.
3137                          */
3138                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3139                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3140                                 inc = 8;
3141                         else
3142                                 inc = 4;
3143
3144                         if (iom->type & IOMUX_SOURCE_PMU)
3145                                 drv_pmu_offs += inc;
3146                         else
3147                                 drv_grf_offs += inc;
3148
3149                         bank_pins += 8;
3150                 }
3151
3152                 /* calculate the per-bank route_mask */
3153                 for (j = 0; j < ctrl->niomux_routes; j++) {
3154                         int pin = 0;
3155
3156                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3157                                 pin = ctrl->iomux_routes[j].pin;
3158                                 bank->route_mask |= BIT(pin);
3159                         }
3160                 }
3161         }
3162
3163         return ctrl;
3164 }
3165
3166 #define RK3288_GRF_GPIO6C_IOMUX         0x64
3167 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
3168
3169 static u32 rk3288_grf_gpio6c_iomux;
3170
3171 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3172 {
3173         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3174         int ret = pinctrl_force_sleep(info->pctl_dev);
3175
3176         if (ret)
3177                 return ret;
3178
3179         /*
3180          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3181          * the setting here, and restore it at resume.
3182          */
3183         if (info->ctrl->type == RK3288) {
3184                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3185                                   &rk3288_grf_gpio6c_iomux);
3186                 if (ret) {
3187                         pinctrl_force_default(info->pctl_dev);
3188                         return ret;
3189                 }
3190         }
3191
3192         return 0;
3193 }
3194
3195 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3196 {
3197         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3198         int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3199                                rk3288_grf_gpio6c_iomux |
3200                                GPIO6C6_SEL_WRITE_ENABLE);
3201
3202         if (ret)
3203                 return ret;
3204
3205         return pinctrl_force_default(info->pctl_dev);
3206 }
3207
3208 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3209                          rockchip_pinctrl_resume);
3210
3211 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3212 {
3213         struct rockchip_pinctrl *info;
3214         struct device *dev = &pdev->dev;
3215         struct rockchip_pin_ctrl *ctrl;
3216         struct device_node *np = pdev->dev.of_node, *node;
3217         struct resource *res;
3218         void __iomem *base;
3219         int ret;
3220
3221         if (!dev->of_node) {
3222                 dev_err(dev, "device tree node not found\n");
3223                 return -ENODEV;
3224         }
3225
3226         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
3227         if (!info)
3228                 return -ENOMEM;
3229
3230         info->dev = dev;
3231
3232         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3233         if (!ctrl) {
3234                 dev_err(dev, "driver data not available\n");
3235                 return -EINVAL;
3236         }
3237         info->ctrl = ctrl;
3238
3239         node = of_parse_phandle(np, "rockchip,grf", 0);
3240         if (node) {
3241                 info->regmap_base = syscon_node_to_regmap(node);
3242                 if (IS_ERR(info->regmap_base))
3243                         return PTR_ERR(info->regmap_base);
3244         } else {
3245                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3246                 base = devm_ioremap_resource(&pdev->dev, res);
3247                 if (IS_ERR(base))
3248                         return PTR_ERR(base);
3249
3250                 rockchip_regmap_config.max_register = resource_size(res) - 4;
3251                 rockchip_regmap_config.name = "rockchip,pinctrl";
3252                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3253                                                     &rockchip_regmap_config);
3254
3255                 /* to check for the old dt-bindings */
3256                 info->reg_size = resource_size(res);
3257
3258                 /* Honor the old binding, with pull registers as 2nd resource */
3259                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3260                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3261                         base = devm_ioremap_resource(&pdev->dev, res);
3262                         if (IS_ERR(base))
3263                                 return PTR_ERR(base);
3264
3265                         rockchip_regmap_config.max_register =
3266                                                         resource_size(res) - 4;
3267                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3268                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3269                                                     base,
3270                                                     &rockchip_regmap_config);
3271                 }
3272         }
3273
3274         /* try to find the optional reference to the pmu syscon */
3275         node = of_parse_phandle(np, "rockchip,pmu", 0);
3276         if (node) {
3277                 info->regmap_pmu = syscon_node_to_regmap(node);
3278                 if (IS_ERR(info->regmap_pmu))
3279                         return PTR_ERR(info->regmap_pmu);
3280         }
3281
3282         ret = rockchip_gpiolib_register(pdev, info);
3283         if (ret)
3284                 return ret;
3285
3286         ret = rockchip_pinctrl_register(pdev, info);
3287         if (ret) {
3288                 rockchip_gpiolib_unregister(pdev, info);
3289                 return ret;
3290         }
3291
3292         platform_set_drvdata(pdev, info);
3293
3294         return 0;
3295 }
3296
3297 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3298         PIN_BANK(0, 32, "gpio0"),
3299         PIN_BANK(1, 32, "gpio1"),
3300         PIN_BANK(2, 32, "gpio2"),
3301         PIN_BANK(3, 32, "gpio3"),
3302 };
3303
3304 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3305                 .pin_banks              = rk2928_pin_banks,
3306                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
3307                 .label                  = "RK2928-GPIO",
3308                 .type                   = RK2928,
3309                 .grf_mux_offset         = 0xa8,
3310                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3311 };
3312
3313 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3314         PIN_BANK(0, 32, "gpio0"),
3315         PIN_BANK(1, 32, "gpio1"),
3316         PIN_BANK(2, 32, "gpio2"),
3317 };
3318
3319 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3320                 .pin_banks              = rk3036_pin_banks,
3321                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
3322                 .label                  = "RK3036-GPIO",
3323                 .type                   = RK2928,
3324                 .grf_mux_offset         = 0xa8,
3325                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3326 };
3327
3328 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3329         PIN_BANK(0, 32, "gpio0"),
3330         PIN_BANK(1, 32, "gpio1"),
3331         PIN_BANK(2, 32, "gpio2"),
3332         PIN_BANK(3, 32, "gpio3"),
3333         PIN_BANK(4, 32, "gpio4"),
3334         PIN_BANK(6, 16, "gpio6"),
3335 };
3336
3337 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3338                 .pin_banks              = rk3066a_pin_banks,
3339                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
3340                 .label                  = "RK3066a-GPIO",
3341                 .type                   = RK2928,
3342                 .grf_mux_offset         = 0xa8,
3343                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3344 };
3345
3346 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3347         PIN_BANK(0, 32, "gpio0"),
3348         PIN_BANK(1, 32, "gpio1"),
3349         PIN_BANK(2, 32, "gpio2"),
3350         PIN_BANK(3, 32, "gpio3"),
3351 };
3352
3353 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3354                 .pin_banks      = rk3066b_pin_banks,
3355                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
3356                 .label          = "RK3066b-GPIO",
3357                 .type           = RK3066B,
3358                 .grf_mux_offset = 0x60,
3359 };
3360
3361 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3362         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3363         PIN_BANK(1, 32, "gpio1"),
3364         PIN_BANK(2, 32, "gpio2"),
3365         PIN_BANK(3, 32, "gpio3"),
3366 };
3367
3368 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3369                 .pin_banks              = rk3188_pin_banks,
3370                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
3371                 .label                  = "RK3188-GPIO",
3372                 .type                   = RK3188,
3373                 .grf_mux_offset         = 0x60,
3374                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
3375 };
3376
3377 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3378         PIN_BANK(0, 32, "gpio0"),
3379         PIN_BANK(1, 32, "gpio1"),
3380         PIN_BANK(2, 32, "gpio2"),
3381         PIN_BANK(3, 32, "gpio3"),
3382 };
3383
3384 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3385                 .pin_banks              = rk3228_pin_banks,
3386                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
3387                 .label                  = "RK3228-GPIO",
3388                 .type                   = RK3288,
3389                 .grf_mux_offset         = 0x0,
3390                 .iomux_routes           = rk3228_mux_route_data,
3391                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
3392                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3393                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3394 };
3395
3396 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3397         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3398                                              IOMUX_SOURCE_PMU,
3399                                              IOMUX_SOURCE_PMU,
3400                                              IOMUX_SOURCE_PMU
3401                             ),
3402         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3403                                              IOMUX_UNROUTED,
3404                                              IOMUX_UNROUTED,
3405                                              0
3406                             ),
3407         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3408         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3409         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3410                                              IOMUX_WIDTH_4BIT,
3411                                              0,
3412                                              0
3413                             ),
3414         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3415                                              0,
3416                                              0,
3417                                              IOMUX_UNROUTED
3418                             ),
3419         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3420         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3421                                              0,
3422                                              IOMUX_WIDTH_4BIT,
3423                                              IOMUX_UNROUTED
3424                             ),
3425         PIN_BANK(8, 16, "gpio8"),
3426 };
3427
3428 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3429                 .pin_banks              = rk3288_pin_banks,
3430                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3431                 .label                  = "RK3288-GPIO",
3432                 .type                   = RK3288,
3433                 .grf_mux_offset         = 0x0,
3434                 .pmu_mux_offset         = 0x84,
3435                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
3436                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
3437 };
3438
3439 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3440         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3441         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3442         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3443                              IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
3444                              IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
3445                              0),
3446         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3447                              IOMUX_WIDTH_3BIT,
3448                              IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
3449                              0,
3450                              0),
3451 };
3452
3453 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3454                 .pin_banks              = rk3328_pin_banks,
3455                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
3456                 .label                  = "RK3328-GPIO",
3457                 .type                   = RK3288,
3458                 .grf_mux_offset         = 0x0,
3459                 .iomux_routes           = rk3328_mux_route_data,
3460                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
3461                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3462                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3463                 .iomux_recalc           = rk3328_recalc_mux,
3464                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
3465 };
3466
3467 static struct rockchip_pin_bank rk3366_pin_banks[] = {
3468         PIN_BANK_IOMUX_DRV_FLAGS(0, 32, "gpio0",
3469                                  IOMUX_SOURCE_PMU,
3470                                  IOMUX_SOURCE_PMU,
3471                                  IOMUX_SOURCE_PMU,
3472                                  IOMUX_SOURCE_PMU,
3473                                  DRV_TYPE_IO_NARROW_LEVEL,
3474                                  DRV_TYPE_IO_NARROW_LEVEL,
3475                                  DRV_TYPE_IO_NARROW_LEVEL,
3476                                  DRV_TYPE_IO_NARROW_LEVEL
3477                                  ),
3478         PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
3479                                               IOMUX_SOURCE_PMU,
3480                                               IOMUX_SOURCE_PMU,
3481                                               IOMUX_SOURCE_PMU,
3482                                               IOMUX_SOURCE_PMU,
3483                                               0x30,
3484                                               0x34,
3485                                               0x38,
3486                                               0x3c,
3487                                               DRV_TYPE_IO_NARROW_LEVEL,
3488                                               DRV_TYPE_IO_NARROW_LEVEL,
3489                                               DRV_TYPE_IO_NARROW_LEVEL,
3490                                               DRV_TYPE_IO_NARROW_LEVEL
3491                                               ),
3492         PIN_BANK_DRV_FLAGS(2, 32, "gpio2",
3493                            DRV_TYPE_IO_WIDE_LEVEL,
3494                            DRV_TYPE_IO_NARROW_LEVEL,
3495                            DRV_TYPE_IO_WIDE_LEVEL,
3496                            DRV_TYPE_IO_NARROW_LEVEL
3497                            ),
3498         PIN_BANK_DRV_FLAGS(3, 32, "gpio3",
3499                            DRV_TYPE_IO_NARROW_LEVEL,
3500                            DRV_TYPE_IO_NARROW_LEVEL,
3501                            DRV_TYPE_IO_NARROW_LEVEL,
3502                            DRV_TYPE_IO_NARROW_LEVEL
3503                            ),
3504         PIN_BANK_DRV_FLAGS(4, 32, "gpio4",
3505                            DRV_TYPE_IO_NARROW_LEVEL,
3506                            DRV_TYPE_IO_NARROW_LEVEL,
3507                            DRV_TYPE_IO_NARROW_LEVEL,
3508                            DRV_TYPE_IO_NARROW_LEVEL
3509                            ),
3510         PIN_BANK_DRV_FLAGS(5, 32, "gpio5",
3511                            DRV_TYPE_IO_NARROW_LEVEL,
3512                            DRV_TYPE_IO_NARROW_LEVEL,
3513                            DRV_TYPE_IO_NARROW_LEVEL,
3514                            DRV_TYPE_IO_NARROW_LEVEL
3515                            ),
3516 };
3517
3518 static struct rockchip_pin_ctrl rk3366_pin_ctrl = {
3519                 .pin_banks              = rk3366_pin_banks,
3520                 .nr_banks               = ARRAY_SIZE(rk3366_pin_banks),
3521                 .label                  = "RK3366-GPIO",
3522                 .type                   = RK3366,
3523                 .grf_mux_offset         = 0x10,
3524                 .pmu_mux_offset         = 0x0,
3525                 .pull_calc_reg          = rk3366_calc_pull_reg_and_bit,
3526                 .drv_calc_reg           = rk3366_calc_drv_reg_and_bit,
3527                 .drv_calc_extra_reg     = rk3366_calc_drv_extra_reg_and_bit,
3528 };
3529
3530 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3531         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3532                                              IOMUX_SOURCE_PMU,
3533                                              IOMUX_SOURCE_PMU,
3534                                              IOMUX_SOURCE_PMU
3535                             ),
3536         PIN_BANK(1, 32, "gpio1"),
3537         PIN_BANK(2, 32, "gpio2"),
3538         PIN_BANK(3, 32, "gpio3"),
3539 };
3540
3541 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3542                 .pin_banks              = rk3368_pin_banks,
3543                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
3544                 .label                  = "RK3368-GPIO",
3545                 .type                   = RK3368,
3546                 .grf_mux_offset         = 0x0,
3547                 .pmu_mux_offset         = 0x0,
3548                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
3549                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
3550 };
3551
3552 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3553         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3554                                                          IOMUX_SOURCE_PMU,
3555                                                          IOMUX_SOURCE_PMU,
3556                                                          IOMUX_SOURCE_PMU,
3557                                                          IOMUX_SOURCE_PMU,
3558                                                          DRV_TYPE_IO_1V8_ONLY,
3559                                                          DRV_TYPE_IO_1V8_ONLY,
3560                                                          DRV_TYPE_IO_DEFAULT,
3561                                                          DRV_TYPE_IO_DEFAULT,
3562                                                          0x0,
3563                                                          0x8,
3564                                                          -1,
3565                                                          -1,
3566                                                          PULL_TYPE_IO_1V8_ONLY,
3567                                                          PULL_TYPE_IO_1V8_ONLY,
3568                                                          PULL_TYPE_IO_DEFAULT,
3569                                                          PULL_TYPE_IO_DEFAULT),
3570         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3571                                               IOMUX_SOURCE_PMU,
3572                                               IOMUX_SOURCE_PMU,
3573                                               IOMUX_SOURCE_PMU,
3574                                               DRV_TYPE_IO_1V8_OR_3V0,
3575                                               DRV_TYPE_IO_1V8_OR_3V0,
3576                                               DRV_TYPE_IO_1V8_OR_3V0,
3577                                               DRV_TYPE_IO_1V8_OR_3V0,
3578                                               0x20,
3579                                               0x28,
3580                                               0x30,
3581                                               0x38
3582                                               ),
3583         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3584                                       DRV_TYPE_IO_1V8_OR_3V0,
3585                                       DRV_TYPE_IO_1V8_ONLY,
3586                                       DRV_TYPE_IO_1V8_ONLY,
3587                                       PULL_TYPE_IO_DEFAULT,
3588                                       PULL_TYPE_IO_DEFAULT,
3589                                       PULL_TYPE_IO_1V8_ONLY,
3590                                       PULL_TYPE_IO_1V8_ONLY
3591                                       ),
3592         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3593                            DRV_TYPE_IO_3V3_ONLY,
3594                            DRV_TYPE_IO_3V3_ONLY,
3595                            DRV_TYPE_IO_1V8_OR_3V0
3596                            ),
3597         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3598                            DRV_TYPE_IO_1V8_3V0_AUTO,
3599                            DRV_TYPE_IO_1V8_OR_3V0,
3600                            DRV_TYPE_IO_1V8_OR_3V0
3601                            ),
3602 };
3603
3604 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3605                 .pin_banks              = rk3399_pin_banks,
3606                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
3607                 .label                  = "RK3399-GPIO",
3608                 .type                   = RK3399,
3609                 .grf_mux_offset         = 0xe000,
3610                 .pmu_mux_offset         = 0x0,
3611                 .grf_drv_offset         = 0xe100,
3612                 .pmu_drv_offset         = 0x80,
3613                 .iomux_routes           = rk3399_mux_route_data,
3614                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
3615                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
3616                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
3617 };
3618
3619 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3620         { .compatible = "rockchip,rk2928-pinctrl",
3621                 .data = (void *)&rk2928_pin_ctrl },
3622         { .compatible = "rockchip,rk3036-pinctrl",
3623                 .data = (void *)&rk3036_pin_ctrl },
3624         { .compatible = "rockchip,rk3066a-pinctrl",
3625                 .data = (void *)&rk3066a_pin_ctrl },
3626         { .compatible = "rockchip,rk3066b-pinctrl",
3627                 .data = (void *)&rk3066b_pin_ctrl },
3628         { .compatible = "rockchip,rk3188-pinctrl",
3629                 .data = (void *)&rk3188_pin_ctrl },
3630         { .compatible = "rockchip,rk3228-pinctrl",
3631                 .data = (void *)&rk3228_pin_ctrl },
3632         { .compatible = "rockchip,rk3288-pinctrl",
3633                 .data = (void *)&rk3288_pin_ctrl },
3634         { .compatible = "rockchip,rk3328-pinctrl",
3635                 .data = (void *)&rk3328_pin_ctrl },
3636         { .compatible = "rockchip,rk3366-pinctrl",
3637                 .data = (void *)&rk3366_pin_ctrl },
3638         { .compatible = "rockchip,rk3368-pinctrl",
3639                 .data = (void *)&rk3368_pin_ctrl },
3640         { .compatible = "rockchip,rk3399-pinctrl",
3641                 .data = (void *)&rk3399_pin_ctrl },
3642         {},
3643 };
3644 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
3645
3646 static struct platform_driver rockchip_pinctrl_driver = {
3647         .probe          = rockchip_pinctrl_probe,
3648         .driver = {
3649                 .name   = "rockchip-pinctrl",
3650                 .pm = &rockchip_pinctrl_dev_pm_ops,
3651                 .of_match_table = rockchip_pinctrl_dt_match,
3652         },
3653 };
3654
3655 static int __init rockchip_pinctrl_drv_register(void)
3656 {
3657         return platform_driver_register(&rockchip_pinctrl_driver);
3658 }
3659 postcore_initcall(rockchip_pinctrl_drv_register);
3660
3661 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
3662 MODULE_DESCRIPTION("Rockchip pinctrl driver");
3663 MODULE_LICENSE("GPL v2");