2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <dt-bindings/pinctrl/rockchip.h>
45 /* GPIO control registers */
46 #define GPIO_SWPORT_DR 0x00
47 #define GPIO_SWPORT_DDR 0x04
48 #define GPIO_INTEN 0x30
49 #define GPIO_INTMASK 0x34
50 #define GPIO_INTTYPE_LEVEL 0x38
51 #define GPIO_INT_POLARITY 0x3c
52 #define GPIO_INT_STATUS 0x40
53 #define GPIO_INT_RAWSTATUS 0x44
54 #define GPIO_DEBOUNCE 0x48
55 #define GPIO_PORTS_EOI 0x4c
56 #define GPIO_EXT_PORT 0x50
57 #define GPIO_LS_SYNC 0x60
60 * @reg_base: register base of the gpio bank
61 * @clk: clock of the gpio bank
62 * @irq: interrupt of the gpio bank
63 * @pin_base: first pin number
64 * @nr_pins: number of pins in this bank
65 * @name: name of the bank
66 * @bank_num: number of the bank, to account for holes
67 * @valid: are all necessary informations present
68 * @of_node: dt node of this bank
69 * @drvdata: common pinctrl basedata
70 * @domain: irqdomain of the gpio bank
71 * @gpio_chip: gpiolib chip
73 * @slock: spinlock for the gpio bank
75 struct rockchip_pin_bank {
76 void __iomem *reg_base;
84 struct device_node *of_node;
85 struct rockchip_pinctrl *drvdata;
86 struct irq_domain *domain;
87 struct gpio_chip gpio_chip;
88 struct pinctrl_gpio_range grange;
93 #define PIN_BANK(id, pins, label) \
101 * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but
102 * instead decide this automatically based on the pad-type.
104 struct rockchip_pin_ctrl {
105 struct rockchip_pin_bank *pin_banks;
112 int pull_bank_stride;
115 struct rockchip_pin_config {
117 unsigned long *configs;
118 unsigned int nconfigs;
122 * struct rockchip_pin_group: represent group of pins of a pinmux function.
123 * @name: name of the pin group, used to lookup the group.
124 * @pins: the pins included in this group.
125 * @npins: number of pins included in this group.
126 * @func: the mux function number to be programmed when selected.
127 * @configs: the config values to be set for each pin
128 * @nconfigs: number of configs for each pin
130 struct rockchip_pin_group {
134 struct rockchip_pin_config *data;
138 * struct rockchip_pmx_func: represent a pin function.
139 * @name: name of the pin function, used to lookup the function.
140 * @groups: one or more names of pin groups that provide this function.
141 * @num_groups: number of groups included in @groups.
143 struct rockchip_pmx_func {
149 struct rockchip_pinctrl {
150 void __iomem *reg_base;
152 struct rockchip_pin_ctrl *ctrl;
153 struct pinctrl_desc pctl;
154 struct pinctrl_dev *pctl_dev;
155 struct rockchip_pin_group *groups;
156 unsigned int ngroups;
157 struct rockchip_pmx_func *functions;
158 unsigned int nfunctions;
161 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
163 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
166 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
167 const struct rockchip_pinctrl *info,
172 for (i = 0; i < info->ngroups; i++) {
173 if (!strcmp(info->groups[i].name, name))
174 return &info->groups[i];
181 * given a pin number that is local to a pin controller, find out the pin bank
182 * and the register base of the pin bank.
184 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
187 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
189 while ((pin >= b->pin_base) &&
190 ((b->pin_base + b->nr_pins - 1) < pin))
196 static struct rockchip_pin_bank *bank_num_to_bank(
197 struct rockchip_pinctrl *info,
200 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
203 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
204 if (b->bank_num == num)
208 return ERR_PTR(-EINVAL);
212 * Pinctrl_ops handling
215 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
217 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
219 return info->ngroups;
222 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
225 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
227 return info->groups[selector].name;
230 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
231 unsigned selector, const unsigned **pins,
234 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
236 if (selector >= info->ngroups)
239 *pins = info->groups[selector].pins;
240 *npins = info->groups[selector].npins;
245 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
246 struct device_node *np,
247 struct pinctrl_map **map, unsigned *num_maps)
249 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
250 const struct rockchip_pin_group *grp;
251 struct pinctrl_map *new_map;
252 struct device_node *parent;
257 * first find the group of this node and check if we need to create
258 * config maps for pins
260 grp = pinctrl_name_to_group(info, np->name);
262 dev_err(info->dev, "unable to find group for node %s\n",
267 map_num += grp->npins;
268 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
277 parent = of_get_parent(np);
279 devm_kfree(pctldev->dev, new_map);
282 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
283 new_map[0].data.mux.function = parent->name;
284 new_map[0].data.mux.group = np->name;
287 /* create config map */
289 for (i = 0; i < grp->npins; i++) {
290 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
291 new_map[i].data.configs.group_or_pin =
292 pin_get_name(pctldev, grp->pins[i]);
293 new_map[i].data.configs.configs = grp->data[i].configs;
294 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
297 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
298 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
303 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
304 struct pinctrl_map *map, unsigned num_maps)
308 static const struct pinctrl_ops rockchip_pctrl_ops = {
309 .get_groups_count = rockchip_get_groups_count,
310 .get_group_name = rockchip_get_group_name,
311 .get_group_pins = rockchip_get_group_pins,
312 .dt_node_to_map = rockchip_dt_node_to_map,
313 .dt_free_map = rockchip_dt_free_map,
321 * Set a new mux function for a pin.
323 * The register is divided into the upper and lower 16 bit. When changing
324 * a value, the previous register value is not read and changed. Instead
325 * it seems the changed bits are marked in the upper 16 bit, while the
326 * changed value gets set in the same offset in the lower 16 bit.
327 * All pin settings seem to be 2 bit wide in both the upper and lower
329 * @bank: pin bank to change
330 * @pin: pin to change
331 * @mux: new mux function to set
333 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
335 struct rockchip_pinctrl *info = bank->drvdata;
336 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
341 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
342 bank->bank_num, pin, mux);
344 /* get basic quadrupel of mux registers and the correct reg inside */
345 reg += bank->bank_num * 0x10;
346 reg += (pin / 8) * 4;
349 spin_lock_irqsave(&bank->slock, flags);
351 data = (3 << (bit + 16));
352 data |= (mux & 3) << bit;
355 spin_unlock_irqrestore(&bank->slock, flags);
358 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
360 struct rockchip_pinctrl *info = bank->drvdata;
361 struct rockchip_pin_ctrl *ctrl = info->ctrl;
365 /* rk3066b does support any pulls */
366 if (!ctrl->pull_offset)
367 return PIN_CONFIG_BIAS_DISABLE;
369 reg = info->reg_base + ctrl->pull_offset;
371 if (ctrl->pull_auto) {
372 reg += bank->bank_num * ctrl->pull_bank_stride;
373 reg += (pin_num / 16) * 4;
376 return !(readl_relaxed(reg) & BIT(bit))
377 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
378 : PIN_CONFIG_BIAS_DISABLE;
380 dev_err(info->dev, "pull support for rk31xx not implemented\n");
385 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
386 int pin_num, int pull)
388 struct rockchip_pinctrl *info = bank->drvdata;
389 struct rockchip_pin_ctrl *ctrl = info->ctrl;
395 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
396 bank->bank_num, pin_num, pull);
398 /* rk3066b does support any pulls */
399 if (!ctrl->pull_offset)
400 return pull ? -EINVAL : 0;
402 reg = info->reg_base + ctrl->pull_offset;
404 if (ctrl->pull_auto) {
405 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
406 pull != PIN_CONFIG_BIAS_DISABLE) {
407 dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
411 reg += bank->bank_num * ctrl->pull_bank_stride;
412 reg += (pin_num / 16) * 4;
415 spin_lock_irqsave(&bank->slock, flags);
417 data = BIT(bit + 16);
418 if (pull == PIN_CONFIG_BIAS_DISABLE)
422 spin_unlock_irqrestore(&bank->slock, flags);
424 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) {
425 dev_err(info->dev, "pull direction (up/down) needs to be specified\n");
429 dev_err(info->dev, "pull support for rk31xx not implemented\n");
437 * Pinmux_ops handling
440 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
442 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
444 return info->nfunctions;
447 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
450 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
452 return info->functions[selector].name;
455 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
456 unsigned selector, const char * const **groups,
457 unsigned * const num_groups)
459 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
461 *groups = info->functions[selector].groups;
462 *num_groups = info->functions[selector].ngroups;
467 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
470 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
471 const unsigned int *pins = info->groups[group].pins;
472 const struct rockchip_pin_config *data = info->groups[group].data;
473 struct rockchip_pin_bank *bank;
476 dev_dbg(info->dev, "enable function %s group %s\n",
477 info->functions[selector].name, info->groups[group].name);
480 * for each pin in the pin group selected, program the correspoding pin
481 * pin function number in the config register.
483 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
484 bank = pin_to_bank(info, pins[cnt]);
485 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
492 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
493 unsigned selector, unsigned group)
495 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
496 const unsigned int *pins = info->groups[group].pins;
497 struct rockchip_pin_bank *bank;
500 dev_dbg(info->dev, "disable function %s group %s\n",
501 info->functions[selector].name, info->groups[group].name);
503 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
504 bank = pin_to_bank(info, pins[cnt]);
505 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
510 * The calls to gpio_direction_output() and gpio_direction_input()
511 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
512 * function called from the gpiolib interface).
514 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
515 struct pinctrl_gpio_range *range,
516 unsigned offset, bool input)
518 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
519 struct rockchip_pin_bank *bank;
520 struct gpio_chip *chip;
525 bank = gc_to_pin_bank(chip);
526 pin = offset - chip->base;
528 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
529 offset, range->name, pin, input ? "input" : "output");
531 rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
533 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
534 /* set bit to 1 for output, 0 for input */
539 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
544 static const struct pinmux_ops rockchip_pmx_ops = {
545 .get_functions_count = rockchip_pmx_get_funcs_count,
546 .get_function_name = rockchip_pmx_get_func_name,
547 .get_function_groups = rockchip_pmx_get_groups,
548 .enable = rockchip_pmx_enable,
549 .disable = rockchip_pmx_disable,
550 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
554 * Pinconf_ops handling
557 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
558 enum pin_config_param pull)
560 /* rk3066b does support any pulls */
561 if (!ctrl->pull_offset)
562 return pull ? false : true;
564 if (ctrl->pull_auto) {
565 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
566 pull != PIN_CONFIG_BIAS_DISABLE)
569 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
576 /* set the pin config settings for a specified pin */
577 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
578 unsigned long config)
580 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
581 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
582 enum pin_config_param param = pinconf_to_config_param(config);
583 u16 arg = pinconf_to_config_argument(config);
586 case PIN_CONFIG_BIAS_DISABLE:
587 return rockchip_set_pull(bank, pin - bank->pin_base, param);
589 case PIN_CONFIG_BIAS_PULL_UP:
590 case PIN_CONFIG_BIAS_PULL_DOWN:
591 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
592 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
598 return rockchip_set_pull(bank, pin - bank->pin_base, param);
608 /* get the pin config settings for a specified pin */
609 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
610 unsigned long *config)
612 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
613 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
614 enum pin_config_param param = pinconf_to_config_param(*config);
617 case PIN_CONFIG_BIAS_DISABLE:
618 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
623 case PIN_CONFIG_BIAS_PULL_UP:
624 case PIN_CONFIG_BIAS_PULL_DOWN:
625 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
626 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
629 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
642 static const struct pinconf_ops rockchip_pinconf_ops = {
643 .pin_config_get = rockchip_pinconf_get,
644 .pin_config_set = rockchip_pinconf_set,
647 static const char *gpio_compat = "rockchip,gpio-bank";
649 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
650 struct device_node *np)
652 struct device_node *child;
654 for_each_child_of_node(np, child) {
655 if (of_device_is_compatible(child, gpio_compat))
659 info->ngroups += of_get_child_count(child);
663 static int rockchip_pinctrl_parse_groups(struct device_node *np,
664 struct rockchip_pin_group *grp,
665 struct rockchip_pinctrl *info,
668 struct rockchip_pin_bank *bank;
675 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
677 /* Initialise group */
678 grp->name = np->name;
681 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
682 * do sanity check and calculate pins number
684 list = of_get_property(np, "rockchip,pins", &size);
685 /* we do not check return since it's safe node passed down */
686 size /= sizeof(*list);
687 if (!size || size % 4) {
688 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
692 grp->npins = size / 4;
694 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
696 grp->data = devm_kzalloc(info->dev, grp->npins *
697 sizeof(struct rockchip_pin_config),
699 if (!grp->pins || !grp->data)
702 for (i = 0, j = 0; i < size; i += 4, j++) {
703 const __be32 *phandle;
704 struct device_node *np_config;
706 num = be32_to_cpu(*list++);
707 bank = bank_num_to_bank(info, num);
709 return PTR_ERR(bank);
711 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
712 grp->data[j].func = be32_to_cpu(*list++);
718 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
719 ret = pinconf_generic_parse_dt_config(np_config,
720 &grp->data[j].configs, &grp->data[j].nconfigs);
728 static int rockchip_pinctrl_parse_functions(struct device_node *np,
729 struct rockchip_pinctrl *info,
732 struct device_node *child;
733 struct rockchip_pmx_func *func;
734 struct rockchip_pin_group *grp;
736 static u32 grp_index;
739 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
741 func = &info->functions[index];
743 /* Initialise function */
744 func->name = np->name;
745 func->ngroups = of_get_child_count(np);
746 if (func->ngroups <= 0)
749 func->groups = devm_kzalloc(info->dev,
750 func->ngroups * sizeof(char *), GFP_KERNEL);
754 for_each_child_of_node(np, child) {
755 func->groups[i] = child->name;
756 grp = &info->groups[grp_index++];
757 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
765 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
766 struct rockchip_pinctrl *info)
768 struct device *dev = &pdev->dev;
769 struct device_node *np = dev->of_node;
770 struct device_node *child;
774 rockchip_pinctrl_child_count(info, np);
776 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
777 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
779 info->functions = devm_kzalloc(dev, info->nfunctions *
780 sizeof(struct rockchip_pmx_func),
782 if (!info->functions) {
783 dev_err(dev, "failed to allocate memory for function list\n");
787 info->groups = devm_kzalloc(dev, info->ngroups *
788 sizeof(struct rockchip_pin_group),
791 dev_err(dev, "failed allocate memory for ping group list\n");
797 for_each_child_of_node(np, child) {
798 if (of_device_is_compatible(child, gpio_compat))
800 ret = rockchip_pinctrl_parse_functions(child, info, i++);
802 dev_err(&pdev->dev, "failed to parse function\n");
810 static int rockchip_pinctrl_register(struct platform_device *pdev,
811 struct rockchip_pinctrl *info)
813 struct pinctrl_desc *ctrldesc = &info->pctl;
814 struct pinctrl_pin_desc *pindesc, *pdesc;
815 struct rockchip_pin_bank *pin_bank;
819 ctrldesc->name = "rockchip-pinctrl";
820 ctrldesc->owner = THIS_MODULE;
821 ctrldesc->pctlops = &rockchip_pctrl_ops;
822 ctrldesc->pmxops = &rockchip_pmx_ops;
823 ctrldesc->confops = &rockchip_pinconf_ops;
825 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
826 info->ctrl->nr_pins, GFP_KERNEL);
828 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
831 ctrldesc->pins = pindesc;
832 ctrldesc->npins = info->ctrl->nr_pins;
835 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
836 pin_bank = &info->ctrl->pin_banks[bank];
837 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
839 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
840 pin_bank->name, pin);
845 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
846 if (!info->pctl_dev) {
847 dev_err(&pdev->dev, "could not register pinctrl driver\n");
851 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
852 pin_bank = &info->ctrl->pin_banks[bank];
853 pin_bank->grange.name = pin_bank->name;
854 pin_bank->grange.id = bank;
855 pin_bank->grange.pin_base = pin_bank->pin_base;
856 pin_bank->grange.base = pin_bank->gpio_chip.base;
857 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
858 pin_bank->grange.gc = &pin_bank->gpio_chip;
859 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
862 ret = rockchip_pinctrl_parse_dt(pdev, info);
864 pinctrl_unregister(info->pctl_dev);
875 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
877 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
878 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
882 spin_lock_irqsave(&bank->slock, flags);
885 data &= ~BIT(offset);
890 spin_unlock_irqrestore(&bank->slock, flags);
894 * Returns the level of the pin for input direction and setting of the DR
895 * register for output gpios.
897 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
899 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
902 data = readl(bank->reg_base + GPIO_EXT_PORT);
909 * gpiolib gpio_direction_input callback function. The setting of the pin
910 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
913 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
915 return pinctrl_gpio_direction_input(gc->base + offset);
919 * gpiolib gpio_direction_output callback function. The setting of the pin
920 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
923 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
924 unsigned offset, int value)
926 rockchip_gpio_set(gc, offset, value);
927 return pinctrl_gpio_direction_output(gc->base + offset);
931 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
932 * and a virtual IRQ, if not already present.
934 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
936 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
942 virq = irq_create_mapping(bank->domain, offset);
944 return (virq) ? : -ENXIO;
947 static const struct gpio_chip rockchip_gpiolib_chip = {
948 .set = rockchip_gpio_set,
949 .get = rockchip_gpio_get,
950 .direction_input = rockchip_gpio_direction_input,
951 .direction_output = rockchip_gpio_direction_output,
952 .to_irq = rockchip_gpio_to_irq,
953 .owner = THIS_MODULE,
960 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
962 struct irq_chip *chip = irq_get_chip(irq);
963 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
966 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
968 chained_irq_enter(chip, desc);
970 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
977 virq = irq_linear_revmap(bank->domain, irq);
980 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
984 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
986 generic_handle_irq(virq);
989 chained_irq_exit(chip, desc);
992 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
994 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
995 struct rockchip_pin_bank *bank = gc->private;
996 u32 mask = BIT(d->hwirq);
1001 if (type & IRQ_TYPE_EDGE_BOTH)
1002 __irq_set_handler_locked(d->irq, handle_edge_irq);
1004 __irq_set_handler_locked(d->irq, handle_level_irq);
1008 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1009 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1012 case IRQ_TYPE_EDGE_RISING:
1016 case IRQ_TYPE_EDGE_FALLING:
1020 case IRQ_TYPE_LEVEL_HIGH:
1024 case IRQ_TYPE_LEVEL_LOW:
1033 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1034 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1038 /* make sure the pin is configured as gpio input */
1039 rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1040 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1042 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1047 static int rockchip_interrupts_register(struct platform_device *pdev,
1048 struct rockchip_pinctrl *info)
1050 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1051 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1052 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1053 struct irq_chip_generic *gc;
1057 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1059 dev_warn(&pdev->dev, "bank %s is not valid\n",
1064 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1065 &irq_generic_chip_ops, NULL);
1066 if (!bank->domain) {
1067 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1072 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1073 "rockchip_gpio_irq", handle_level_irq,
1074 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1076 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1078 irq_domain_remove(bank->domain);
1082 gc = irq_get_domain_generic_chip(bank->domain, 0);
1083 gc->reg_base = bank->reg_base;
1085 gc->chip_types[0].regs.mask = GPIO_INTEN;
1086 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1087 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1088 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1089 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1090 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1091 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1093 irq_set_handler_data(bank->irq, bank);
1094 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1100 static int rockchip_gpiolib_register(struct platform_device *pdev,
1101 struct rockchip_pinctrl *info)
1103 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1104 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1105 struct gpio_chip *gc;
1109 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1111 dev_warn(&pdev->dev, "bank %s is not valid\n",
1116 bank->gpio_chip = rockchip_gpiolib_chip;
1118 gc = &bank->gpio_chip;
1119 gc->base = bank->pin_base;
1120 gc->ngpio = bank->nr_pins;
1121 gc->dev = &pdev->dev;
1122 gc->of_node = bank->of_node;
1123 gc->label = bank->name;
1125 ret = gpiochip_add(gc);
1127 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1133 rockchip_interrupts_register(pdev, info);
1138 for (--i, --bank; i >= 0; --i, --bank) {
1142 if (gpiochip_remove(&bank->gpio_chip))
1143 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1144 bank->gpio_chip.label);
1149 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1150 struct rockchip_pinctrl *info)
1152 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1153 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1157 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1161 ret = gpiochip_remove(&bank->gpio_chip);
1165 dev_err(&pdev->dev, "gpio chip remove failed\n");
1170 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1173 struct resource res;
1175 if (of_address_to_resource(bank->of_node, 0, &res)) {
1176 dev_err(dev, "cannot find IO resource for bank\n");
1180 bank->reg_base = devm_ioremap_resource(dev, &res);
1181 if (IS_ERR(bank->reg_base))
1182 return PTR_ERR(bank->reg_base);
1184 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1186 bank->clk = of_clk_get(bank->of_node, 0);
1187 if (IS_ERR(bank->clk))
1188 return PTR_ERR(bank->clk);
1190 return clk_prepare_enable(bank->clk);
1193 static const struct of_device_id rockchip_pinctrl_dt_match[];
1195 /* retrieve the soc specific data */
1196 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1197 struct rockchip_pinctrl *d,
1198 struct platform_device *pdev)
1200 const struct of_device_id *match;
1201 struct device_node *node = pdev->dev.of_node;
1202 struct device_node *np;
1203 struct rockchip_pin_ctrl *ctrl;
1204 struct rockchip_pin_bank *bank;
1207 match = of_match_node(rockchip_pinctrl_dt_match, node);
1208 ctrl = (struct rockchip_pin_ctrl *)match->data;
1210 for_each_child_of_node(node, np) {
1211 if (!of_find_property(np, "gpio-controller", NULL))
1214 bank = ctrl->pin_banks;
1215 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1216 if (!strcmp(bank->name, np->name)) {
1219 if (!rockchip_get_bank_data(bank, &pdev->dev))
1227 bank = ctrl->pin_banks;
1228 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1229 spin_lock_init(&bank->slock);
1231 bank->pin_base = ctrl->nr_pins;
1232 ctrl->nr_pins += bank->nr_pins;
1238 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1240 struct rockchip_pinctrl *info;
1241 struct device *dev = &pdev->dev;
1242 struct rockchip_pin_ctrl *ctrl;
1243 struct resource *res;
1246 if (!dev->of_node) {
1247 dev_err(dev, "device tree node not found\n");
1251 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1255 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1257 dev_err(dev, "driver data not available\n");
1263 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1264 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1265 if (IS_ERR(info->reg_base))
1266 return PTR_ERR(info->reg_base);
1268 ret = rockchip_gpiolib_register(pdev, info);
1272 ret = rockchip_pinctrl_register(pdev, info);
1274 rockchip_gpiolib_unregister(pdev, info);
1278 platform_set_drvdata(pdev, info);
1283 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1284 PIN_BANK(0, 32, "gpio0"),
1285 PIN_BANK(1, 32, "gpio1"),
1286 PIN_BANK(2, 32, "gpio2"),
1287 PIN_BANK(3, 32, "gpio3"),
1290 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1291 .pin_banks = rk2928_pin_banks,
1292 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1293 .label = "RK2928-GPIO",
1295 .pull_offset = 0x118,
1297 .pull_bank_stride = 8,
1300 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1301 PIN_BANK(0, 32, "gpio0"),
1302 PIN_BANK(1, 32, "gpio1"),
1303 PIN_BANK(2, 32, "gpio2"),
1304 PIN_BANK(3, 32, "gpio3"),
1305 PIN_BANK(4, 32, "gpio4"),
1306 PIN_BANK(6, 16, "gpio6"),
1309 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1310 .pin_banks = rk3066a_pin_banks,
1311 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1312 .label = "RK3066a-GPIO",
1314 .pull_offset = 0x118,
1316 .pull_bank_stride = 8,
1319 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1320 PIN_BANK(0, 32, "gpio0"),
1321 PIN_BANK(1, 32, "gpio1"),
1322 PIN_BANK(2, 32, "gpio2"),
1323 PIN_BANK(3, 32, "gpio3"),
1326 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1327 .pin_banks = rk3066b_pin_banks,
1328 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1329 .label = "RK3066b-GPIO",
1331 .pull_offset = -EINVAL,
1334 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1335 PIN_BANK(0, 32, "gpio0"),
1336 PIN_BANK(1, 32, "gpio1"),
1337 PIN_BANK(2, 32, "gpio2"),
1338 PIN_BANK(3, 32, "gpio3"),
1341 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1342 .pin_banks = rk3188_pin_banks,
1343 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1344 .label = "RK3188-GPIO",
1346 .pull_offset = 0x164,
1347 .pull_bank_stride = 16,
1350 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1351 { .compatible = "rockchip,rk2928-pinctrl",
1352 .data = (void *)&rk2928_pin_ctrl },
1353 { .compatible = "rockchip,rk3066a-pinctrl",
1354 .data = (void *)&rk3066a_pin_ctrl },
1355 { .compatible = "rockchip,rk3066b-pinctrl",
1356 .data = (void *)&rk3066b_pin_ctrl },
1357 { .compatible = "rockchip,rk3188-pinctrl",
1358 .data = (void *)&rk3188_pin_ctrl },
1361 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1363 static struct platform_driver rockchip_pinctrl_driver = {
1364 .probe = rockchip_pinctrl_probe,
1366 .name = "rockchip-pinctrl",
1367 .owner = THIS_MODULE,
1368 .of_match_table = of_match_ptr(rockchip_pinctrl_dt_match),
1372 static int __init rockchip_pinctrl_drv_register(void)
1374 return platform_driver_register(&rockchip_pinctrl_driver);
1376 postcore_initcall(rockchip_pinctrl_drv_register);
1378 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1379 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1380 MODULE_LICENSE("GPL v2");