drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         RK2928,
  63         RK3066B,
  64         RK3188,
  65         RK3288,
  66         RK3368,
  67         RK3399,
  68 };
  69
  70 /**
  71  * Encode variants of iomux registers into a type variable
  72  */
  73 #define IOMUX_GPIO_ONLY         BIT(0)
  74 #define IOMUX_WIDTH_4BIT        BIT(1)
  75 #define IOMUX_SOURCE_PMU        BIT(2)
  76 #define IOMUX_UNROUTED          BIT(3)
  77
  78 /**
  79  * @type: iomux variant using IOMUX_* constants
  80  * @offset: if initialized to -1 it will be autocalculated, by specifying
  81  *          an initial offset value the relevant source offset can be reset
  82  *          to a new value for autocalculating the following iomux registers.
  83  */
  84 struct rockchip_iomux {
  85         int                             type;
  86         int                             offset;
  87 };
  88
  89 /**
  90  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  91  */
  92 enum rockchip_pin_drv_type {
  93         DRV_TYPE_IO_DEFAULT = 0,
  94         DRV_TYPE_IO_1V8_OR_3V0,
  95         DRV_TYPE_IO_1V8_ONLY,
  96         DRV_TYPE_IO_1V8_3V0_AUTO,
  97         DRV_TYPE_IO_3V3_ONLY,
  98         DRV_TYPE_MAX
  99 };
 100
 101 /**
 102  * @drv_type: drive strength variant using rockchip_perpin_drv_type
 103  * @offset: if initialized to -1 it will be autocalculated, by specifying
 104  *          an initial offset value the relevant source offset can be reset
 105  *          to a new value for autocalculating the following drive strength
 106  *          registers. if used chips own cal_drv func instead to calculate
 107  *          registers offset, the variant could be ignored.
 108  */
 109 struct rockchip_drv {
 110         enum rockchip_pin_drv_type      drv_type;
 111         int                             offset;
 112 };
 113
 114 /**
 115  * @reg_base: register base of the gpio bank
 116  * @reg_pull: optional separate register for additional pull settings
 117  * @clk: clock of the gpio bank
 118  * @irq: interrupt of the gpio bank
 119  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 120  * @pin_base: first pin number
 121  * @nr_pins: number of pins in this bank
 122  * @name: name of the bank
 123  * @bank_num: number of the bank, to account for holes
 124  * @iomux: array describing the 4 iomux sources of the bank
 125  * @drv: array describing the 4 drive strength sources of the bank
 126  * @valid: are all necessary informations present
 127  * @of_node: dt node of this bank
 128  * @drvdata: common pinctrl basedata
 129  * @domain: irqdomain of the gpio bank
 130  * @gpio_chip: gpiolib chip
 131  * @grange: gpio range
 132  * @slock: spinlock for the gpio bank
 133  */
 134 struct rockchip_pin_bank {
 135         void __iomem                    *reg_base;
 136         struct regmap                   *regmap_pull;
 137         struct clk                      *clk;
 138         int                             irq;
 139         u32                             saved_masks;
 140         u32                             pin_base;
 141         u8                              nr_pins;
 142         char                            *name;
 143         u8                              bank_num;
 144         struct rockchip_iomux           iomux[4];
 145         struct rockchip_drv             drv[4];
 146         bool                            valid;
 147         struct device_node              *of_node;
 148         struct rockchip_pinctrl         *drvdata;
 149         struct irq_domain               *domain;
 150         struct gpio_chip                gpio_chip;
 151         struct pinctrl_gpio_range       grange;
 152         spinlock_t                      slock;
 153         u32                             toggle_edge_mode;
 154 };
 155
 156 #define PIN_BANK(id, pins, label)                       \
 157         {                                               \
 158                 .bank_num       = id,                   \
 159                 .nr_pins        = pins,                 \
 160                 .name           = label,                \
 161                 .iomux          = {                     \
 162                         { .offset = -1 },               \
 163                         { .offset = -1 },               \
 164                         { .offset = -1 },               \
 165                         { .offset = -1 },               \
 166                 },                                      \
 167         }
 168
 169 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 170         {                                                               \
 171                 .bank_num       = id,                                   \
 172                 .nr_pins        = pins,                                 \
 173                 .name           = label,                                \
 174                 .iomux          = {                                     \
 175                         { .type = iom0, .offset = -1 },                 \
 176                         { .type = iom1, .offset = -1 },                 \
 177                         { .type = iom2, .offset = -1 },                 \
 178                         { .type = iom3, .offset = -1 },                 \
 179                 },                                                      \
 180         }
 181
 182 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 183         {                                                               \
 184                 .bank_num       = id,                                   \
 185                 .nr_pins        = pins,                                 \
 186                 .name           = label,                                \
 187                 .iomux          = {                                     \
 188                         { .offset = -1 },                               \
 189                         { .offset = -1 },                               \
 190                         { .offset = -1 },                               \
 191                         { .offset = -1 },                               \
 192                 },                                                      \
 193                 .drv            = {                                     \
 194                         { .drv_type = type0, .offset = -1 },            \
 195                         { .drv_type = type1, .offset = -1 },            \
 196                         { .drv_type = type2, .offset = -1 },            \
 197                         { .drv_type = type3, .offset = -1 },            \
 198                 },                                                      \
 199         }
 200
 201 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 202                                         iom2, iom3, drv0, drv1, drv2,   \
 203                                         drv3, offset0, offset1,         \
 204                                         offset2, offset3)               \
 205         {                                                               \
 206                 .bank_num       = id,                                   \
 207                 .nr_pins        = pins,                                 \
 208                 .name           = label,                                \
 209                 .iomux          = {                                     \
 210                         { .type = iom0, .offset = -1 },                 \
 211                         { .type = iom1, .offset = -1 },                 \
 212                         { .type = iom2, .offset = -1 },                 \
 213                         { .type = iom3, .offset = -1 },                 \
 214                 },                                                      \
 215                 .drv            = {                                     \
 216                         { .drv_type = drv0, .offset = offset0 },        \
 217                         { .drv_type = drv1, .offset = offset1 },        \
 218                         { .drv_type = drv2, .offset = offset2 },        \
 219                         { .drv_type = drv3, .offset = offset3 },        \
 220                 },                                                      \
 221         }
 222
 223 /**
 224  */
 225 struct rockchip_pin_ctrl {
 226         struct rockchip_pin_bank        *pin_banks;
 227         u32                             nr_banks;
 228         u32                             nr_pins;
 229         char                            *label;
 230         enum rockchip_pinctrl_type      type;
 231         int                             grf_mux_offset;
 232         int                             pmu_mux_offset;
 233         int                             grf_drv_offset;
 234         int                             pmu_drv_offset;
 235
 236         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 237                                     int pin_num, struct regmap **regmap,
 238                                     int *reg, u8 *bit);
 239         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 240                                     int pin_num, struct regmap **regmap,
 241                                     int *reg, u8 *bit);
 242 };
 243
 244 struct rockchip_pin_config {
 245         unsigned int            func;
 246         unsigned long           *configs;
 247         unsigned int            nconfigs;
 248 };
 249
 250 /**
 251  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 252  * @name: name of the pin group, used to lookup the group.
 253  * @pins: the pins included in this group.
 254  * @npins: number of pins included in this group.
 255  * @func: the mux function number to be programmed when selected.
 256  * @configs: the config values to be set for each pin
 257  * @nconfigs: number of configs for each pin
 258  */
 259 struct rockchip_pin_group {
 260         const char                      *name;
 261         unsigned int                    npins;
 262         unsigned int                    *pins;
 263         struct rockchip_pin_config      *data;
 264 };
 265
 266 /**
 267  * struct rockchip_pmx_func: represent a pin function.
 268  * @name: name of the pin function, used to lookup the function.
 269  * @groups: one or more names of pin groups that provide this function.
 270  * @num_groups: number of groups included in @groups.
 271  */
 272 struct rockchip_pmx_func {
 273         const char              *name;
 274         const char              **groups;
 275         u8                      ngroups;
 276 };
 277
 278 struct rockchip_pinctrl {
 279         struct regmap                   *regmap_base;
 280         int                             reg_size;
 281         struct regmap                   *regmap_pull;
 282         struct regmap                   *regmap_pmu;
 283         struct device                   *dev;
 284         struct rockchip_pin_ctrl        *ctrl;
 285         struct pinctrl_desc             pctl;
 286         struct pinctrl_dev              *pctl_dev;
 287         struct rockchip_pin_group       *groups;
 288         unsigned int                    ngroups;
 289         struct rockchip_pmx_func        *functions;
 290         unsigned int                    nfunctions;
 291 };
 292
 293 static struct regmap_config rockchip_regmap_config = {
 294         .reg_bits = 32,
 295         .val_bits = 32,
 296         .reg_stride = 4,
 297 };
 298
 299 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 300 {
 301         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 302 }
 303
 304 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 305                                         const struct rockchip_pinctrl *info,
 306                                         const char *name)
 307 {
 308         int i;
 309
 310         for (i = 0; i < info->ngroups; i++) {
 311                 if (!strcmp(info->groups[i].name, name))
 312                         return &info->groups[i];
 313         }
 314
 315         return NULL;
 316 }
 317
 318 /*
 319  * given a pin number that is local to a pin controller, find out the pin bank
 320  * and the register base of the pin bank.
 321  */
 322 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 323                                                                 unsigned pin)
 324 {
 325         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 326
 327         while (pin >= (b->pin_base + b->nr_pins))
 328                 b++;
 329
 330         return b;
 331 }
 332
 333 static struct rockchip_pin_bank *bank_num_to_bank(
 334                                         struct rockchip_pinctrl *info,
 335                                         unsigned num)
 336 {
 337         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 338         int i;
 339
 340         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 341                 if (b->bank_num == num)
 342                         return b;
 343         }
 344
 345         return ERR_PTR(-EINVAL);
 346 }
 347
 348 /*
 349  * Pinctrl_ops handling
 350  */
 351
 352 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 353 {
 354         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 355
 356         return info->ngroups;
 357 }
 358
 359 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 360                                                         unsigned selector)
 361 {
 362         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 363
 364         return info->groups[selector].name;
 365 }
 366
 367 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 368                                       unsigned selector, const unsigned **pins,
 369                                       unsigned *npins)
 370 {
 371         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 372
 373         if (selector >= info->ngroups)
 374                 return -EINVAL;
 375
 376         *pins = info->groups[selector].pins;
 377         *npins = info->groups[selector].npins;
 378
 379         return 0;
 380 }
 381
 382 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 383                                  struct device_node *np,
 384                                  struct pinctrl_map **map, unsigned *num_maps)
 385 {
 386         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 387         const struct rockchip_pin_group *grp;
 388         struct pinctrl_map *new_map;
 389         struct device_node *parent;
 390         int map_num = 1;
 391         int i;
 392
 393         /*
 394          * first find the group of this node and check if we need to create
 395          * config maps for pins
 396          */
 397         grp = pinctrl_name_to_group(info, np->name);
 398         if (!grp) {
 399                 dev_err(info->dev, "unable to find group for node %s\n",
 400                         np->name);
 401                 return -EINVAL;
 402         }
 403
 404         map_num += grp->npins;
 405         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 406                                                                 GFP_KERNEL);
 407         if (!new_map)
 408                 return -ENOMEM;
 409
 410         *map = new_map;
 411         *num_maps = map_num;
 412
 413         /* create mux map */
 414         parent = of_get_parent(np);
 415         if (!parent) {
 416                 devm_kfree(pctldev->dev, new_map);
 417                 return -EINVAL;
 418         }
 419         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 420         new_map[0].data.mux.function = parent->name;
 421         new_map[0].data.mux.group = np->name;
 422         of_node_put(parent);
 423
 424         /* create config map */
 425         new_map++;
 426         for (i = 0; i < grp->npins; i++) {
 427                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 428                 new_map[i].data.configs.group_or_pin =
 429                                 pin_get_name(pctldev, grp->pins[i]);
 430                 new_map[i].data.configs.configs = grp->data[i].configs;
 431                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 432         }
 433
 434         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 435                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 436
 437         return 0;
 438 }
 439
 440 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 441                                     struct pinctrl_map *map, unsigned num_maps)
 442 {
 443 }
 444
 445 static const struct pinctrl_ops rockchip_pctrl_ops = {
 446         .get_groups_count       = rockchip_get_groups_count,
 447         .get_group_name         = rockchip_get_group_name,
 448         .get_group_pins         = rockchip_get_group_pins,
 449         .dt_node_to_map         = rockchip_dt_node_to_map,
 450         .dt_free_map            = rockchip_dt_free_map,
 451 };
 452
 453 /*
 454  * Hardware access
 455  */
 456
 457 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 458 {
 459         struct rockchip_pinctrl *info = bank->drvdata;
 460         int iomux_num = (pin / 8);
 461         struct regmap *regmap;
 462         unsigned int val;
 463         int reg, ret, mask;
 464         u8 bit;
 465
 466         if (iomux_num > 3)
 467                 return -EINVAL;
 468
 469         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 470                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 471                 return -EINVAL;
 472         }
 473
 474         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 475                 return RK_FUNC_GPIO;
 476
 477         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 478                                 ? info->regmap_pmu : info->regmap_base;
 479
 480         /* get basic quadrupel of mux registers and the correct reg inside */
 481         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 482         reg = bank->iomux[iomux_num].offset;
 483         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 484                 if ((pin % 8) >= 4)
 485                         reg += 0x4;
 486                 bit = (pin % 4) * 4;
 487         } else {
 488                 bit = (pin % 8) * 2;
 489         }
 490
 491         ret = regmap_read(regmap, reg, &val);
 492         if (ret)
 493                 return ret;
 494
 495         return ((val >> bit) & mask);
 496 }
 497
 498 /*
 499  * Set a new mux function for a pin.
 500  *
 501  * The register is divided into the upper and lower 16 bit. When changing
 502  * a value, the previous register value is not read and changed. Instead
 503  * it seems the changed bits are marked in the upper 16 bit, while the
 504  * changed value gets set in the same offset in the lower 16 bit.
 505  * All pin settings seem to be 2 bit wide in both the upper and lower
 506  * parts.
 507  * @bank: pin bank to change
 508  * @pin: pin to change
 509  * @mux: new mux function to set
 510  */
 511 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 512 {
 513         struct rockchip_pinctrl *info = bank->drvdata;
 514         int iomux_num = (pin / 8);
 515         struct regmap *regmap;
 516         int reg, ret, mask;
 517         unsigned long flags;
 518         u8 bit;
 519         u32 data, rmask;
 520
 521         if (iomux_num > 3)
 522                 return -EINVAL;
 523
 524         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 525                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 526                 return -EINVAL;
 527         }
 528
 529         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 530                 if (mux != RK_FUNC_GPIO) {
 531                         dev_err(info->dev,
 532                                 "pin %d only supports a gpio mux\n", pin);
 533                         return -ENOTSUPP;
 534                 } else {
 535                         return 0;
 536                 }
 537         }
 538
 539         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 540                                                 bank->bank_num, pin, mux);
 541
 542         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 543                                 ? info->regmap_pmu : info->regmap_base;
 544
 545         /* get basic quadrupel of mux registers and the correct reg inside */
 546         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 547         reg = bank->iomux[iomux_num].offset;
 548         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 549                 if ((pin % 8) >= 4)
 550                         reg += 0x4;
 551                 bit = (pin % 4) * 4;
 552         } else {
 553                 bit = (pin % 8) * 2;
 554         }
 555
 556         spin_lock_irqsave(&bank->slock, flags);
 557
 558         data = (mask << (bit + 16));
 559         rmask = data | (data >> 16);
 560         data |= (mux & mask) << bit;
 561         ret = regmap_update_bits(regmap, reg, rmask, data);
 562
 563         spin_unlock_irqrestore(&bank->slock, flags);
 564
 565         return ret;
 566 }
 567
 568 #define RK2928_PULL_OFFSET              0x118
 569 #define RK2928_PULL_PINS_PER_REG        16
 570 #define RK2928_PULL_BANK_STRIDE         8
 571
 572 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 573                                     int pin_num, struct regmap **regmap,
 574                                     int *reg, u8 *bit)
 575 {
 576         struct rockchip_pinctrl *info = bank->drvdata;
 577
 578         *regmap = info->regmap_base;
 579         *reg = RK2928_PULL_OFFSET;
 580         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 581         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 582
 583         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 584 };
 585
 586 #define RK3188_PULL_OFFSET              0x164
 587 #define RK3188_PULL_BITS_PER_PIN        2
 588 #define RK3188_PULL_PINS_PER_REG        8
 589 #define RK3188_PULL_BANK_STRIDE         16
 590 #define RK3188_PULL_PMU_OFFSET          0x64
 591
 592 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 593                                     int pin_num, struct regmap **regmap,
 594                                     int *reg, u8 *bit)
 595 {
 596         struct rockchip_pinctrl *info = bank->drvdata;
 597
 598         /* The first 12 pins of the first bank are located elsewhere */
 599         if (bank->bank_num == 0 && pin_num < 12) {
 600                 *regmap = info->regmap_pmu ? info->regmap_pmu
 601                                            : bank->regmap_pull;
 602                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
 603                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 604                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 605                 *bit *= RK3188_PULL_BITS_PER_PIN;
 606         } else {
 607                 *regmap = info->regmap_pull ? info->regmap_pull
 608                                             : info->regmap_base;
 609                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
 610
 611                 /* correct the offset, as it is the 2nd pull register */
 612                 *reg -= 4;
 613                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 614                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 615
 616                 /*
 617                  * The bits in these registers have an inverse ordering
 618                  * with the lowest pin being in bits 15:14 and the highest
 619                  * pin in bits 1:0
 620                  */
 621                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 622                 *bit *= RK3188_PULL_BITS_PER_PIN;
 623         }
 624 }
 625
 626 #define RK3288_PULL_OFFSET              0x140
 627 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 628                                     int pin_num, struct regmap **regmap,
 629                                     int *reg, u8 *bit)
 630 {
 631         struct rockchip_pinctrl *info = bank->drvdata;
 632
 633         /* The first 24 pins of the first bank are located in PMU */
 634         if (bank->bank_num == 0) {
 635                 *regmap = info->regmap_pmu;
 636                 *reg = RK3188_PULL_PMU_OFFSET;
 637
 638                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 639                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 640                 *bit *= RK3188_PULL_BITS_PER_PIN;
 641         } else {
 642                 *regmap = info->regmap_base;
 643                 *reg = RK3288_PULL_OFFSET;
 644
 645                 /* correct the offset, as we're starting with the 2nd bank */
 646                 *reg -= 0x10;
 647                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 648                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 649
 650                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 651                 *bit *= RK3188_PULL_BITS_PER_PIN;
 652         }
 653 }
 654
 655 #define RK3288_DRV_PMU_OFFSET           0x70
 656 #define RK3288_DRV_GRF_OFFSET           0x1c0
 657 #define RK3288_DRV_BITS_PER_PIN         2
 658 #define RK3288_DRV_PINS_PER_REG         8
 659 #define RK3288_DRV_BANK_STRIDE          16
 660
 661 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 662                                     int pin_num, struct regmap **regmap,
 663                                     int *reg, u8 *bit)
 664 {
 665         struct rockchip_pinctrl *info = bank->drvdata;
 666
 667         /* The first 24 pins of the first bank are located in PMU */
 668         if (bank->bank_num == 0) {
 669                 *regmap = info->regmap_pmu;
 670                 *reg = RK3288_DRV_PMU_OFFSET;
 671
 672                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 673                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 674                 *bit *= RK3288_DRV_BITS_PER_PIN;
 675         } else {
 676                 *regmap = info->regmap_base;
 677                 *reg = RK3288_DRV_GRF_OFFSET;
 678
 679                 /* correct the offset, as we're starting with the 2nd bank */
 680                 *reg -= 0x10;
 681                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 682                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 683
 684                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 685                 *bit *= RK3288_DRV_BITS_PER_PIN;
 686         }
 687 }
 688
 689 #define RK3228_PULL_OFFSET              0x100
 690
 691 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 692                                     int pin_num, struct regmap **regmap,
 693                                     int *reg, u8 *bit)
 694 {
 695         struct rockchip_pinctrl *info = bank->drvdata;
 696
 697         *regmap = info->regmap_base;
 698         *reg = RK3228_PULL_OFFSET;
 699         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 700         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 701
 702         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 703         *bit *= RK3188_PULL_BITS_PER_PIN;
 704 }
 705
 706 #define RK3228_DRV_GRF_OFFSET           0x200
 707
 708 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 709                                     int pin_num, struct regmap **regmap,
 710                                     int *reg, u8 *bit)
 711 {
 712         struct rockchip_pinctrl *info = bank->drvdata;
 713
 714         *regmap = info->regmap_base;
 715         *reg = RK3228_DRV_GRF_OFFSET;
 716         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 717         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 718
 719         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 720         *bit *= RK3288_DRV_BITS_PER_PIN;
 721 }
 722
 723 #define RK3368_PULL_GRF_OFFSET          0x100
 724 #define RK3368_PULL_PMU_OFFSET          0x10
 725
 726 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 727                                     int pin_num, struct regmap **regmap,
 728                                     int *reg, u8 *bit)
 729 {
 730         struct rockchip_pinctrl *info = bank->drvdata;
 731
 732         /* The first 32 pins of the first bank are located in PMU */
 733         if (bank->bank_num == 0) {
 734                 *regmap = info->regmap_pmu;
 735                 *reg = RK3368_PULL_PMU_OFFSET;
 736
 737                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 738                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 739                 *bit *= RK3188_PULL_BITS_PER_PIN;
 740         } else {
 741                 *regmap = info->regmap_base;
 742                 *reg = RK3368_PULL_GRF_OFFSET;
 743
 744                 /* correct the offset, as we're starting with the 2nd bank */
 745                 *reg -= 0x10;
 746                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 747                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 748
 749                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 750                 *bit *= RK3188_PULL_BITS_PER_PIN;
 751         }
 752 }
 753
 754 #define RK3368_DRV_PMU_OFFSET           0x20
 755 #define RK3368_DRV_GRF_OFFSET           0x200
 756
 757 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 758                                     int pin_num, struct regmap **regmap,
 759                                     int *reg, u8 *bit)
 760 {
 761         struct rockchip_pinctrl *info = bank->drvdata;
 762
 763         /* The first 32 pins of the first bank are located in PMU */
 764         if (bank->bank_num == 0) {
 765                 *regmap = info->regmap_pmu;
 766                 *reg = RK3368_DRV_PMU_OFFSET;
 767
 768                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 769                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 770                 *bit *= RK3288_DRV_BITS_PER_PIN;
 771         } else {
 772                 *regmap = info->regmap_base;
 773                 *reg = RK3368_DRV_GRF_OFFSET;
 774
 775                 /* correct the offset, as we're starting with the 2nd bank */
 776                 *reg -= 0x10;
 777                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 778                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 779
 780                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 781                 *bit *= RK3288_DRV_BITS_PER_PIN;
 782         }
 783 }
 784
 785 #define RK3399_PULL_GRF_OFFSET          0xe040
 786 #define RK3399_PULL_PMU_OFFSET          0x40
 787 #define RK3399_DRV_3BITS_PER_PIN        3
 788
 789 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 790                                          int pin_num, struct regmap **regmap,
 791                                          int *reg, u8 *bit)
 792 {
 793         struct rockchip_pinctrl *info = bank->drvdata;
 794
 795         /* The bank0:16 and bank1:32 pins are located in PMU */
 796         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
 797                 *regmap = info->regmap_pmu;
 798                 *reg = RK3399_PULL_PMU_OFFSET;
 799
 800                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 801
 802                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 803                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 804                 *bit *= RK3188_PULL_BITS_PER_PIN;
 805         } else {
 806                 *regmap = info->regmap_base;
 807                 *reg = RK3399_PULL_GRF_OFFSET;
 808
 809                 /* correct the offset, as we're starting with the 3rd bank */
 810                 *reg -= 0x20;
 811                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 812                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 813
 814                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 815                 *bit *= RK3188_PULL_BITS_PER_PIN;
 816         }
 817 }
 818
 819 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 820                                         int pin_num, struct regmap **regmap,
 821                                         int *reg, u8 *bit)
 822 {
 823         struct rockchip_pinctrl *info = bank->drvdata;
 824         int drv_num = (pin_num / 8);
 825
 826         /*  The bank0:16 and bank1:32 pins are located in PMU */
 827         if ((bank->bank_num == 0) || (bank->bank_num == 1))
 828                 *regmap = info->regmap_pmu;
 829         else
 830                 *regmap = info->regmap_base;
 831
 832         *reg = bank->drv[drv_num].offset;
 833         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
 834             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
 835                 *bit = (pin_num % 8) * 3;
 836         else
 837                 *bit = (pin_num % 8) * 2;
 838 }
 839
 840 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
 841         { 2, 4, 8, 12, -1, -1, -1, -1 },
 842         { 3, 6, 9, 12, -1, -1, -1, -1 },
 843         { 5, 10, 15, 20, -1, -1, -1, -1 },
 844         { 4, 6, 8, 10, 12, 14, 16, 18 },
 845         { 4, 7, 10, 13, 16, 19, 22, 26 }
 846 };
 847
 848 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
 849                                      int pin_num)
 850 {
 851         struct rockchip_pinctrl *info = bank->drvdata;
 852         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 853         struct regmap *regmap;
 854         int reg, ret;
 855         u32 data, temp, rmask_bits;
 856         u8 bit;
 857         int drv_type = bank->drv[pin_num / 8].drv_type;
 858
 859         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 860
 861         switch (drv_type) {
 862         case DRV_TYPE_IO_1V8_3V0_AUTO:
 863         case DRV_TYPE_IO_3V3_ONLY:
 864                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
 865                 switch (bit) {
 866                 case 0 ... 12:
 867                         /* regular case, nothing to do */
 868                         break;
 869                 case 15:
 870                         /*
 871                          * drive-strength offset is special, as it is
 872                          * spread over 2 registers
 873                          */
 874                         ret = regmap_read(regmap, reg, &data);
 875                         if (ret)
 876                                 return ret;
 877
 878                         ret = regmap_read(regmap, reg + 0x4, &temp);
 879                         if (ret)
 880                                 return ret;
 881
 882                         /*
 883                          * the bit data[15] contains bit 0 of the value
 884                          * while temp[1:0] contains bits 2 and 1
 885                          */
 886                         data >>= 15;
 887                         temp &= 0x3;
 888                         temp <<= 1;
 889                         data |= temp;
 890
 891                         return rockchip_perpin_drv_list[drv_type][data];
 892                 case 18 ... 21:
 893                         /* setting fully enclosed in the second register */
 894                         reg += 4;
 895                         bit -= 16;
 896                         break;
 897                 default:
 898                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
 899                                 bit, drv_type);
 900                         return -EINVAL;
 901                 }
 902
 903                 break;
 904         case DRV_TYPE_IO_DEFAULT:
 905         case DRV_TYPE_IO_1V8_OR_3V0:
 906         case DRV_TYPE_IO_1V8_ONLY:
 907                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
 908                 break;
 909         default:
 910                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
 911                         drv_type);
 912                 return -EINVAL;
 913         }
 914
 915         ret = regmap_read(regmap, reg, &data);
 916         if (ret)
 917                 return ret;
 918
 919         data >>= bit;
 920         data &= (1 << rmask_bits) - 1;
 921
 922         return rockchip_perpin_drv_list[drv_type][data];
 923 }
 924
 925 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
 926                                      int pin_num, int strength)
 927 {
 928         struct rockchip_pinctrl *info = bank->drvdata;
 929         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 930         struct regmap *regmap;
 931         unsigned long flags;
 932         int reg, ret, i;
 933         u32 data, rmask, rmask_bits, temp;
 934         u8 bit;
 935         int drv_type = bank->drv[pin_num / 8].drv_type;
 936
 937         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
 938                 bank->bank_num, pin_num, strength);
 939
 940         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 941
 942         ret = -EINVAL;
 943         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
 944                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
 945                         ret = i;
 946                         break;
 947                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
 948                         ret = rockchip_perpin_drv_list[drv_type][i];
 949                         break;
 950                 }
 951         }
 952
 953         if (ret < 0) {
 954                 dev_err(info->dev, "unsupported driver strength %d\n",
 955                         strength);
 956                 return ret;
 957         }
 958
 959         spin_lock_irqsave(&bank->slock, flags);
 960
 961         switch (drv_type) {
 962         case DRV_TYPE_IO_1V8_3V0_AUTO:
 963         case DRV_TYPE_IO_3V3_ONLY:
 964                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
 965                 switch (bit) {
 966                 case 0 ... 12:
 967                         /* regular case, nothing to do */
 968                         break;
 969                 case 15:
 970                         /*
 971                          * drive-strength offset is special, as it is spread
 972                          * over 2 registers, the bit data[15] contains bit 0
 973                          * of the value while temp[1:0] contains bits 2 and 1
 974                          */
 975                         data = (ret & 0x1) << 15;
 976                         temp = (ret >> 0x1) & 0x3;
 977
 978                         rmask = BIT(15) | BIT(31);
 979                         data |= BIT(31);
 980                         ret = regmap_update_bits(regmap, reg, rmask, data);
 981                         if (ret) {
 982                                 spin_unlock_irqrestore(&bank->slock, flags);
 983                                 return ret;
 984                         }
 985
 986                         rmask = 0x3 | (0x3 << 16);
 987                         temp |= (0x3 << 16);
 988                         reg += 0x4;
 989                         ret = regmap_update_bits(regmap, reg, rmask, temp);
 990
 991                         spin_unlock_irqrestore(&bank->slock, flags);
 992                         return ret;
 993                 case 18 ... 21:
 994                         /* setting fully enclosed in the second register */
 995                         reg += 4;
 996                         bit -= 16;
 997                         break;
 998                 default:
 999                         spin_unlock_irqrestore(&bank->slock, flags);
1000                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1001                                 bit, drv_type);
1002                         return -EINVAL;
1003                 }
1004                 break;
1005         case DRV_TYPE_IO_DEFAULT:
1006         case DRV_TYPE_IO_1V8_OR_3V0:
1007         case DRV_TYPE_IO_1V8_ONLY:
1008                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1009                 break;
1010         default:
1011                 spin_unlock_irqrestore(&bank->slock, flags);
1012                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1013                         drv_type);
1014                 return -EINVAL;
1015         }
1016
1017         /* enable the write to the equivalent lower bits */
1018         data = ((1 << rmask_bits) - 1) << (bit + 16);
1019         rmask = data | (data >> 16);
1020         data |= (ret << bit);
1021
1022         ret = regmap_update_bits(regmap, reg, rmask, data);
1023         spin_unlock_irqrestore(&bank->slock, flags);
1024
1025         return ret;
1026 }
1027
1028 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1029 {
1030         struct rockchip_pinctrl *info = bank->drvdata;
1031         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1032         struct regmap *regmap;
1033         int reg, ret;
1034         u8 bit;
1035         u32 data;
1036
1037         /* rk3066b does support any pulls */
1038         if (ctrl->type == RK3066B)
1039                 return PIN_CONFIG_BIAS_DISABLE;
1040
1041         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1042
1043         ret = regmap_read(regmap, reg, &data);
1044         if (ret)
1045                 return ret;
1046
1047         switch (ctrl->type) {
1048         case RK2928:
1049                 return !(data & BIT(bit))
1050                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1051                                 : PIN_CONFIG_BIAS_DISABLE;
1052         case RK3188:
1053         case RK3288:
1054         case RK3368:
1055         case RK3399:
1056                 data >>= bit;
1057                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1058
1059                 switch (data) {
1060                 case 0:
1061                         return PIN_CONFIG_BIAS_DISABLE;
1062                 case 1:
1063                         return PIN_CONFIG_BIAS_PULL_UP;
1064                 case 2:
1065                         return PIN_CONFIG_BIAS_PULL_DOWN;
1066                 case 3:
1067                         return PIN_CONFIG_BIAS_BUS_HOLD;
1068                 }
1069
1070                 dev_err(info->dev, "unknown pull setting\n");
1071                 return -EIO;
1072         default:
1073                 dev_err(info->dev, "unsupported pinctrl type\n");
1074                 return -EINVAL;
1075         };
1076 }
1077
1078 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1079                                         int pin_num, int pull)
1080 {
1081         struct rockchip_pinctrl *info = bank->drvdata;
1082         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1083         struct regmap *regmap;
1084         int reg, ret;
1085         unsigned long flags;
1086         u8 bit;
1087         u32 data, rmask;
1088
1089         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1090                  bank->bank_num, pin_num, pull);
1091
1092         /* rk3066b does support any pulls */
1093         if (ctrl->type == RK3066B)
1094                 return pull ? -EINVAL : 0;
1095
1096         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1097
1098         switch (ctrl->type) {
1099         case RK2928:
1100                 spin_lock_irqsave(&bank->slock, flags);
1101
1102                 data = BIT(bit + 16);
1103                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1104                         data |= BIT(bit);
1105                 ret = regmap_write(regmap, reg, data);
1106
1107                 spin_unlock_irqrestore(&bank->slock, flags);
1108                 break;
1109         case RK3188:
1110         case RK3288:
1111         case RK3368:
1112         case RK3399:
1113                 spin_lock_irqsave(&bank->slock, flags);
1114
1115                 /* enable the write to the equivalent lower bits */
1116                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1117                 rmask = data | (data >> 16);
1118
1119                 switch (pull) {
1120                 case PIN_CONFIG_BIAS_DISABLE:
1121                         break;
1122                 case PIN_CONFIG_BIAS_PULL_UP:
1123                         data |= (1 << bit);
1124                         break;
1125                 case PIN_CONFIG_BIAS_PULL_DOWN:
1126                         data |= (2 << bit);
1127                         break;
1128                 case PIN_CONFIG_BIAS_BUS_HOLD:
1129                         data |= (3 << bit);
1130                         break;
1131                 default:
1132                         spin_unlock_irqrestore(&bank->slock, flags);
1133                         dev_err(info->dev, "unsupported pull setting %d\n",
1134                                 pull);
1135                         return -EINVAL;
1136                 }
1137
1138                 ret = regmap_update_bits(regmap, reg, rmask, data);
1139
1140                 spin_unlock_irqrestore(&bank->slock, flags);
1141                 break;
1142         default:
1143                 dev_err(info->dev, "unsupported pinctrl type\n");
1144                 return -EINVAL;
1145         }
1146
1147         return ret;
1148 }
1149
1150 /*
1151  * Pinmux_ops handling
1152  */
1153
1154 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1155 {
1156         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1157
1158         return info->nfunctions;
1159 }
1160
1161 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1162                                           unsigned selector)
1163 {
1164         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1165
1166         return info->functions[selector].name;
1167 }
1168
1169 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1170                                 unsigned selector, const char * const **groups,
1171                                 unsigned * const num_groups)
1172 {
1173         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1174
1175         *groups = info->functions[selector].groups;
1176         *num_groups = info->functions[selector].ngroups;
1177
1178         return 0;
1179 }
1180
1181 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1182                             unsigned group)
1183 {
1184         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1185         const unsigned int *pins = info->groups[group].pins;
1186         const struct rockchip_pin_config *data = info->groups[group].data;
1187         struct rockchip_pin_bank *bank;
1188         int cnt, ret = 0;
1189
1190         dev_dbg(info->dev, "enable function %s group %s\n",
1191                 info->functions[selector].name, info->groups[group].name);
1192
1193         /*
1194          * for each pin in the pin group selected, program the correspoding pin
1195          * pin function number in the config register.
1196          */
1197         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1198                 bank = pin_to_bank(info, pins[cnt]);
1199                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1200                                        data[cnt].func);
1201                 if (ret)
1202                         break;
1203         }
1204
1205         if (ret) {
1206                 /* revert the already done pin settings */
1207                 for (cnt--; cnt >= 0; cnt--)
1208                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1209
1210                 return ret;
1211         }
1212
1213         return 0;
1214 }
1215
1216 /*
1217  * The calls to gpio_direction_output() and gpio_direction_input()
1218  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1219  * function called from the gpiolib interface).
1220  */
1221 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1222                                             int pin, bool input)
1223 {
1224         struct rockchip_pin_bank *bank;
1225         int ret;
1226         unsigned long flags;
1227         u32 data;
1228
1229         bank = gc_to_pin_bank(chip);
1230
1231         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1232         if (ret < 0)
1233                 return ret;
1234
1235         clk_enable(bank->clk);
1236         spin_lock_irqsave(&bank->slock, flags);
1237
1238         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1239         /* set bit to 1 for output, 0 for input */
1240         if (!input)
1241                 data |= BIT(pin);
1242         else
1243                 data &= ~BIT(pin);
1244         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1245
1246         spin_unlock_irqrestore(&bank->slock, flags);
1247         clk_disable(bank->clk);
1248
1249         return 0;
1250 }
1251
1252 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1253                                               struct pinctrl_gpio_range *range,
1254                                               unsigned offset, bool input)
1255 {
1256         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1257         struct gpio_chip *chip;
1258         int pin;
1259
1260         chip = range->gc;
1261         pin = offset - chip->base;
1262         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1263                  offset, range->name, pin, input ? "input" : "output");
1264
1265         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1266                                                 input);
1267 }
1268
1269 static const struct pinmux_ops rockchip_pmx_ops = {
1270         .get_functions_count    = rockchip_pmx_get_funcs_count,
1271         .get_function_name      = rockchip_pmx_get_func_name,
1272         .get_function_groups    = rockchip_pmx_get_groups,
1273         .set_mux                = rockchip_pmx_set,
1274         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
1275 };
1276
1277 /*
1278  * Pinconf_ops handling
1279  */
1280
1281 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1282                                         enum pin_config_param pull)
1283 {
1284         switch (ctrl->type) {
1285         case RK2928:
1286                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1287                                         pull == PIN_CONFIG_BIAS_DISABLE);
1288         case RK3066B:
1289                 return pull ? false : true;
1290         case RK3188:
1291         case RK3288:
1292         case RK3368:
1293         case RK3399:
1294                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1295         }
1296
1297         return false;
1298 }
1299
1300 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
1301 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1302
1303 /* set the pin config settings for a specified pin */
1304 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1305                                 unsigned long *configs, unsigned num_configs)
1306 {
1307         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1308         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1309         enum pin_config_param param;
1310         u16 arg;
1311         int i;
1312         int rc;
1313
1314         for (i = 0; i < num_configs; i++) {
1315                 param = pinconf_to_config_param(configs[i]);
1316                 arg = pinconf_to_config_argument(configs[i]);
1317
1318                 switch (param) {
1319                 case PIN_CONFIG_BIAS_DISABLE:
1320                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
1321                                 param);
1322                         if (rc)
1323                                 return rc;
1324                         break;
1325                 case PIN_CONFIG_BIAS_PULL_UP:
1326                 case PIN_CONFIG_BIAS_PULL_DOWN:
1327                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1328                 case PIN_CONFIG_BIAS_BUS_HOLD:
1329                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1330                                 return -ENOTSUPP;
1331
1332                         if (!arg)
1333                                 return -EINVAL;
1334
1335                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
1336                                 param);
1337                         if (rc)
1338                                 return rc;
1339                         break;
1340                 case PIN_CONFIG_OUTPUT:
1341                         rockchip_gpio_set(&bank->gpio_chip,
1342                                           pin - bank->pin_base, arg);
1343                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1344                                           pin - bank->pin_base, false);
1345                         if (rc)
1346                                 return rc;
1347                         break;
1348                 case PIN_CONFIG_DRIVE_STRENGTH:
1349                         /* rk3288 is the first with per-pin drive-strength */
1350                         if (!info->ctrl->drv_calc_reg)
1351                                 return -ENOTSUPP;
1352
1353                         rc = rockchip_set_drive_perpin(bank,
1354                                                 pin - bank->pin_base, arg);
1355                         if (rc < 0)
1356                                 return rc;
1357                         break;
1358                 default:
1359                         return -ENOTSUPP;
1360                         break;
1361                 }
1362         } /* for each config */
1363
1364         return 0;
1365 }
1366
1367 /* get the pin config settings for a specified pin */
1368 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1369                                                         unsigned long *config)
1370 {
1371         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1372         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1373         enum pin_config_param param = pinconf_to_config_param(*config);
1374         u16 arg;
1375         int rc;
1376
1377         switch (param) {
1378         case PIN_CONFIG_BIAS_DISABLE:
1379                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1380                         return -EINVAL;
1381
1382                 arg = 0;
1383                 break;
1384         case PIN_CONFIG_BIAS_PULL_UP:
1385         case PIN_CONFIG_BIAS_PULL_DOWN:
1386         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1387         case PIN_CONFIG_BIAS_BUS_HOLD:
1388                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1389                         return -ENOTSUPP;
1390
1391                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1392                         return -EINVAL;
1393
1394                 arg = 1;
1395                 break;
1396         case PIN_CONFIG_OUTPUT:
1397                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1398                 if (rc != RK_FUNC_GPIO)
1399                         return -EINVAL;
1400
1401                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1402                 if (rc < 0)
1403                         return rc;
1404
1405                 arg = rc ? 1 : 0;
1406                 break;
1407         case PIN_CONFIG_DRIVE_STRENGTH:
1408                 /* rk3288 is the first with per-pin drive-strength */
1409                 if (!info->ctrl->drv_calc_reg)
1410                         return -ENOTSUPP;
1411
1412                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
1413                 if (rc < 0)
1414                         return rc;
1415
1416                 arg = rc;
1417                 break;
1418         default:
1419                 return -ENOTSUPP;
1420                 break;
1421         }
1422
1423         *config = pinconf_to_config_packed(param, arg);
1424
1425         return 0;
1426 }
1427
1428 static const struct pinconf_ops rockchip_pinconf_ops = {
1429         .pin_config_get                 = rockchip_pinconf_get,
1430         .pin_config_set                 = rockchip_pinconf_set,
1431         .is_generic                     = true,
1432 };
1433
1434 static const struct of_device_id rockchip_bank_match[] = {
1435         { .compatible = "rockchip,gpio-bank" },
1436         { .compatible = "rockchip,rk3188-gpio-bank0" },
1437         {},
1438 };
1439
1440 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1441                                                 struct device_node *np)
1442 {
1443         struct device_node *child;
1444
1445         for_each_child_of_node(np, child) {
1446                 if (of_match_node(rockchip_bank_match, child))
1447                         continue;
1448
1449                 info->nfunctions++;
1450                 info->ngroups += of_get_child_count(child);
1451         }
1452 }
1453
1454 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1455                                               struct rockchip_pin_group *grp,
1456                                               struct rockchip_pinctrl *info,
1457                                               u32 index)
1458 {
1459         struct rockchip_pin_bank *bank;
1460         int size;
1461         const __be32 *list;
1462         int num;
1463         int i, j;
1464         int ret;
1465
1466         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1467
1468         /* Initialise group */
1469         grp->name = np->name;
1470
1471         /*
1472          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1473          * do sanity check and calculate pins number
1474          */
1475         list = of_get_property(np, "rockchip,pins", &size);
1476         /* we do not check return since it's safe node passed down */
1477         size /= sizeof(*list);
1478         if (!size || size % 4) {
1479                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1480                 return -EINVAL;
1481         }
1482
1483         grp->npins = size / 4;
1484
1485         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1486                                                 GFP_KERNEL);
1487         grp->data = devm_kzalloc(info->dev, grp->npins *
1488                                           sizeof(struct rockchip_pin_config),
1489                                         GFP_KERNEL);
1490         if (!grp->pins || !grp->data)
1491                 return -ENOMEM;
1492
1493         for (i = 0, j = 0; i < size; i += 4, j++) {
1494                 const __be32 *phandle;
1495                 struct device_node *np_config;
1496
1497                 num = be32_to_cpu(*list++);
1498                 bank = bank_num_to_bank(info, num);
1499                 if (IS_ERR(bank))
1500                         return PTR_ERR(bank);
1501
1502                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1503                 grp->data[j].func = be32_to_cpu(*list++);
1504
1505                 phandle = list++;
1506                 if (!phandle)
1507                         return -EINVAL;
1508
1509                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1510                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
1511                                 &grp->data[j].configs, &grp->data[j].nconfigs);
1512                 if (ret)
1513                         return ret;
1514         }
1515
1516         return 0;
1517 }
1518
1519 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1520                                                 struct rockchip_pinctrl *info,
1521                                                 u32 index)
1522 {
1523         struct device_node *child;
1524         struct rockchip_pmx_func *func;
1525         struct rockchip_pin_group *grp;
1526         int ret;
1527         static u32 grp_index;
1528         u32 i = 0;
1529
1530         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1531
1532         func = &info->functions[index];
1533
1534         /* Initialise function */
1535         func->name = np->name;
1536         func->ngroups = of_get_child_count(np);
1537         if (func->ngroups <= 0)
1538                 return 0;
1539
1540         func->groups = devm_kzalloc(info->dev,
1541                         func->ngroups * sizeof(char *), GFP_KERNEL);
1542         if (!func->groups)
1543                 return -ENOMEM;
1544
1545         for_each_child_of_node(np, child) {
1546                 func->groups[i] = child->name;
1547                 grp = &info->groups[grp_index++];
1548                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1549                 if (ret) {
1550                         of_node_put(child);
1551                         return ret;
1552                 }
1553         }
1554
1555         return 0;
1556 }
1557
1558 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1559                                               struct rockchip_pinctrl *info)
1560 {
1561         struct device *dev = &pdev->dev;
1562         struct device_node *np = dev->of_node;
1563         struct device_node *child;
1564         int ret;
1565         int i;
1566
1567         rockchip_pinctrl_child_count(info, np);
1568
1569         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1570         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1571
1572         info->functions = devm_kzalloc(dev, info->nfunctions *
1573                                               sizeof(struct rockchip_pmx_func),
1574                                               GFP_KERNEL);
1575         if (!info->functions) {
1576                 dev_err(dev, "failed to allocate memory for function list\n");
1577                 return -EINVAL;
1578         }
1579
1580         info->groups = devm_kzalloc(dev, info->ngroups *
1581                                             sizeof(struct rockchip_pin_group),
1582                                             GFP_KERNEL);
1583         if (!info->groups) {
1584                 dev_err(dev, "failed allocate memory for ping group list\n");
1585                 return -EINVAL;
1586         }
1587
1588         i = 0;
1589
1590         for_each_child_of_node(np, child) {
1591                 if (of_match_node(rockchip_bank_match, child))
1592                         continue;
1593
1594                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1595                 if (ret) {
1596                         dev_err(&pdev->dev, "failed to parse function\n");
1597                         of_node_put(child);
1598                         return ret;
1599                 }
1600         }
1601
1602         return 0;
1603 }
1604
1605 static int rockchip_pinctrl_register(struct platform_device *pdev,
1606                                         struct rockchip_pinctrl *info)
1607 {
1608         struct pinctrl_desc *ctrldesc = &info->pctl;
1609         struct pinctrl_pin_desc *pindesc, *pdesc;
1610         struct rockchip_pin_bank *pin_bank;
1611         int pin, bank, ret;
1612         int k;
1613
1614         ctrldesc->name = "rockchip-pinctrl";
1615         ctrldesc->owner = THIS_MODULE;
1616         ctrldesc->pctlops = &rockchip_pctrl_ops;
1617         ctrldesc->pmxops = &rockchip_pmx_ops;
1618         ctrldesc->confops = &rockchip_pinconf_ops;
1619
1620         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1621                         info->ctrl->nr_pins, GFP_KERNEL);
1622         if (!pindesc) {
1623                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1624                 return -ENOMEM;
1625         }
1626         ctrldesc->pins = pindesc;
1627         ctrldesc->npins = info->ctrl->nr_pins;
1628
1629         pdesc = pindesc;
1630         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1631                 pin_bank = &info->ctrl->pin_banks[bank];
1632                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1633                         pdesc->number = k;
1634                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1635                                                 pin_bank->name, pin);
1636                         pdesc++;
1637                 }
1638         }
1639
1640         ret = rockchip_pinctrl_parse_dt(pdev, info);
1641         if (ret)
1642                 return ret;
1643
1644         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1645         if (IS_ERR(info->pctl_dev)) {
1646                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1647                 return PTR_ERR(info->pctl_dev);
1648         }
1649
1650         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1651                 pin_bank = &info->ctrl->pin_banks[bank];
1652                 pin_bank->grange.name = pin_bank->name;
1653                 pin_bank->grange.id = bank;
1654                 pin_bank->grange.pin_base = pin_bank->pin_base;
1655                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1656                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1657                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1658                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1659         }
1660
1661         return 0;
1662 }
1663
1664 /*
1665  * GPIO handling
1666  */
1667
1668 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1669 {
1670         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1671         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1672         unsigned long flags;
1673         u32 data;
1674
1675         clk_enable(bank->clk);
1676         spin_lock_irqsave(&bank->slock, flags);
1677
1678         data = readl(reg);
1679         data &= ~BIT(offset);
1680         if (value)
1681                 data |= BIT(offset);
1682         writel(data, reg);
1683
1684         spin_unlock_irqrestore(&bank->slock, flags);
1685         clk_disable(bank->clk);
1686 }
1687
1688 /*
1689  * Returns the level of the pin for input direction and setting of the DR
1690  * register for output gpios.
1691  */
1692 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1693 {
1694         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1695         u32 data;
1696
1697         clk_enable(bank->clk);
1698         data = readl(bank->reg_base + GPIO_EXT_PORT);
1699         clk_disable(bank->clk);
1700         data >>= offset;
1701         data &= 1;
1702         return data;
1703 }
1704
1705 /*
1706  * gpiolib gpio_direction_input callback function. The setting of the pin
1707  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1708  * interface.
1709  */
1710 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1711 {
1712         return pinctrl_gpio_direction_input(gc->base + offset);
1713 }
1714
1715 /*
1716  * gpiolib gpio_direction_output callback function. The setting of the pin
1717  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1718  * interface.
1719  */
1720 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1721                                           unsigned offset, int value)
1722 {
1723         rockchip_gpio_set(gc, offset, value);
1724         return pinctrl_gpio_direction_output(gc->base + offset);
1725 }
1726
1727 /*
1728  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1729  * and a virtual IRQ, if not already present.
1730  */
1731 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1732 {
1733         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1734         unsigned int virq;
1735
1736         if (!bank->domain)
1737                 return -ENXIO;
1738
1739         virq = irq_create_mapping(bank->domain, offset);
1740
1741         return (virq) ? : -ENXIO;
1742 }
1743
1744 static const struct gpio_chip rockchip_gpiolib_chip = {
1745         .request = gpiochip_generic_request,
1746         .free = gpiochip_generic_free,
1747         .set = rockchip_gpio_set,
1748         .get = rockchip_gpio_get,
1749         .direction_input = rockchip_gpio_direction_input,
1750         .direction_output = rockchip_gpio_direction_output,
1751         .to_irq = rockchip_gpio_to_irq,
1752         .owner = THIS_MODULE,
1753 };
1754
1755 /*
1756  * Interrupt handling
1757  */
1758
1759 static void rockchip_irq_demux(struct irq_desc *desc)
1760 {
1761         struct irq_chip *chip = irq_desc_get_chip(desc);
1762         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
1763         u32 pend;
1764
1765         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1766
1767         chained_irq_enter(chip, desc);
1768
1769         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1770
1771         while (pend) {
1772                 unsigned int irq, virq;
1773
1774                 irq = __ffs(pend);
1775                 pend &= ~BIT(irq);
1776                 virq = irq_linear_revmap(bank->domain, irq);
1777
1778                 if (!virq) {
1779                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1780                         continue;
1781                 }
1782
1783                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1784
1785                 /*
1786                  * Triggering IRQ on both rising and falling edge
1787                  * needs manual intervention.
1788                  */
1789                 if (bank->toggle_edge_mode & BIT(irq)) {
1790                         u32 data, data_old, polarity;
1791                         unsigned long flags;
1792
1793                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1794                         do {
1795                                 spin_lock_irqsave(&bank->slock, flags);
1796
1797                                 polarity = readl_relaxed(bank->reg_base +
1798                                                          GPIO_INT_POLARITY);
1799                                 if (data & BIT(irq))
1800                                         polarity &= ~BIT(irq);
1801                                 else
1802                                         polarity |= BIT(irq);
1803                                 writel(polarity,
1804                                        bank->reg_base + GPIO_INT_POLARITY);
1805
1806                                 spin_unlock_irqrestore(&bank->slock, flags);
1807
1808                                 data_old = data;
1809                                 data = readl_relaxed(bank->reg_base +
1810                                                      GPIO_EXT_PORT);
1811                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
1812                 }
1813
1814                 generic_handle_irq(virq);
1815         }
1816
1817         chained_irq_exit(chip, desc);
1818 }
1819
1820 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1821 {
1822         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1823         struct rockchip_pin_bank *bank = gc->private;
1824         u32 mask = BIT(d->hwirq);
1825         u32 polarity;
1826         u32 level;
1827         u32 data;
1828         unsigned long flags;
1829         int ret;
1830
1831         /* make sure the pin is configured as gpio input */
1832         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1833         if (ret < 0)
1834                 return ret;
1835
1836         clk_enable(bank->clk);
1837         spin_lock_irqsave(&bank->slock, flags);
1838
1839         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1840         data &= ~mask;
1841         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1842
1843         spin_unlock_irqrestore(&bank->slock, flags);
1844
1845         if (type & IRQ_TYPE_EDGE_BOTH)
1846                 irq_set_handler_locked(d, handle_edge_irq);
1847         else
1848                 irq_set_handler_locked(d, handle_level_irq);
1849
1850         spin_lock_irqsave(&bank->slock, flags);
1851         irq_gc_lock(gc);
1852
1853         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1854         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1855
1856         switch (type) {
1857         case IRQ_TYPE_EDGE_BOTH:
1858                 bank->toggle_edge_mode |= mask;
1859                 level |= mask;
1860
1861                 /*
1862                  * Determine gpio state. If 1 next interrupt should be falling
1863                  * otherwise rising.
1864                  */
1865                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1866                 if (data & mask)
1867                         polarity &= ~mask;
1868                 else
1869                         polarity |= mask;
1870                 break;
1871         case IRQ_TYPE_EDGE_RISING:
1872                 bank->toggle_edge_mode &= ~mask;
1873                 level |= mask;
1874                 polarity |= mask;
1875                 break;
1876         case IRQ_TYPE_EDGE_FALLING:
1877                 bank->toggle_edge_mode &= ~mask;
1878                 level |= mask;
1879                 polarity &= ~mask;
1880                 break;
1881         case IRQ_TYPE_LEVEL_HIGH:
1882                 bank->toggle_edge_mode &= ~mask;
1883                 level &= ~mask;
1884                 polarity |= mask;
1885                 break;
1886         case IRQ_TYPE_LEVEL_LOW:
1887                 bank->toggle_edge_mode &= ~mask;
1888                 level &= ~mask;
1889                 polarity &= ~mask;
1890                 break;
1891         default:
1892                 irq_gc_unlock(gc);
1893                 spin_unlock_irqrestore(&bank->slock, flags);
1894                 clk_disable(bank->clk);
1895                 return -EINVAL;
1896         }
1897
1898         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1899         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1900
1901         irq_gc_unlock(gc);
1902         spin_unlock_irqrestore(&bank->slock, flags);
1903         clk_disable(bank->clk);
1904
1905         return 0;
1906 }
1907
1908 static void rockchip_irq_suspend(struct irq_data *d)
1909 {
1910         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1911         struct rockchip_pin_bank *bank = gc->private;
1912
1913         clk_enable(bank->clk);
1914         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
1915         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
1916         clk_disable(bank->clk);
1917 }
1918
1919 static void rockchip_irq_resume(struct irq_data *d)
1920 {
1921         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1922         struct rockchip_pin_bank *bank = gc->private;
1923
1924         clk_enable(bank->clk);
1925         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
1926         clk_disable(bank->clk);
1927 }
1928
1929 static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
1930 {
1931         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1932         struct rockchip_pin_bank *bank = gc->private;
1933
1934         clk_enable(bank->clk);
1935         irq_gc_mask_clr_bit(d);
1936 }
1937
1938 void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
1939 {
1940         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1941         struct rockchip_pin_bank *bank = gc->private;
1942
1943         irq_gc_mask_set_bit(d);
1944         clk_disable(bank->clk);
1945 }
1946
1947 static int rockchip_interrupts_register(struct platform_device *pdev,
1948                                                 struct rockchip_pinctrl *info)
1949 {
1950         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1951         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1952         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1953         struct irq_chip_generic *gc;
1954         int ret;
1955         int i, j;
1956
1957         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1958                 if (!bank->valid) {
1959                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1960                                  bank->name);
1961                         continue;
1962                 }
1963
1964                 ret = clk_enable(bank->clk);
1965                 if (ret) {
1966                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
1967                                 bank->name);
1968                         continue;
1969                 }
1970
1971                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1972                                                 &irq_generic_chip_ops, NULL);
1973                 if (!bank->domain) {
1974                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1975                                  bank->name);
1976                         clk_disable(bank->clk);
1977                         continue;
1978                 }
1979
1980                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1981                                          "rockchip_gpio_irq", handle_level_irq,
1982                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1983                 if (ret) {
1984                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1985                                 bank->name);
1986                         irq_domain_remove(bank->domain);
1987                         clk_disable(bank->clk);
1988                         continue;
1989                 }
1990
1991                 /*
1992                  * Linux assumes that all interrupts start out disabled/masked.
1993                  * Our driver only uses the concept of masked and always keeps
1994                  * things enabled, so for us that's all masked and all enabled.
1995                  */
1996                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
1997                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
1998
1999                 gc = irq_get_domain_generic_chip(bank->domain, 0);
2000                 gc->reg_base = bank->reg_base;
2001                 gc->private = bank;
2002                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2003                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2004                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2005                 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
2006                 gc->chip_types[0].chip.irq_unmask =
2007                                                   rockchip_irq_gc_mask_clr_bit;
2008                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2009                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2010                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2011                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2012                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2013
2014                 irq_set_chained_handler_and_data(bank->irq,
2015                                                  rockchip_irq_demux, bank);
2016
2017                 /* map the gpio irqs here, when the clock is still running */
2018                 for (j = 0 ; j < 32 ; j++)
2019                         irq_create_mapping(bank->domain, j);
2020
2021                 clk_disable(bank->clk);
2022         }
2023
2024         return 0;
2025 }
2026
2027 static int rockchip_gpiolib_register(struct platform_device *pdev,
2028                                                 struct rockchip_pinctrl *info)
2029 {
2030         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2031         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2032         struct gpio_chip *gc;
2033         int ret;
2034         int i;
2035
2036         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2037                 if (!bank->valid) {
2038                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2039                                  bank->name);
2040                         continue;
2041                 }
2042
2043                 bank->gpio_chip = rockchip_gpiolib_chip;
2044
2045                 gc = &bank->gpio_chip;
2046                 gc->base = bank->pin_base;
2047                 gc->ngpio = bank->nr_pins;
2048                 gc->dev = &pdev->dev;
2049                 gc->of_node = bank->of_node;
2050                 gc->label = bank->name;
2051
2052                 ret = gpiochip_add(gc);
2053                 if (ret) {
2054                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2055                                                         gc->label, ret);
2056                         goto fail;
2057                 }
2058         }
2059
2060         rockchip_interrupts_register(pdev, info);
2061
2062         return 0;
2063
2064 fail:
2065         for (--i, --bank; i >= 0; --i, --bank) {
2066                 if (!bank->valid)
2067                         continue;
2068                 gpiochip_remove(&bank->gpio_chip);
2069         }
2070         return ret;
2071 }
2072
2073 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2074                                                 struct rockchip_pinctrl *info)
2075 {
2076         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2077         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2078         int i;
2079
2080         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2081                 if (!bank->valid)
2082                         continue;
2083                 gpiochip_remove(&bank->gpio_chip);
2084         }
2085
2086         return 0;
2087 }
2088
2089 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2090                                   struct rockchip_pinctrl *info)
2091 {
2092         struct resource res;
2093         void __iomem *base;
2094
2095         if (of_address_to_resource(bank->of_node, 0, &res)) {
2096                 dev_err(info->dev, "cannot find IO resource for bank\n");
2097                 return -ENOENT;
2098         }
2099
2100         bank->reg_base = devm_ioremap_resource(info->dev, &res);
2101         if (IS_ERR(bank->reg_base))
2102                 return PTR_ERR(bank->reg_base);
2103
2104         /*
2105          * special case, where parts of the pull setting-registers are
2106          * part of the PMU register space
2107          */
2108         if (of_device_is_compatible(bank->of_node,
2109                                     "rockchip,rk3188-gpio-bank0")) {
2110                 struct device_node *node;
2111
2112                 node = of_parse_phandle(bank->of_node->parent,
2113                                         "rockchip,pmu", 0);
2114                 if (!node) {
2115                         if (of_address_to_resource(bank->of_node, 1, &res)) {
2116                                 dev_err(info->dev, "cannot find IO resource for bank\n");
2117                                 return -ENOENT;
2118                         }
2119
2120                         base = devm_ioremap_resource(info->dev, &res);
2121                         if (IS_ERR(base))
2122                                 return PTR_ERR(base);
2123                         rockchip_regmap_config.max_register =
2124                                                     resource_size(&res) - 4;
2125                         rockchip_regmap_config.name =
2126                                             "rockchip,rk3188-gpio-bank0-pull";
2127                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2128                                                     base,
2129                                                     &rockchip_regmap_config);
2130                 }
2131         }
2132
2133         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2134
2135         bank->clk = of_clk_get(bank->of_node, 0);
2136         if (IS_ERR(bank->clk))
2137                 return PTR_ERR(bank->clk);
2138
2139         return clk_prepare(bank->clk);
2140 }
2141
2142 static const struct of_device_id rockchip_pinctrl_dt_match[];
2143
2144 /* retrieve the soc specific data */
2145 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2146                                                 struct rockchip_pinctrl *d,
2147                                                 struct platform_device *pdev)
2148 {
2149         const struct of_device_id *match;
2150         struct device_node *node = pdev->dev.of_node;
2151         struct device_node *np;
2152         struct rockchip_pin_ctrl *ctrl;
2153         struct rockchip_pin_bank *bank;
2154         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2155
2156         match = of_match_node(rockchip_pinctrl_dt_match, node);
2157         ctrl = (struct rockchip_pin_ctrl *)match->data;
2158
2159         for_each_child_of_node(node, np) {
2160                 if (!of_find_property(np, "gpio-controller", NULL))
2161                         continue;
2162
2163                 bank = ctrl->pin_banks;
2164                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2165                         if (!strcmp(bank->name, np->name)) {
2166                                 bank->of_node = np;
2167
2168                                 if (!rockchip_get_bank_data(bank, d))
2169                                         bank->valid = true;
2170
2171                                 break;
2172                         }
2173                 }
2174         }
2175
2176         grf_offs = ctrl->grf_mux_offset;
2177         pmu_offs = ctrl->pmu_mux_offset;
2178         drv_pmu_offs = ctrl->pmu_drv_offset;
2179         drv_grf_offs = ctrl->grf_drv_offset;
2180         bank = ctrl->pin_banks;
2181         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2182                 int bank_pins = 0;
2183
2184                 spin_lock_init(&bank->slock);
2185                 bank->drvdata = d;
2186                 bank->pin_base = ctrl->nr_pins;
2187                 ctrl->nr_pins += bank->nr_pins;
2188
2189                 /* calculate iomux and drv offsets */
2190                 for (j = 0; j < 4; j++) {
2191                         struct rockchip_iomux *iom = &bank->iomux[j];
2192                         struct rockchip_drv *drv = &bank->drv[j];
2193                         int inc;
2194
2195                         if (bank_pins >= bank->nr_pins)
2196                                 break;
2197
2198                         /* preset iomux offset value, set new start value */
2199                         if (iom->offset >= 0) {
2200                                 if (iom->type & IOMUX_SOURCE_PMU)
2201                                         pmu_offs = iom->offset;
2202                                 else
2203                                         grf_offs = iom->offset;
2204                         } else { /* set current iomux offset */
2205                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2206                                                         pmu_offs : grf_offs;
2207                         }
2208
2209                         /* preset drv offset value, set new start value */
2210                         if (drv->offset >= 0) {
2211                                 if (iom->type & IOMUX_SOURCE_PMU)
2212                                         drv_pmu_offs = drv->offset;
2213                                 else
2214                                         drv_grf_offs = drv->offset;
2215                         } else { /* set current drv offset */
2216                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2217                                                 drv_pmu_offs : drv_grf_offs;
2218                         }
2219
2220                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2221                                 i, j, iom->offset, drv->offset);
2222
2223                         /*
2224                          * Increase offset according to iomux width.
2225                          * 4bit iomux'es are spread over two registers.
2226                          */
2227                         inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
2228                         if (iom->type & IOMUX_SOURCE_PMU)
2229                                 pmu_offs += inc;
2230                         else
2231                                 grf_offs += inc;
2232
2233                         /*
2234                          * Increase offset according to drv width.
2235                          * 3bit drive-strenth'es are spread over two registers.
2236                          */
2237                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2238                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2239                                 inc = 8;
2240                         else
2241                                 inc = 4;
2242
2243                         if (iom->type & IOMUX_SOURCE_PMU)
2244                                 drv_pmu_offs += inc;
2245                         else
2246                                 drv_grf_offs += inc;
2247
2248                         bank_pins += 8;
2249                 }
2250         }
2251
2252         return ctrl;
2253 }
2254
2255 #define RK3288_GRF_GPIO6C_IOMUX         0x64
2256 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
2257
2258 static u32 rk3288_grf_gpio6c_iomux;
2259
2260 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2261 {
2262         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2263         int ret = pinctrl_force_sleep(info->pctl_dev);
2264
2265         if (ret)
2266                 return ret;
2267
2268         /*
2269          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2270          * the setting here, and restore it at resume.
2271          */
2272         if (info->ctrl->type == RK3288) {
2273                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2274                                   &rk3288_grf_gpio6c_iomux);
2275                 if (ret) {
2276                         pinctrl_force_default(info->pctl_dev);
2277                         return ret;
2278                 }
2279         }
2280
2281         return 0;
2282 }
2283
2284 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2285 {
2286         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2287         int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2288                                rk3288_grf_gpio6c_iomux |
2289                                GPIO6C6_SEL_WRITE_ENABLE);
2290
2291         if (ret)
2292                 return ret;
2293
2294         return pinctrl_force_default(info->pctl_dev);
2295 }
2296
2297 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2298                          rockchip_pinctrl_resume);
2299
2300 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2301 {
2302         struct rockchip_pinctrl *info;
2303         struct device *dev = &pdev->dev;
2304         struct rockchip_pin_ctrl *ctrl;
2305         struct device_node *np = pdev->dev.of_node, *node;
2306         struct resource *res;
2307         void __iomem *base;
2308         int ret;
2309
2310         if (!dev->of_node) {
2311                 dev_err(dev, "device tree node not found\n");
2312                 return -ENODEV;
2313         }
2314
2315         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2316         if (!info)
2317                 return -ENOMEM;
2318
2319         info->dev = dev;
2320
2321         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2322         if (!ctrl) {
2323                 dev_err(dev, "driver data not available\n");
2324                 return -EINVAL;
2325         }
2326         info->ctrl = ctrl;
2327
2328         node = of_parse_phandle(np, "rockchip,grf", 0);
2329         if (node) {
2330                 info->regmap_base = syscon_node_to_regmap(node);
2331                 if (IS_ERR(info->regmap_base))
2332                         return PTR_ERR(info->regmap_base);
2333         } else {
2334                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2335                 base = devm_ioremap_resource(&pdev->dev, res);
2336                 if (IS_ERR(base))
2337                         return PTR_ERR(base);
2338
2339                 rockchip_regmap_config.max_register = resource_size(res) - 4;
2340                 rockchip_regmap_config.name = "rockchip,pinctrl";
2341                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2342                                                     &rockchip_regmap_config);
2343
2344                 /* to check for the old dt-bindings */
2345                 info->reg_size = resource_size(res);
2346
2347                 /* Honor the old binding, with pull registers as 2nd resource */
2348                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2349                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2350                         base = devm_ioremap_resource(&pdev->dev, res);
2351                         if (IS_ERR(base))
2352                                 return PTR_ERR(base);
2353
2354                         rockchip_regmap_config.max_register =
2355                                                         resource_size(res) - 4;
2356                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2357                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2358                                                     base,
2359                                                     &rockchip_regmap_config);
2360                 }
2361         }
2362
2363         /* try to find the optional reference to the pmu syscon */
2364         node = of_parse_phandle(np, "rockchip,pmu", 0);
2365         if (node) {
2366                 info->regmap_pmu = syscon_node_to_regmap(node);
2367                 if (IS_ERR(info->regmap_pmu))
2368                         return PTR_ERR(info->regmap_pmu);
2369         }
2370
2371         ret = rockchip_gpiolib_register(pdev, info);
2372         if (ret)
2373                 return ret;
2374
2375         ret = rockchip_pinctrl_register(pdev, info);
2376         if (ret) {
2377                 rockchip_gpiolib_unregister(pdev, info);
2378                 return ret;
2379         }
2380
2381         platform_set_drvdata(pdev, info);
2382
2383         return 0;
2384 }
2385
2386 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2387         PIN_BANK(0, 32, "gpio0"),
2388         PIN_BANK(1, 32, "gpio1"),
2389         PIN_BANK(2, 32, "gpio2"),
2390         PIN_BANK(3, 32, "gpio3"),
2391 };
2392
2393 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2394                 .pin_banks              = rk2928_pin_banks,
2395                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2396                 .label                  = "RK2928-GPIO",
2397                 .type                   = RK2928,
2398                 .grf_mux_offset         = 0xa8,
2399                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2400 };
2401
2402 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2403         PIN_BANK(0, 32, "gpio0"),
2404         PIN_BANK(1, 32, "gpio1"),
2405         PIN_BANK(2, 32, "gpio2"),
2406 };
2407
2408 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2409                 .pin_banks              = rk3036_pin_banks,
2410                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
2411                 .label                  = "RK3036-GPIO",
2412                 .type                   = RK2928,
2413                 .grf_mux_offset         = 0xa8,
2414                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2415 };
2416
2417 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2418         PIN_BANK(0, 32, "gpio0"),
2419         PIN_BANK(1, 32, "gpio1"),
2420         PIN_BANK(2, 32, "gpio2"),
2421         PIN_BANK(3, 32, "gpio3"),
2422         PIN_BANK(4, 32, "gpio4"),
2423         PIN_BANK(6, 16, "gpio6"),
2424 };
2425
2426 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2427                 .pin_banks              = rk3066a_pin_banks,
2428                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2429                 .label                  = "RK3066a-GPIO",
2430                 .type                   = RK2928,
2431                 .grf_mux_offset         = 0xa8,
2432                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2433 };
2434
2435 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2436         PIN_BANK(0, 32, "gpio0"),
2437         PIN_BANK(1, 32, "gpio1"),
2438         PIN_BANK(2, 32, "gpio2"),
2439         PIN_BANK(3, 32, "gpio3"),
2440 };
2441
2442 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2443                 .pin_banks      = rk3066b_pin_banks,
2444                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2445                 .label          = "RK3066b-GPIO",
2446                 .type           = RK3066B,
2447                 .grf_mux_offset = 0x60,
2448 };
2449
2450 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2451         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2452         PIN_BANK(1, 32, "gpio1"),
2453         PIN_BANK(2, 32, "gpio2"),
2454         PIN_BANK(3, 32, "gpio3"),
2455 };
2456
2457 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2458                 .pin_banks              = rk3188_pin_banks,
2459                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2460                 .label                  = "RK3188-GPIO",
2461                 .type                   = RK3188,
2462                 .grf_mux_offset         = 0x60,
2463                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2464 };
2465
2466 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2467         PIN_BANK(0, 32, "gpio0"),
2468         PIN_BANK(1, 32, "gpio1"),
2469         PIN_BANK(2, 32, "gpio2"),
2470         PIN_BANK(3, 32, "gpio3"),
2471 };
2472
2473 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2474                 .pin_banks              = rk3228_pin_banks,
2475                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
2476                 .label                  = "RK3228-GPIO",
2477                 .type                   = RK3288,
2478                 .grf_mux_offset         = 0x0,
2479                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
2480                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
2481 };
2482
2483 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2484         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2485                                              IOMUX_SOURCE_PMU,
2486                                              IOMUX_SOURCE_PMU,
2487                                              IOMUX_UNROUTED
2488                             ),
2489         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2490                                              IOMUX_UNROUTED,
2491                                              IOMUX_UNROUTED,
2492                                              0
2493                             ),
2494         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2495         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2496         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2497                                              IOMUX_WIDTH_4BIT,
2498                                              0,
2499                                              0
2500                             ),
2501         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2502                                              0,
2503                                              0,
2504                                              IOMUX_UNROUTED
2505                             ),
2506         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2507         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2508                                              0,
2509                                              IOMUX_WIDTH_4BIT,
2510                                              IOMUX_UNROUTED
2511                             ),
2512         PIN_BANK(8, 16, "gpio8"),
2513 };
2514
2515 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2516                 .pin_banks              = rk3288_pin_banks,
2517                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
2518                 .label                  = "RK3288-GPIO",
2519                 .type                   = RK3288,
2520                 .grf_mux_offset         = 0x0,
2521                 .pmu_mux_offset         = 0x84,
2522                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
2523                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
2524 };
2525
2526 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2527         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2528                                              IOMUX_SOURCE_PMU,
2529                                              IOMUX_SOURCE_PMU,
2530                                              IOMUX_SOURCE_PMU
2531                             ),
2532         PIN_BANK(1, 32, "gpio1"),
2533         PIN_BANK(2, 32, "gpio2"),
2534         PIN_BANK(3, 32, "gpio3"),
2535 };
2536
2537 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2538                 .pin_banks              = rk3368_pin_banks,
2539                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
2540                 .label                  = "RK3368-GPIO",
2541                 .type                   = RK3368,
2542                 .grf_mux_offset         = 0x0,
2543                 .pmu_mux_offset         = 0x0,
2544                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
2545                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
2546 };
2547
2548 static struct rockchip_pin_bank rk3399_pin_banks[] = {
2549         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2550                                         IOMUX_SOURCE_PMU,
2551                                         IOMUX_SOURCE_PMU,
2552                                         IOMUX_SOURCE_PMU,
2553                                         DRV_TYPE_IO_1V8_ONLY,
2554                                         DRV_TYPE_IO_1V8_ONLY,
2555                                         DRV_TYPE_IO_DEFAULT,
2556                                         DRV_TYPE_IO_DEFAULT,
2557                                         0x0,
2558                                         0x8,
2559                                         -1,
2560                                         -1
2561                                         ),
2562         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
2563                                         IOMUX_SOURCE_PMU,
2564                                         IOMUX_SOURCE_PMU,
2565                                         IOMUX_SOURCE_PMU,
2566                                         DRV_TYPE_IO_1V8_OR_3V0,
2567                                         DRV_TYPE_IO_1V8_OR_3V0,
2568                                         DRV_TYPE_IO_1V8_OR_3V0,
2569                                         DRV_TYPE_IO_1V8_OR_3V0,
2570                                         0x20,
2571                                         0x28,
2572                                         0x30,
2573                                         0x38
2574                                         ),
2575         PIN_BANK_DRV_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
2576                            DRV_TYPE_IO_1V8_OR_3V0,
2577                            DRV_TYPE_IO_1V8_ONLY,
2578                            DRV_TYPE_IO_1V8_ONLY
2579                            ),
2580         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
2581                            DRV_TYPE_IO_3V3_ONLY,
2582                            DRV_TYPE_IO_3V3_ONLY,
2583                            DRV_TYPE_IO_1V8_OR_3V0
2584                            ),
2585         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
2586                            DRV_TYPE_IO_1V8_3V0_AUTO,
2587                            DRV_TYPE_IO_1V8_OR_3V0,
2588                            DRV_TYPE_IO_1V8_OR_3V0
2589                            ),
2590 };
2591
2592 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
2593                 .pin_banks              = rk3399_pin_banks,
2594                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
2595                 .label                  = "RK3399-GPIO",
2596                 .type                   = RK3399,
2597                 .grf_mux_offset         = 0xe000,
2598                 .pmu_mux_offset         = 0x0,
2599                 .grf_drv_offset         = 0xe100,
2600                 .pmu_drv_offset         = 0x80,
2601                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
2602                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
2603 };
2604
2605 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2606         { .compatible = "rockchip,rk2928-pinctrl",
2607                 .data = (void *)&rk2928_pin_ctrl },
2608         { .compatible = "rockchip,rk3036-pinctrl",
2609                 .data = (void *)&rk3036_pin_ctrl },
2610         { .compatible = "rockchip,rk3066a-pinctrl",
2611                 .data = (void *)&rk3066a_pin_ctrl },
2612         { .compatible = "rockchip,rk3066b-pinctrl",
2613                 .data = (void *)&rk3066b_pin_ctrl },
2614         { .compatible = "rockchip,rk3188-pinctrl",
2615                 .data = (void *)&rk3188_pin_ctrl },
2616         { .compatible = "rockchip,rk3228-pinctrl",
2617                 .data = (void *)&rk3228_pin_ctrl },
2618         { .compatible = "rockchip,rk3288-pinctrl",
2619                 .data = (void *)&rk3288_pin_ctrl },
2620         { .compatible = "rockchip,rk3368-pinctrl",
2621                 .data = (void *)&rk3368_pin_ctrl },
2622         { .compatible = "rockchip,rk3399-pinctrl",
2623                 .data = (void *)&rk3399_pin_ctrl },
2624         {},
2625 };
2626 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2627
2628 static struct platform_driver rockchip_pinctrl_driver = {
2629         .probe          = rockchip_pinctrl_probe,
2630         .driver = {
2631                 .name   = "rockchip-pinctrl",
2632                 .pm = &rockchip_pinctrl_dev_pm_ops,
2633                 .of_match_table = rockchip_pinctrl_dt_match,
2634         },
2635 };
2636
2637 static int __init rockchip_pinctrl_drv_register(void)
2638 {
2639         return platform_driver_register(&rockchip_pinctrl_driver);
2640 }
2641 postcore_initcall(rockchip_pinctrl_drv_register);
2642
2643 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2644 MODULE_DESCRIPTION("Rockchip pinctrl driver");
2645 MODULE_LICENSE("GPL v2");