drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2016 Rockchip electronic L.T.D
   5  * Author: Luo Wei <lw@rock-chips.com>
   6  *
   7  * Thanks to Heiko Stuebner <heiko@sntech.de>
   8  * With some ideas taken from pinctrl-samsung
   9  *
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as published
  13  * by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/io.h>
  24 #include <linux/bitops.h>
  25 #include <linux/irq.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/gpio.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/pinctrl/machine.h>
  31 #include <linux/pinctrl/pinconf.h>
  32 #include <linux/pinctrl/pinctrl.h>
  33 #include <linux/pinctrl/pinmux.h>
  34 #include <linux/pinctrl/pinconf-generic.h>
  35 #include <linux/irqchip/chained_irq.h>
  36 #include <linux/clk.h>
  37 #include <linux/syscore_ops.h>
  38 #include <linux/highmem.h>
  39 #include <dt-bindings/pinctrl/rockchip.h>
  40 #include <linux/of.h>
  41 #include <linux/of_device.h>
  42 #include <linux/pinctrl/consumer.h>
  43 #include <linux/slab.h>
  44 #include <linux/delay.h>
  45 #include <linux/rockchip/grf.h>
  46 #include <linux/of_gpio.h>
  47
  48
  49 #ifdef CONFIG_DEBUG_FS
  50 #include <linux/debugfs.h>
  51 #endif
  52
  53
  54 #include "core.h"
  55 #include "pinconf.h"
  56
  57
  58 #if 1
  59 #define DBG_PINCTRL(x...) do { if((((atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1)) && (atomic_read(&info->pin_debug_flag) == (pin + 1))) || ((atomic_read(&info->pin_debug_flag) == 0) && (atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1)))) && bank && info) printk(x); } while (0)
  60 #else
  61 #define DBG_PINCTRL(x...)
  62 #endif
  63
  64
  65 /* GPIO control registers */
  66 #define GPIO_SWPORT_DR          0x00
  67 #define GPIO_SWPORT_DDR         0x04
  68 #define GPIO_INTEN              0x30
  69 #define GPIO_INTMASK            0x34
  70 #define GPIO_INTTYPE_LEVEL      0x38
  71 #define GPIO_INT_POLARITY       0x3c
  72 #define GPIO_INT_STATUS         0x40
  73 #define GPIO_INT_RAWSTATUS      0x44
  74 #define GPIO_DEBOUNCE           0x48
  75 #define GPIO_PORTS_EOI          0x4c
  76 #define GPIO_EXT_PORT           0x50
  77 #define GPIO_LS_SYNC            0x60
  78
  79 enum rockchip_pinctrl_type {
  80         RK2928,
  81         RK3066B,
  82         RK3188,
  83         RK3288,
  84         RK3036,
  85         RK312X,
  86 };
  87
  88 enum rockchip_pin_bank_type {
  89         COMMON_BANK,
  90         RK3188_BANK0,
  91         RK3288_BANK0,
  92 };
  93
  94 /**
  95  * @reg_base: register base of the gpio bank
  96  * @reg_pull: optional separate register for additional pull settings
  97  * @clk: clock of the gpio bank
  98  * @irq: interrupt of the gpio bank
  99  * @pin_base: first pin number
 100  * @nr_pins: number of pins in this bank
 101  * @name: name of the bank
 102  * @bank_num: number of the bank, to account for holes
 103  * @valid: are all necessary informations present
 104  * @of_node: dt node of this bank
 105  * @drvdata: common pinctrl basedata
 106  * @domain: irqdomain of the gpio bank
 107  * @gpio_chip: gpiolib chip
 108  * @grange: gpio range
 109  * @slock: spinlock for the gpio bank
 110  */
 111 struct rockchip_pin_bank {
 112         void __iomem                    *reg_base;
 113         void __iomem                    *reg_mux_bank0;
 114         void __iomem                    *reg_pull_bank0;
 115         void __iomem                    *reg_drv_bank0;
 116         struct clk                      *clk;
 117         int                             irq;
 118         u32                             pin_base;
 119         u8                              nr_pins;
 120         char                            *name;
 121         u8                              bank_num;
 122         enum rockchip_pin_bank_type     bank_type;
 123         bool                            valid;
 124         struct device_node              *of_node;
 125         struct rockchip_pinctrl         *drvdata;
 126         struct irq_domain               *domain;
 127         struct gpio_chip                gpio_chip;
 128         struct pinctrl_gpio_range       grange;
 129         spinlock_t                      slock;
 130         u32                             toggle_edge_mode;
 131         u32                             suspend_wakeup;
 132         u32                             saved_wakeup;
 133 };
 134
 135 #define PIN_BANK(id, pins, label)                       \
 136         {                                               \
 137                 .bank_num       = id,                   \
 138                 .nr_pins        = pins,                 \
 139                 .name           = label,                \
 140         }
 141
 142 /**
 143  */
 144 struct rockchip_pin_ctrl {
 145         struct rockchip_pin_bank        *pin_banks;
 146         u32                             nr_banks;
 147         u32                             nr_pins;
 148         char                            *label;
 149         enum rockchip_pinctrl_type      type;
 150         int                             mux_offset;
 151         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
 152                                  void __iomem **reg, u8 *bit);
 153         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
 154                                  void __iomem **reg, u8 *bit);
 155 };
 156
 157 struct rockchip_pin_config {
 158         unsigned int            func;
 159         unsigned long           *configs;
 160         unsigned int            nconfigs;
 161 };
 162
 163 /**
 164  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 165  * @name: name of the pin group, used to lookup the group.
 166  * @pins: the pins included in this group.
 167  * @npins: number of pins included in this group.
 168  * @func: the mux function number to be programmed when selected.
 169  * @configs: the config values to be set for each pin
 170  * @nconfigs: number of configs for each pin
 171  */
 172 struct rockchip_pin_group {
 173         const char                      *name;
 174         const char                      *func_name;
 175         unsigned int                    npins;
 176         unsigned int                    *pins;
 177         struct rockchip_pin_config      *data;
 178         unsigned long   gconfigs;
 179 };
 180
 181 /**
 182  * struct rockchip_pmx_func: represent a pin function.
 183  * @name: name of the pin function, used to lookup the function.
 184  * @groups: one or more names of pin groups that provide this function.
 185  * @num_groups: number of groups included in @groups.
 186  */
 187 struct rockchip_pmx_func {
 188         const char              *name;
 189         const char              **groups;
 190         u8                      ngroups;
 191 };
 192
 193 struct gpio_init_config {
 194         struct gpio *gpios;
 195         int nr_gpios;
 196 };
 197
 198
 199 struct rockchip_pinctrl {
 200         void __iomem                    *reg_base;
 201
 202         void __iomem                    *reg_mux;
 203         void __iomem                    *reg_pull;
 204         void __iomem                    *reg_drv;
 205
 206         struct device                   *dev;
 207         struct rockchip_pin_ctrl        *ctrl;
 208         struct pinctrl_desc             pctl;
 209         struct pinctrl_dev              *pctl_dev;
 210         struct rockchip_pin_group       *groups;
 211         unsigned int                    ngroups;
 212         struct rockchip_pmx_func        *functions;
 213         unsigned int                    nfunctions;
 214
 215         atomic_t                        bank_debug_flag;
 216         atomic_t                        pin_debug_flag;
 217 #ifdef CONFIG_DEBUG_FS
 218         struct dentry *debugfs;
 219 #endif
 220         struct gpio_init_config         *config;
 221 };
 222
 223 struct iomux_mode{
 224         unsigned int mode:4,
 225                      off:4,
 226                      goff:4,
 227                      bank:4,
 228                      reserve:16;
 229 };
 230
 231 struct union_mode{
 232         union{
 233                 struct iomux_mode mux;
 234                 unsigned int mode;
 235         };
 236 };
 237
 238 struct func_to_reg_offset {
 239         unsigned int reg_type;
 240         const char *vol_name;
 241         const char *func_name;
 242         const char *group_name;
 243         unsigned int reg_offset;
 244         unsigned int bit_offset;
 245         unsigned int bit_mask;
 246 };
 247
 248 #define FUNC_GROUP_TO_REG_OFFSET(type, vol, func, group, reg, bit, mask)        \
 249         {                                               \
 250                 .reg_type       = type,         \
 251                 .vol_name       = vol,          \
 252                 .func_name      = func,         \
 253                 .group_name     = group,        \
 254                 .reg_offset     = reg,          \
 255                 .bit_offset     = bit,          \
 256                 .bit_mask       = mask,         \
 257         }
 258
 259
 260 static struct rockchip_pinctrl *g_info;
 261
 262
 263 #ifdef CONFIG_DEBUG_FS
 264 #define PINCTRL_REGS_BUFSIZE    (1024<<4)
 265 static ssize_t pinctrl_write_proc_data(struct file *file, const char __user *buffer,
 266                            size_t count, loff_t *data)
 267 {
 268         struct rockchip_pinctrl *info;
 269         char *buf;
 270         ssize_t ret;
 271         int bank_value, pin_value;
 272
 273         info = file->private_data;
 274
 275         buf = kzalloc(32, GFP_KERNEL);
 276         if (!buf)
 277         return 0;
 278
 279         ret = copy_from_user(buf, buffer, count);
 280         if (ret)
 281         {
 282                 return ret;
 283         }
 284
 285         if((strstr(buf, "debug") != NULL) || (strstr(buf, "DEBUG") != NULL))
 286         {
 287                 if(strstr(buf, "-") != NULL)
 288                 {
 289                         if(strstr(buf, "debug") != NULL)
 290                         sscanf(buf, "debug%d-%d", &bank_value, &pin_value);
 291                         else if(strstr(buf, "DEBUG") != NULL)
 292                         sscanf(buf, "DEBUG%d-%d", &bank_value, &pin_value);
 293
 294                         if((bank_value < 0) || (pin_value < 0))
 295                         {
 296                                 printk("%s:error:bank %d or pin %d is out of range %d-%d\n",__func__, bank_value, pin_value, info->ctrl->nr_banks-1, info->ctrl->nr_pins);
 297                         }
 298                         else
 299                         {
 300                                 atomic_set(&info->bank_debug_flag, bank_value+1);
 301                                 atomic_set(&info->pin_debug_flag, pin_value+1);
 302                                 printk("%s:open debug for bank%d-%d\n",__func__,bank_value, pin_value);
 303                         }
 304                 }
 305                 else
 306                 {
 307                         if(strstr(buf, "debug") != NULL)
 308                         sscanf(buf, "debug%d", &bank_value);
 309                         else if(strstr(buf, "DEBUG") != NULL)
 310                         sscanf(buf, "DEBUG%d", &bank_value);
 311
 312                         if((bank_value < 0))
 313                         {
 314                                 printk("%s:error:bank%d is out of range %d\n",__func__, bank_value,info->ctrl->nr_banks-1);
 315                         }
 316                         else
 317                         {
 318                                 atomic_set(&info->bank_debug_flag, bank_value+1);
 319                                 atomic_set(&info->pin_debug_flag, 0);
 320                                 printk("%s:open debug for bank%d\n",__func__,bank_value);
 321                         }
 322                 }
 323
 324         }
 325         else if((strstr(buf, "stop") != NULL) || (strstr(buf, "STOP") != NULL))
 326         {
 327                 atomic_set(&info->bank_debug_flag, 0);
 328                 atomic_set(&info->pin_debug_flag, 0);
 329                 printk("%s:close debug\n",__func__);
 330         }
 331
 332         kfree(buf);
 333
 334         return count;
 335 }
 336
 337 static ssize_t  pinctrl_show_regs(struct file *file, char __user *user_buf,
 338                                 size_t count, loff_t *ppos)
 339 {
 340         struct rockchip_pinctrl *info;
 341         struct rockchip_pin_ctrl *ctrl;
 342         struct rockchip_pin_bank *bank, *bank0;
 343         char *buf;
 344         u32 len = 0;
 345         ssize_t ret;
 346         int i = 0, n = 0;
 347         int value = 0;
 348
 349         info = file->private_data;
 350         ctrl = info->ctrl;
 351         bank = ctrl->pin_banks;
 352         bank0 = bank;
 353
 354         buf = kzalloc(PINCTRL_REGS_BUFSIZE, GFP_KERNEL);
 355         if (!buf)
 356                 return 0;
 357
 358         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 359                         "%s registers:\n",ctrl->label);
 360         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 361                         "=================================\n");
 362
 363         for(n=0; n<ctrl->nr_banks-1; n++)
 364         {
 365                 for(i=GPIO_SWPORT_DR; i<GPIO_LS_SYNC; i=i+4)
 366                 {
 367                         value = readl_relaxed(bank->reg_base + i);
 368                         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "bank%d reg[0x%p+0x%x]=0x%08x\n",bank->bank_num, (int *)bank->reg_base, i, value);
 369                 }
 370                 bank++;
 371         }
 372
 373         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 374                         "=================================\n\n");
 375
 376         if(bank0 && bank0->reg_mux_bank0 && bank0->reg_pull_bank0 && bank0->reg_drv_bank0)
 377         {
 378                 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 379                                 "BANK0 GRF registers:\n");
 380                 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 381                                 "=================================\n");
 382
 383                 for(i=0; i<0x0c; i=i+4)
 384                 {
 385                         value = readl_relaxed(bank0->reg_mux_bank0 + i);
 386                         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "MUX_BANK0[0x%p+0x%x]=0x%08x\n",(int *)bank0->reg_mux_bank0, i, value);
 387                 }
 388
 389                 for(i=0; i<0x0c; i=i+4)
 390                 {
 391                         value = readl_relaxed(bank0->reg_pull_bank0 + i);
 392                         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "PULL_BANK0[0x%p+0x%x]=0x%08x\n",(int *)bank0->reg_pull_bank0, i, value);
 393                 }
 394
 395                 for(i=0; i<0x0c; i=i+4)
 396                 {
 397                         value = readl_relaxed(bank0->reg_drv_bank0 + i);
 398                         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "DRV_BANK0[0x%p+0x%x]=0x%08x\n",(int *)bank0->reg_drv_bank0, i, value);
 399                 }
 400
 401                 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 402                                 "=================================\n\n");
 403         }
 404
 405
 406         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 407                         "rockchip pinctrl GRF registers:\n");
 408         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 409                         "=================================\n");
 410
 411
 412         for(i=0; i<0x400; i=i+4)
 413         {
 414                 value = readl_relaxed(info->reg_base + i);
 415                 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "GRF[0x%p+0x%x]=0x%08x\n",(int *)info->reg_base, i, value);
 416         }
 417
 418         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 419                         "=================================\n\n");
 420
 421         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 422         kfree(buf);
 423
 424         return ret;
 425 }
 426
 427 static const struct file_operations pinctrl_regs_ops = {
 428         .owner          = THIS_MODULE,
 429         .open           = simple_open,
 430         .read           = pinctrl_show_regs,
 431         .write          = pinctrl_write_proc_data,
 432         .llseek         = default_llseek,
 433 };
 434
 435 static int pinctrl_debugfs_init(struct rockchip_pinctrl *info)
 436 {
 437         info->debugfs = debugfs_create_dir("rockchip_pinctrl", NULL);
 438         if (!info->debugfs)
 439                 return -ENOMEM;
 440
 441         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 442                 info->debugfs, (void *)info, &pinctrl_regs_ops);
 443         return 0;
 444 }
 445
 446 #if 0
 447 static void pinctrl_debugfs_remove(struct rockchip_pinctrl*info)
 448 {
 449         if (info->debugfs)
 450                 debugfs_remove_recursive(info->debugfs);
 451 }
 452 #endif
 453
 454 #else
 455 static inline int pinctrl_debugfs_init(struct rockchip_pinctrl*info)
 456 {
 457         return 0;
 458 }
 459
 460 #if 0
 461 static inline void pinctrl_debugfs_remove(struct rockchip_pinctrl*info)
 462 {
 463 }
 464 #endif
 465 #endif /* CONFIG_DEBUG_FS */
 466
 467
 468 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 469 {
 470         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 471 }
 472
 473 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 474                                         const struct rockchip_pinctrl *info,
 475                                         const char *name)
 476 {
 477         int i;
 478
 479         for (i = 0; i < info->ngroups; i++) {
 480                 if (!strcmp(info->groups[i].name, name))
 481                         return &info->groups[i];
 482         }
 483
 484         return NULL;
 485 }
 486
 487 /*
 488  * given a pin number that is local to a pin controller, find out the pin bank
 489  * and the register base of the pin bank.
 490  */
 491 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 492                                                                 unsigned pin)
 493 {
 494         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 495
 496         while (pin >= (b->pin_base + b->nr_pins))
 497                 b++;
 498
 499         return b;
 500 }
 501
 502 static struct rockchip_pin_bank *bank_num_to_bank(
 503                                         struct rockchip_pinctrl *info,
 504                                         unsigned num)
 505 {
 506         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 507         int i;
 508
 509         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 510                 if (b->bank_num == num)
 511                         return b;
 512         }
 513
 514         return ERR_PTR(-EINVAL);
 515 }
 516
 517 /*
 518  * Pinctrl_ops handling
 519  */
 520
 521 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 522 {
 523         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 524
 525         return info->ngroups;
 526 }
 527
 528 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 529                                                         unsigned selector)
 530 {
 531         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 532
 533         return info->groups[selector].name;
 534 }
 535
 536 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 537                                       unsigned selector, const unsigned **pins,
 538                                       unsigned *npins)
 539 {
 540         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 541
 542         if (selector >= info->ngroups)
 543                 return -EINVAL;
 544
 545         *pins = info->groups[selector].pins;
 546         *npins = info->groups[selector].npins;
 547
 548         return 0;
 549 }
 550
 551 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 552                                  struct device_node *np,
 553                                  struct pinctrl_map **map, unsigned *num_maps)
 554 {
 555         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 556         const struct rockchip_pin_group *grp;
 557         struct pinctrl_map *new_map;
 558         struct device_node *parent;
 559         int map_num = 1;
 560         int i;
 561
 562         /*
 563          * first find the group of this node and check if we need to create
 564          * config maps for pins
 565          */
 566         grp = pinctrl_name_to_group(info, np->name);
 567         if (!grp) {
 568                 dev_err(info->dev, "unable to find group for node %s\n",
 569                         np->name);
 570                 return -EINVAL;
 571         }
 572
 573         map_num += grp->npins;
 574         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 575                                                                 GFP_KERNEL);
 576         if (!new_map)
 577                 return -ENOMEM;
 578
 579         *map = new_map;
 580         *num_maps = map_num;
 581
 582         /* create mux map */
 583         parent = of_get_parent(np);
 584         if (!parent) {
 585                 devm_kfree(pctldev->dev, new_map);
 586                 return -EINVAL;
 587         }
 588         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 589         new_map[0].data.mux.function = parent->name;
 590         new_map[0].data.mux.group = np->name;
 591         of_node_put(parent);
 592
 593         /* create config map */
 594         new_map++;
 595         for (i = 0; i < grp->npins; i++) {
 596                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 597                 new_map[i].data.configs.group_or_pin = grp->name;
 598                                 //pin_get_name(pctldev, grp->pins[i]);
 599                 new_map[i].data.configs.configs = grp->data[i].configs;
 600                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 601         }
 602
 603         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 604                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 605
 606         return 0;
 607 }
 608
 609 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 610                                     struct pinctrl_map *map, unsigned num_maps)
 611 {
 612 }
 613
 614 static const struct pinctrl_ops rockchip_pctrl_ops = {
 615         .get_groups_count       = rockchip_get_groups_count,
 616         .get_group_name         = rockchip_get_group_name,
 617         .get_group_pins         = rockchip_get_group_pins,
 618         .dt_node_to_map         = rockchip_dt_node_to_map,
 619         .dt_free_map            = rockchip_dt_free_map,
 620 };
 621
 622
 623 #define RK3288_GRF_GPIO1A_IOMUX         0x0000
 624 #define RK3288_GRF_GPIO5A_IOMUX         0x004C
 625
 626 static int rk32_iomux_bit_op(struct rockchip_pin_bank *bank, int pin, int mux, void __iomem *reg, int bits)
 627 {
 628         u32 data = 0,result;
 629         u8 bit;
 630         unsigned long flags;
 631         struct rockchip_pinctrl *info = bank->drvdata;
 632
 633         if(bits == 2)
 634         {
 635                 reg += (pin / 8) * 4;
 636                 bit = (pin % 8) * 2;
 637
 638                 spin_lock_irqsave(&bank->slock, flags);
 639                 if(bank->bank_num == 0)
 640                 {
 641                         data = readl_relaxed(reg);
 642                         data &= ~(3<<bit);
 643                         data |= (mux & 3) << bit;
 644                         writel(data, reg);
 645                 }
 646                 else
 647                 {
 648                         data = (3 << (bit + 16));
 649                         data |= (mux & 3) << bit;
 650                         writel(data, reg);
 651                 }
 652
 653                 spin_unlock_irqrestore(&bank->slock, flags);
 654
 655         }
 656         else if(bits == 4)
 657         {
 658                 reg += (pin / 4) * 4;
 659                 bit = (pin % 4) * 4;
 660
 661                 spin_lock_irqsave(&bank->slock, flags);
 662                 if(bank->bank_num == 0)
 663                 {
 664                         data = readl_relaxed(reg);
 665                         data &= ~(0x0f<<bit);
 666                         data |= (mux & 0x0f) << bit;
 667                         writel(data, reg);
 668                 }
 669                 else
 670                 {
 671                         data = (0x0f << (bit + 16));
 672                         data |= (mux & 0x0f) << bit;
 673                         writel(data, reg);
 674                 }
 675
 676                 spin_unlock_irqrestore(&bank->slock, flags);
 677         }
 678         else
 679         {
 680                 printk("%s:unknow bits %d\n",__func__, bits);
 681         }
 682
 683
 684         result = readl_relaxed(reg);
 685         if(bank->bank_num == 0)
 686         DBG_PINCTRL("%s:GPIO%d-%d,reg=0x%x,data=0x%x,result=0x%x\n",__func__, bank->bank_num, pin, reg - bank->reg_mux_bank0, data, result);
 687         else
 688         DBG_PINCTRL("%s:GPIO%d-%d,reg=0x%x,data=0x%x,result=0x%x\n",__func__, bank->bank_num, pin, reg - info->reg_base, data, result);
 689
 690         return 0;
 691
 692 }
 693
 694
 695 static int rockchip_set_rk32_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 696 {
 697         struct rockchip_pinctrl *info = bank->drvdata;
 698         void __iomem *reg = info->reg_mux;
 699         struct union_mode m;
 700         u8 bits = 0;
 701
 702         m.mode = mux;
 703
 704         if((m.mux.bank != bank->bank_num))
 705         {
 706                 printk("%s:error:mux_bank(%d) != gpio_bank(%d)\n",__func__, m.mux.bank, bank->bank_num);
 707                 return 0;
 708         }
 709
 710         switch(bank->bank_num)
 711         {
 712                 case 0:
 713                 //pmu
 714                 reg = bank->reg_mux_bank0;
 715                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
 716                 {
 717                         bits = 2;
 718                 }
 719                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 720                 break;
 721
 722                 case 1:
 723                 reg += RK3288_GRF_GPIO1A_IOMUX;
 724                 if((m.mux.goff == 0x0d))
 725                 {
 726                         bits = 2;
 727                 }
 728                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 729                 break;
 730
 731                 case 2:
 732                 reg += RK3288_GRF_GPIO2A_IOMUX;
 733                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
 734                 {
 735                         bits = 2;
 736                 }
 737                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 738                 break;
 739
 740                 case 3:
 741                 reg += RK3288_GRF_GPIO3A_IOMUX;
 742                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
 743                 {
 744                         bits = 2;
 745                 }
 746                 else if(m.mux.goff == 0x0d)
 747                 {
 748                         reg -= 3*4;
 749                         bits = 4;
 750                 }
 751
 752                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 753                 break;
 754
 755                 case 4:
 756                 reg += RK3288_GRF_GPIO4AL_IOMUX;
 757                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b))
 758                 {
 759                         bits = 4;
 760                 }
 761                 else if((m.mux.goff == 0x0c) || (m.mux.goff == 0x0d))
 762                 {
 763                         reg += 2*4;
 764                         bits = 2;
 765                 }
 766
 767                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 768
 769                 break;
 770
 771                 case 5:
 772                 reg += RK3288_GRF_GPIO5A_IOMUX;
 773                 if((m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
 774                 {
 775                         bits = 2;
 776                 }
 777
 778                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 779
 780                 break;
 781
 782                 case 6:
 783                 reg += RK3288_GRF_GPIO6A_IOMUX;
 784                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
 785                 {
 786                         bits = 2;
 787                 }
 788
 789                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 790                 break;
 791
 792                 case 7:
 793                 reg += RK3288_GRF_GPIO7A_IOMUX;
 794                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b))
 795                 {
 796                         bits = 2;
 797                 }
 798                 else if((m.mux.goff == 0x0c))
 799                 {
 800                         reg -= 2*4;
 801                         bits = 4;
 802                 }
 803
 804                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 805                 break;
 806
 807                 case 8:
 808                 reg += RK3288_GRF_GPIO8A_IOMUX;
 809                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b))
 810                 {
 811                         bits = 2;
 812                 }
 813
 814                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 815                 break;
 816
 817                 default:
 818                 printk("%s:unknow bank num %d\n", __func__, bank->bank_num);
 819                 break;
 820
 821         }
 822
 823         return 0;
 824
 825 }
 826
 827
 828
 829 /*
 830  * Set a new mux function for a pin.
 831  *
 832  * The register is divided into the upper and lower 16 bit. When changing
 833  * a value, the previous register value is not read and changed. Instead
 834  * it seems the changed bits are marked in the upper 16 bit, while the
 835  * changed value gets set in the same offset in the lower 16 bit.
 836  * All pin settings seem to be 2 bit wide in both the upper and lower
 837  * parts.
 838  * @bank: pin bank to change
 839  * @pin: pin to change
 840  * @mux: new mux function to set
 841  */
 842 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 843 {
 844         struct rockchip_pinctrl *info = bank->drvdata;
 845         void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 846         unsigned long flags;
 847         u8 bit;
 848         u32 data;
 849         struct union_mode m;
 850
 851         /* GPIO0_C */
 852         /*GPIO0_C0 = 0x0c00, NAND_D8, */
 853         /*GPIO0_C1 = 0x0c10, NAND_D9, */
 854
 855         if(bank->bank_num == 15)
 856         {
 857                 printk("%s:warning ignore bank num %d\n",__func__, bank->bank_num);
 858                 return ;
 859         }
 860
 861         if(info->ctrl->type == RK3288)
 862         {
 863                 rockchip_set_rk32_mux(bank, pin, mux);
 864                 return;
 865         }
 866
 867         m.mode = mux;
 868
 869         if((m.mux.bank != bank->bank_num) || (((m.mux.goff - 0x0A) * 8 + m.mux.off ) != pin))
 870         {
 871                 printk("%s:error:mux_bank(%d) != gpio_bank(%d), mux_offset(%d) != gpio_offset(%d)\n",__func__,
 872                 m.mux.bank, bank->bank_num, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), pin);
 873                 return;
 874         }
 875
 876         if((info->ctrl->type == RK312X) && (bank->bank_num == 2) && (pin >= 20) && (pin <= 24))
 877         {
 878                 /*RK321X GPIO2C_IOMUX2 and GPIO2D_IOMUX are special */
 879                 if((pin >= 20) && (pin <= 23))
 880                 {
 881                         reg -= info->ctrl->mux_offset;
 882                         reg += 0xe8;
 883                         bit = (pin % 4) * 4;
 884                 }
 885                 else
 886                 {
 887                         reg -= info->ctrl->mux_offset;
 888                         reg += 0xd4;
 889                         bit = 12;
 890                 }
 891                 spin_lock_irqsave(&bank->slock, flags);
 892
 893                 data = (0x0f << (bit + 16));
 894                 data |= (mux & 0x0f) << bit;
 895                 writel(data, reg);
 896
 897                 spin_unlock_irqrestore(&bank->slock, flags);
 898
 899         }
 900
 901         else
 902         {
 903                 /* get basic quadrupel of mux registers and the correct reg inside */
 904                 reg += bank->bank_num * 0x10;
 905                 reg += (pin / 8) * 4;
 906                 bit = (pin % 8) * 2;
 907
 908                 spin_lock_irqsave(&bank->slock, flags);
 909
 910                 data = (3 << (bit + 16));
 911                 data |= (mux & 3) << bit;
 912                 writel(data, reg);
 913
 914                 spin_unlock_irqrestore(&bank->slock, flags);
 915         }
 916
 917         DBG_PINCTRL("%s:setting GPIO%d-%d to mux:0x%x\n", __func__, m.mux.bank, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), mux);
 918
 919         //DBG_PINCTRL("%s:setting mux of GPIO%d-%d to %d\n", __func__, bank->bank_num, pin, mux&0x3);
 920 }
 921
 922
 923 /*
 924  * Pinmux_ops handling
 925  */
 926
 927 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 928 {
 929         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 930
 931         return info->nfunctions;
 932 }
 933
 934 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 935                                           unsigned selector)
 936 {
 937         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 938
 939         return info->functions[selector].name;
 940 }
 941
 942 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 943                                 unsigned selector, const char * const **groups,
 944                                 unsigned * const num_groups)
 945 {
 946         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 947
 948         *groups = info->functions[selector].groups;
 949         *num_groups = info->functions[selector].ngroups;
 950
 951         return 0;
 952 }
 953
 954 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 955                                                             unsigned group)
 956 {
 957         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 958         const unsigned int *pins = info->groups[group].pins;
 959         const struct rockchip_pin_config *data = info->groups[group].data;
 960         struct rockchip_pin_bank *bank;
 961         int cnt;
 962         int pin;
 963
 964         /*
 965          * for each pin in the pin group selected, program the correspoding pin
 966          * pin function number in the config register.
 967          */
 968         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 969                 bank = pin_to_bank(info, pins[cnt]);
 970                 pin = pins[cnt];
 971                 DBG_PINCTRL("%s:enable function %s group %s\n",
 972                 __func__, info->functions[selector].name, info->groups[group].name);
 973                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 974                                  data[cnt].func);
 975         }
 976
 977         return 0;
 978 }
 979
 980 #if 0
 981 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 982                                         unsigned selector, unsigned group)
 983 {
 984         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 985         const unsigned int *pins = info->groups[group].pins;
 986         const struct rockchip_pin_config *data = info->groups[group].data;
 987         struct rockchip_pin_bank *bank;
 988         int cnt;
 989         int pin;
 990
 991         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 992                 bank = pin_to_bank(info, pins[cnt]);
 993                 pin = pins[cnt];
 994                 DBG_PINCTRL("%s:disable function %s group %s\n",
 995                 __func__, info->functions[selector].name, info->groups[group].name);
 996                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, FUNC_TO_GPIO(data[cnt].func));
 997         }
 998 }
 999 #endif
1000
1001 /*
1002  * The calls to gpio_direction_output() and gpio_direction_input()
1003  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1004  * function called from the gpiolib interface).
1005  */
1006 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1007                                               struct pinctrl_gpio_range *range,
1008                                               unsigned offset, bool input)
1009 {
1010         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1011         struct rockchip_pin_bank *bank;
1012         struct gpio_chip *chip;
1013         int pin;
1014         u32 data, result;
1015         u32 mux;
1016
1017         chip = range->gc;
1018         bank = gc_to_pin_bank(chip);
1019         pin = offset - chip->base;
1020
1021         mux = (bank->bank_num << 12) | (((pin / 8) + 0x0A) << 8) | ((pin % 8)<< 4) | RK_FUNC_GPIO;
1022
1023         rockchip_set_mux(bank, pin, mux);
1024
1025         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1026         /* set bit to 1 for output, 0 for input */
1027         if (!input)
1028                 data |= BIT(pin);
1029         else
1030                 data &= ~BIT(pin);
1031         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1032
1033         result = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1034
1035         DBG_PINCTRL("%s:gpio_direction for pin %u as %s-%d to %s,data=0x%x,result=0x%x\n",
1036                          __func__, offset, range->name, pin, input ? "input" : "output", data, result);
1037         return 0;
1038 }
1039
1040 static const struct pinmux_ops rockchip_pmx_ops = {
1041         .get_functions_count    = rockchip_pmx_get_funcs_count,
1042         .get_function_name      = rockchip_pmx_get_func_name,
1043         .get_function_groups    = rockchip_pmx_get_groups,
1044         .enable                 = rockchip_pmx_enable,
1045         //.disable              = rockchip_pmx_disable,
1046         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
1047 };
1048
1049
1050
1051 /*
1052  * Hardware access
1053  */
1054
1055 static struct func_to_reg_offset rk3188_func_to_drv_reg_offset[] =
1056 {
1057         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL",  "reserve" ,"NULL", RK3188_GRF_IO_CON0, 0 ,3),
1058         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_flash" ,"NULL", RK3188_GRF_IO_CON0, 2, 3),
1059         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_flash" ,"NULL", RK3188_GRF_IO_CON0, 4 ,3),
1060         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_d" ,"NULL", RK3188_GRF_IO_CON0, 6 ,3),
1061         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio1_uart0" ,"NULL", RK3188_GRF_IO_CON0, 8 ,3),
1062         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_uart1" ,"NULL", RK3188_GRF_IO_CON0, 10 ,3),
1063         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_spi0" ,"NULL", RK3188_GRF_IO_CON0, 10 ,3),
1064         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "gpio1_uart2" ,"NULL", RK3188_GRF_IO_CON0, 12 ,3),
1065         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio1_uart3" ,"NULL", RK3188_GRF_IO_CON0, 14 ,3),
1066         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio1_spi1" ,"NULL", RK3188_GRF_IO_CON0, 14 ,3),
1067         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio1_gps" ,"NULL", RK3188_GRF_IO_CON0, 14 ,3),
1068
1069         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2s0" ,"NULL", RK3188_GRF_IO_CON1, 0 ,3),
1070         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2s0" ,"NULL", RK3188_GRF_IO_CON1, 2 ,3),
1071         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_c" ,"NULL", RK3188_GRF_IO_CON1, 4 ,3),
1072         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c0" ,"NULL", RK3188_GRF_IO_CON1, 6 ,3),
1073         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c1" ,"NULL", RK3188_GRF_IO_CON1, 8 ,3),
1074         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c2" ,"NULL", RK3188_GRF_IO_CON1, 10 ,3),
1075         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2c4" ,"NULL", RK3188_GRF_IO_CON1, 12 ,3),
1076         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_lcdc1" ,"NULL", RK3188_GRF_IO_CON1, 14 ,3),
1077
1078         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_lcdc1" ,"NULL", RK3188_GRF_IO_CON2, 0 ,3),
1079         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_smc" ,"NULL", RK3188_GRF_IO_CON2, 2 ,3),
1080         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "reserve" ,"NULL", RK3188_GRF_IO_CON2, 4 ,3),
1081         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_sdmmc" ,"NULL", RK3188_GRF_IO_CON2, 6 ,3),
1082         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_rmii" ,"NULL", RK3188_GRF_IO_CON2, 6 ,3),
1083         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_sdmmc" ,"NULL", RK3188_GRF_IO_CON2, 8 ,3),
1084         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_rmii" ,"NULL", RK3188_GRF_IO_CON2, 8 ,3),
1085         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_b" ,"NULL", RK3188_GRF_IO_CON2, 10 ,3),
1086         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_i2c3" ,"NULL", RK3188_GRF_IO_CON2, 10 ,3),
1087         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_cif" ,"NULL", RK3188_GRF_IO_CON2, 12 ,3),
1088         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_cif" ,"NULL", RK3188_GRF_IO_CON2, 14 ,3),
1089
1090         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_sdio" ,"NULL", RK3188_GRF_IO_CON3, 0 ,3),
1091         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_sdio" ,"NULL", RK3188_GRF_IO_CON3, 2 ,3),
1092         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_pwm" ,"NULL", RK3188_GRF_IO_CON3, 4 ,3),
1093         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_d" ,"NULL", RK3188_GRF_IO_CON3, 6 ,3),
1094         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "flash" ,"NULL", RK3188_GRF_IO_CON3, 8 ,3),
1095         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "flash" ,"NULL", RK3188_GRF_IO_CON3, 10 ,3),
1096         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "cif" ,"NULL", RK3188_GRF_IO_CON3, 12 ,3),
1097         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc0-vcc", "lcdc0" ,"NULL", RK3188_GRF_IO_CON3, 14 ,3),
1098
1099         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc0-vcc", "lcdc0" ,"NULL", RK3188_GRF_IO_CON4, 0 ,3),
1100         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "jtag" ,"NULL", RK3188_GRF_IO_CON4, 2 ,3),
1101         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "misc" ,"NULL", RK3188_GRF_IO_CON4, 4 ,3),
1102         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "reserve" ,"NULL", RK3188_GRF_IO_CON4, 6 ,3),
1103
1104 };
1105
1106 static struct func_to_reg_offset rk3188_func_to_vol_reg_offset[] =
1107 {
1108         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "ap0-vcc", "vol_domain", "ap0-vcc", RK3188_GRF_IO_CON4, 8 ,1),
1109         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "ap1-vcc", "vol_domain", "ap1-vcc", RK3188_GRF_IO_CON4, 9 ,1),
1110         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "cif-vcc", "vol_domain", "cif-vcc", RK3188_GRF_IO_CON4, 10 ,1),
1111         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash-vcc", "vol_domain", "flash-vcc", RK3188_GRF_IO_CON4, 11 ,1),
1112         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "vccio0-vcc", "vol_domain", "vccio0-vcc", RK3188_GRF_IO_CON4, 12 ,1),
1113         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "vccio1-vcc", "vol_domain", "vccio1-vcc", RK3188_GRF_IO_CON4, 13 ,1),
1114         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc0-vcc", "vol_domain", "lcdc0-vcc", RK3188_GRF_IO_CON4, 14 ,1),
1115         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc1-vcc", "vol_domain", "lcdc1-vcc", RK3188_GRF_IO_CON4, 15 ,1),
1116 };
1117
1118
1119 static struct func_to_reg_offset rk3288_func_to_vol_reg_offset[] =
1120 {
1121         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc-vcc", "vol_domain", "lcdc-vcc", RK3288_GRF_IO_VSEL, 0 ,1),
1122         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "dvp-vcc", "vol_domain", "dvp-vcc", RK3288_GRF_IO_VSEL, 1 ,1),
1123         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash0-vcc", "vol_domain", "flash0-vcc", RK3288_GRF_IO_VSEL, 2 ,1),
1124         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash1-vcc", "vol_domain", "flash1-vcc", RK3288_GRF_IO_VSEL, 3 ,1),
1125         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "wifi-vcc", "vol_domain", "wifi-vcc", RK3288_GRF_IO_VSEL, 4 ,1),
1126         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "bb-vcc", "vol_domain", "bb-vcc", RK3288_GRF_IO_VSEL, 5 ,1),
1127         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "audio-vcc", "vol_domain", "audio-vcc", RK3288_GRF_IO_VSEL, 6 ,1),
1128         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "sdcard-vcc", "vol_domain", "sdcard-vcc", RK3288_GRF_IO_VSEL, 7 ,1),
1129
1130         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "gpio30-vcc", "vol_domain", "gpio30-vcc", RK3288_GRF_IO_VSEL, 8 ,1),
1131         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "gpio1830-vcc", "vol_domain", "gpio1830-vcc", RK3288_GRF_IO_VSEL, 9 ,1),
1132 };
1133
1134
1135 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1136                                     int pin_num, void __iomem **reg, u8 *bit)
1137 {
1138         struct rockchip_pinctrl *info = bank->drvdata;
1139         void __iomem *reg_base;
1140         int pin = pin_num;
1141
1142         *reg = info->reg_base + RK2928_PULL_OFFSET;
1143         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1144         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1145
1146         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1147
1148         reg_base = info->reg_base;
1149
1150         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1151 };
1152
1153
1154 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1155                                     int pin_num, void __iomem **reg, u8 *bit)
1156 {
1157         struct rockchip_pinctrl *info = bank->drvdata;
1158         void __iomem *reg_base;
1159         int pin = pin_num;
1160
1161         /* The first 12 pins of the first bank are located elsewhere */
1162         if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
1163                 *reg = bank->reg_pull_bank0 +
1164                                 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1165                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1166                 *bit *= RK3188_PULL_BITS_PER_PIN;
1167                 reg_base = bank->reg_pull_bank0;
1168         } else {
1169                 *reg = info->reg_pull - 4;
1170                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1171                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1172
1173                 /*
1174                  * The bits in these registers have an inverse ordering
1175                  * with the lowest pin being in bits 15:14 and the highest
1176                  * pin in bits 1:0
1177                  */
1178                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1179                 *bit *= RK3188_PULL_BITS_PER_PIN;
1180                 reg_base = info->reg_pull - 4;
1181         }
1182
1183         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1184 }
1185
1186 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1187                                     int pin_num, void __iomem **reg, u8 *bit)
1188 {
1189         struct rockchip_pinctrl *info = bank->drvdata;
1190         void __iomem *reg_base;
1191         int pin = pin_num;
1192
1193         /* The first 24 pins of the first bank are located elsewhere */
1194         if (bank->bank_type == RK3288_BANK0 && pin_num < 24) {
1195                 *reg = bank->reg_pull_bank0 +
1196                                 ((pin_num / 8) * 4);
1197                 *bit = pin_num % 8;
1198                 *bit *= 2;
1199                 reg_base = bank->reg_pull_bank0;
1200         } else {
1201                 *reg = info->reg_pull - 0x10;
1202                 *reg += bank->bank_num * 0x10;
1203                 *reg += ((pin_num / 8) * 4);
1204
1205                 *bit = (pin_num % 8);
1206                 *bit *= 2;
1207                 reg_base = info->reg_pull - 0x10;
1208         }
1209
1210         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1211 }
1212
1213
1214 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1215                                     int pin_num, void __iomem **reg, u8 *bit)
1216 {
1217         struct rockchip_pinctrl *info = bank->drvdata;
1218         void __iomem *reg_base;
1219         int pin = pin_num;
1220
1221         /* The first 24 pins of the first bank are located elsewhere */
1222         if (bank->bank_type == RK3288_BANK0 && pin_num < 24) {
1223                 *reg = bank->reg_drv_bank0 +
1224                                 ((pin_num / 8) * 4);
1225                 *bit = pin_num % 8;
1226                 *bit *= 2;
1227
1228                 reg_base = bank->reg_drv_bank0;
1229         } else {
1230                 *reg = info->reg_drv - 0x10;
1231                 *reg += bank->bank_num * 0x10;
1232                 *reg += ((pin_num / 8) * 4);
1233
1234                 *bit = (pin_num % 8);
1235                 *bit *= 2;
1236
1237                 reg_base = info->reg_drv - 0x10;
1238         }
1239
1240         DBG_PINCTRL("%s:GPIO%d-%d, drv_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1241 }
1242
1243
1244 static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1245                                     int pin_num, void __iomem **reg, u8 *bit)
1246 {
1247         struct rockchip_pinctrl *info = bank->drvdata;
1248         void __iomem *reg_base;
1249         int pin = pin_num;
1250
1251         *reg = info->reg_pull;
1252         *reg += bank->bank_num * RK3036_PULL_BANK_STRIDE;
1253         *reg += (pin_num / RK3036_PULL_PINS_PER_REG) * 4;
1254
1255         *bit = pin_num % RK3036_PULL_PINS_PER_REG;
1256
1257         reg_base = info->reg_pull;
1258
1259         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1260 }
1261
1262
1263 static void rk312x_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1264                                     int pin_num, void __iomem **reg, u8 *bit)
1265 {
1266         struct rockchip_pinctrl *info = bank->drvdata;
1267         void __iomem *reg_base;
1268         int pin = pin_num;
1269
1270         *reg = info->reg_pull;
1271         *reg += bank->bank_num * RK312X_PULL_BANK_STRIDE;
1272         *reg += (pin_num / RK312X_PULL_PINS_PER_REG) * 4;
1273
1274         *bit = pin_num % RK312X_PULL_PINS_PER_REG;
1275
1276         reg_base = info->reg_pull;
1277
1278         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1279 }
1280
1281
1282
1283
1284 #if 0
1285 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1286 {
1287         struct rockchip_pinctrl *info = bank->drvdata;
1288         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1289         void __iomem *reg;
1290         u8 bit;
1291         u32 data;
1292         int pin = pin_num;
1293
1294         /* rk3066b does support any pulls */
1295         if (ctrl->type == RK3066B)
1296                 return PIN_CONFIG_BIAS_DISABLE;
1297
1298         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
1299
1300         switch (ctrl->type) {
1301         case RK2928:
1302                 return !(readl_relaxed(reg) & BIT(bit))
1303                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1304                                 : PIN_CONFIG_BIAS_DISABLE;
1305         case RK3188:
1306         case RK3288:
1307                 data = readl_relaxed(reg) >> bit;
1308                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1309
1310                 switch (data) {
1311                 case 0:
1312                         return PIN_CONFIG_BIAS_DISABLE;
1313                 case 1:
1314                         return PIN_CONFIG_BIAS_PULL_UP;
1315                 case 2:
1316                         return PIN_CONFIG_BIAS_PULL_DOWN;
1317                 case 3:
1318                         return PIN_CONFIG_BIAS_BUS_HOLD;
1319                 }
1320
1321                 dev_err(info->dev, "unknown pull setting\n");
1322                 return -EIO;
1323         default:
1324                 dev_err(info->dev, "unsupported pinctrl type\n");
1325                 return -EINVAL;
1326         };
1327
1328         DBG_PINCTRL("%s:GPIO%d-%d pull is 0x%x\n", __func__, bank->bank_num, pin_num, data);
1329 }
1330 #endif
1331
1332 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1333                                         int pin_num, int pull)
1334 {
1335         struct rockchip_pinctrl *info = bank->drvdata;
1336         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1337         void __iomem *reg;
1338         unsigned long flags;
1339         u8 bit;
1340         u32 data;
1341         int pin = pin_num;
1342
1343
1344         /* rk3066b does support any pulls */
1345         if (ctrl->type == RK3066B)
1346                 return pull ? -EINVAL : 0;
1347
1348         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
1349
1350         switch (ctrl->type) {
1351         case RK2928:
1352         case RK3036:
1353         case RK312X:
1354                 spin_lock_irqsave(&bank->slock, flags);
1355
1356                 data = BIT(bit + 16);
1357                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1358                         data |= BIT(bit);
1359
1360                 if(pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
1361                 writel(data, reg);
1362
1363                 spin_unlock_irqrestore(&bank->slock, flags);
1364                 break;
1365         case RK3188:
1366         case RK3288:
1367                 spin_lock_irqsave(&bank->slock, flags);
1368
1369                 /* enable the write to the equivalent lower bits */
1370                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1371
1372                 switch (pull) {
1373                 case PIN_CONFIG_BIAS_DISABLE:
1374                         break;
1375                 case PIN_CONFIG_BIAS_PULL_UP:
1376                         data |= (1 << bit);
1377                         break;
1378                 case PIN_CONFIG_BIAS_PULL_DOWN:
1379                         data |= (2 << bit);
1380                         break;
1381                 case PIN_CONFIG_BIAS_BUS_HOLD:
1382                         data |= (3 << bit);
1383                         break;
1384                 default:
1385                         dev_err(info->dev, "unsupported pull setting %d\n",
1386                                 pull);
1387                         return -EINVAL;
1388                 }
1389
1390                 writel(data, reg);
1391
1392                 spin_unlock_irqrestore(&bank->slock, flags);
1393                 break;
1394         default:
1395                 dev_err(info->dev, "unsupported pinctrl type\n");
1396                 return -EINVAL;
1397         }
1398
1399
1400         DBG_PINCTRL("%s:GPIO%d-%d pull is 0x%x\n", __func__, bank->bank_num, pin_num, data);
1401
1402         return 0;
1403 }
1404
1405 /*
1406  * Pinconf_ops handling
1407  */
1408
1409 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1410                                         enum pin_config_param pull)
1411 {
1412         switch (ctrl->type) {
1413         case RK2928:
1414         case RK3036:
1415         case RK312X:
1416                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1417                                         pull == PIN_CONFIG_BIAS_DISABLE);
1418         case RK3066B:
1419                 return pull ? false : true;
1420         case RK3188:
1421                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1422         case RK3288:
1423                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1424         }
1425
1426         return false;
1427 }
1428
1429 #if 0
1430 static int _rockchip_pinconf_get(struct rockchip_pin_bank *bank,
1431                                         int pin_num, unsigned long *config, int config_type, unsigned group)
1432 {
1433         struct rockchip_pinctrl *info = bank->drvdata;
1434         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1435         struct func_to_reg_offset reg_offset[4];//same name count should be less four
1436         struct func_to_reg_offset *func_to_reg;
1437         int i = 0, ii = 0, j = 0, jj = 0, num = 0;
1438         int data = 0;
1439         u8 bit;
1440         unsigned long flags;
1441         void __iomem *reg;
1442         int pin = pin_num;
1443
1444
1445         if(group < 0)
1446                 return -1;
1447
1448         DBG_PINCTRL("%s:GPIO%d-%d,group=%s, function=%s, type=%d\n", __func__, bank->bank_num, pin_num, info->groups[group].name, info->groups[group].func_name, config_type);
1449
1450         switch(ctrl->type)
1451         {
1452                 case RK2928:
1453                 //to do
1454                 break;
1455
1456                 case RK3066B:
1457
1458                 break;
1459
1460                 case RK3188:
1461
1462                 switch(config_type)
1463                 {
1464                         case TYPE_PULL_REG:
1465                         //compare pin num
1466
1467                         break;
1468
1469                         case TYPE_VOL_REG:
1470                         //compare group_name
1471                         func_to_reg = rk3188_func_to_vol_reg_offset;
1472                         num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1473                         for(i = 0; i < num; i++)
1474                         {
1475                                 //lcdc0-vcc-33 = lcdc0-vcc and lcdc0-vcc-18=lcdc0-vcc
1476                                 if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1477                                 {
1478                                         reg_offset[j++] = func_to_reg[i];
1479                                         DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1480                                 }
1481                         }
1482
1483                         if(j == 0)
1484                         {
1485                                 func_to_reg = rk3188_func_to_drv_reg_offset;
1486                                 num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1487                                 for(i = 0; i < num; i++)
1488                                 {
1489                                         if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1490                                         {
1491
1492                                                 func_to_reg = rk3188_func_to_vol_reg_offset;
1493                                                 num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1494                                                 for(ii = 0; ii < num; ii++)
1495                                                 {
1496                                                         if(!strcmp(func_to_reg[i].vol_name, func_to_reg[ii].group_name))
1497                                                         {
1498                                                                 reg_offset[jj++] = func_to_reg[ii];
1499                                                                 DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[ii].group_name);
1500                                                         }
1501                                                 }
1502
1503                                         }
1504                                 }
1505
1506
1507                                 j = jj;
1508
1509                         }
1510
1511
1512                         break;
1513
1514                         case TYPE_DRV_REG:
1515                         //compare func_name
1516                         func_to_reg = rk3188_func_to_drv_reg_offset;
1517                         num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1518                         for(i = 0; i < num; i++)
1519                         {
1520                                 if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1521                                 {
1522                                         reg_offset[j++] = func_to_reg[i];
1523                                         DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[i].func_name);
1524                                 }
1525                         }
1526
1527                         break;
1528
1529                         case TYPE_TRI_REG:
1530                         break;
1531
1532                         default:
1533                         break;
1534
1535                 }
1536
1537                 break;
1538
1539                 case RK3288:
1540
1541                 switch(config_type)
1542                 {
1543                         case TYPE_VOL_REG:
1544                                 //compare group_name
1545                                 func_to_reg = rk3288_func_to_vol_reg_offset;
1546                                 num = ARRAY_SIZE(rk3288_func_to_vol_reg_offset);
1547                                 for(i = 0; i < num; i++)
1548                                 {
1549                                         //lcdc-vcc-33 = lcdc-vcc and lcdc-vcc-18 = lcdc-vcc
1550                                         if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1551                                         {
1552                                                 reg_offset[j++] = func_to_reg[i];
1553                                                 DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1554                                         }
1555                                 }
1556
1557                                 break;
1558
1559                         case TYPE_DRV_REG:
1560
1561                                 ctrl->drv_calc_reg(bank, pin_num, &reg, &bit);
1562
1563                                 data = readl_relaxed(reg) >> bit;
1564                                 data &= (1 << 2) - 1;
1565
1566                                 *config = data;
1567
1568                                 break;
1569                         default:
1570                                 break;
1571
1572                 }
1573
1574                 break;
1575
1576                 default:
1577                 break;
1578         }
1579
1580
1581         if((ctrl->type == RK3188) || ((ctrl->type == RK3288) && (config_type == TYPE_VOL_REG)))
1582         {
1583                 if(j <= 0)
1584                 {
1585                         printk("%s:could find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num);
1586                         return -1;
1587                 }
1588
1589
1590                 for(i=0; i < j; i++)
1591                 {
1592                         reg = info->reg_base + reg_offset[i].reg_offset;
1593                         spin_lock_irqsave(&bank->slock, flags);
1594                         data = readl_relaxed(reg) >> reg_offset[i].bit_offset;
1595                         data &= reg_offset[i].bit_mask;
1596                         spin_unlock_irqrestore(&bank->slock, flags);
1597
1598                         *config = data;
1599
1600                         DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=0x%x,data[%d]=0x%x\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data);
1601                 }
1602
1603         }
1604         else if((ctrl->type == RK3288) && (config_type == TYPE_DRV_REG))
1605         {
1606                 DBG_PINCTRL("%s:GPIO-%d %d drv=0x%x\n",__func__, bank->bank_num, pin_num, (u32)*config);
1607         }
1608
1609         return 0;
1610 }
1611 #endif
1612
1613
1614 static int _rockchip_pinconf_set(struct rockchip_pin_bank *bank,
1615                                         int pin_num, int arg, int config_type, unsigned group)
1616 {
1617         struct rockchip_pinctrl *info = bank->drvdata;
1618         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1619         struct func_to_reg_offset reg_offset[4];//same name count should be less four
1620         struct func_to_reg_offset *func_to_reg;
1621         int i = 0, ii = 0, j = 0, jj = 0, num = 0;
1622         int data = 0, value = 0;
1623         u8 bit;
1624         unsigned long flags;
1625         void __iomem *reg;
1626         int pin = pin_num;
1627
1628
1629         if(group < 0)
1630                 return -1;
1631
1632         DBG_PINCTRL("%s:GPIO%d-%d,group=%s, function=%s, type=%d\n", __func__, bank->bank_num, pin_num, info->groups[group].name, info->groups[group].func_name, config_type);
1633
1634         switch(ctrl->type)
1635         {
1636                 case RK2928:
1637                 //to do
1638                 break;
1639
1640                 case RK3066B:
1641
1642                 break;
1643
1644                 case RK3188:
1645
1646                 switch(config_type)
1647                 {
1648                         case TYPE_PULL_REG:
1649                         //compare pin num
1650
1651                         break;
1652
1653                         case TYPE_VOL_REG:
1654                         //compare group_name
1655                         func_to_reg = rk3188_func_to_vol_reg_offset;
1656                         num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1657                         for(i = 0; i < num; i++)
1658                         {
1659                                 //lcdc0-vcc-33 = lcdc0-vcc and lcdc0-vcc-18=lcdc0-vcc
1660                                 if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1661                                 {
1662                                         reg_offset[j++] = func_to_reg[i];
1663                                         DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1664                                 }
1665                         }
1666
1667                         if(j == 0)
1668                         {
1669                                 func_to_reg = rk3188_func_to_drv_reg_offset;
1670                                 num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1671                                 for(i = 0; i < num; i++)
1672                                 {
1673                                         if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1674                                         {
1675
1676                                                 func_to_reg = rk3188_func_to_vol_reg_offset;
1677                                                 num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1678                                                 for(ii = 0; ii < num; ii++)
1679                                                 {
1680                                                         if(!strcmp(rk3188_func_to_drv_reg_offset[i].vol_name, func_to_reg[ii].group_name))
1681                                                         {
1682                                                                 reg_offset[jj++] = func_to_reg[ii];
1683                                                                 DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[ii].group_name);
1684                                                         }
1685                                                 }
1686
1687                                         }
1688                                 }
1689
1690
1691                                 j = jj;
1692
1693                         }
1694
1695
1696                         break;
1697
1698                         case TYPE_DRV_REG:
1699                         //compare func_name
1700                         func_to_reg = rk3188_func_to_drv_reg_offset;
1701                         num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1702                         for(i = 0; i < num; i++)
1703                         {
1704                                 if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1705                                 {
1706                                         reg_offset[j++] = func_to_reg[i];
1707                                         DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[i].func_name);
1708                                 }
1709                         }
1710
1711                         break;
1712
1713                         case TYPE_TRI_REG:
1714                         break;
1715
1716                         default:
1717                         break;
1718
1719                 }
1720
1721                 break;
1722
1723                 case RK3288:
1724
1725                 switch(config_type)
1726                 {
1727                         case TYPE_VOL_REG:
1728                                 //compare group_name
1729                                 func_to_reg = rk3288_func_to_vol_reg_offset;
1730                                 num = ARRAY_SIZE(rk3288_func_to_vol_reg_offset);
1731                                 for(i = 0; i < num; i++)
1732                                 {
1733                                         //lcdc-vcc-33 = lcdc-vcc and lcdc-vcc-18 = lcdc-vcc
1734                                         if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1735                                         {
1736                                                 reg_offset[j++] = func_to_reg[i];
1737                                                 DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1738                                         }
1739                                 }
1740
1741                                 break;
1742
1743                         case TYPE_DRV_REG:
1744
1745                                 ctrl->drv_calc_reg(bank, pin_num, &reg, &bit);
1746
1747                                 spin_lock_irqsave(&bank->slock, flags);
1748
1749                                 data = arg << bit;
1750                                 data &= (3<<bit);
1751                                 data |= (3<<(bit+16));
1752
1753                                 writel_relaxed(data, reg);
1754                                 spin_unlock_irqrestore(&bank->slock, flags);
1755
1756                                 break;
1757                         default:
1758                                 break;
1759
1760                 }
1761
1762                 break;
1763
1764                 case RK3036:
1765
1766                 switch(config_type)
1767                 {
1768                         case TYPE_DRV_REG:
1769
1770                                 if((bank->bank_num == 1) && (pin_num >= 0) && (pin_num <= 3))
1771                                 {
1772                                         bit = pin_num*2 + 4;
1773                                         reg = info->reg_drv;
1774                                         spin_lock_irqsave(&bank->slock, flags);
1775
1776                                         data = arg << bit;
1777                                         data &= (3<<bit);
1778                                         data |= (3<<(bit+16));
1779
1780                                         writel_relaxed(data, reg);
1781                                         spin_unlock_irqrestore(&bank->slock, flags);
1782                                 }
1783                                 else
1784                                 {
1785                                         printk("%s:RK3036 GPIO%d-%d could not support driver setting\n",__func__, bank->bank_num, pin_num);
1786                                 }
1787                                 break;
1788                         default:
1789                                 break;
1790
1791                 }
1792
1793                 break;
1794
1795                 case RK312X:
1796
1797                 switch(config_type)
1798                 {
1799                         case TYPE_DRV_REG:
1800
1801                                 if((bank->bank_num == 0)&&((pin_num == GPIO_A6)|| (pin_num == GPIO_A7)||(pin_num == GPIO_B7)||(pin_num == GPIO_C4)))
1802                                 {
1803                                         if(pin_num == GPIO_A6)
1804                                         bit = 4;
1805                                         else if(pin_num == GPIO_A7)
1806                                         bit = 6;
1807                                         else if(pin_num == GPIO_B7)
1808                                         bit = 8;
1809                                         else if(pin_num == GPIO_C4)
1810                                         bit = 10;
1811
1812                                         reg = info->reg_drv;
1813                                         spin_lock_irqsave(&bank->slock, flags);
1814
1815                                         data = arg << bit;
1816                                         data &= (3<<bit);
1817                                         data |= (3<<(bit+16));
1818
1819                                         writel_relaxed(data, reg);
1820                                         spin_unlock_irqrestore(&bank->slock, flags);
1821                                 }
1822                                 else
1823                                 {
1824                                         printk("%s:RK312X GPIO%d-%d could not support driver setting\n",__func__, bank->bank_num, pin_num);
1825                                 }
1826                                 break;
1827                         default:
1828                                 break;
1829
1830                 }
1831
1832                 break;
1833
1834                 default:
1835                 break;
1836         }
1837
1838
1839         if((ctrl->type == RK3188) || ((ctrl->type == RK3288) && (config_type == TYPE_VOL_REG)))
1840         {
1841                 if(j <= 0)
1842                 {
1843                         printk("%s:could not find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num);
1844                         return -1;
1845                 }
1846
1847                 for(i=0; i < j; i++)
1848                 {
1849                         reg = info->reg_base + reg_offset[i].reg_offset;
1850                         data |= ((reg_offset[i].bit_mask) << (16 + reg_offset[i].bit_offset));
1851                         data |= ((arg & reg_offset[i].bit_mask) << reg_offset[i].bit_offset);
1852                         spin_lock_irqsave(&bank->slock, flags);
1853                         writel_relaxed(data, reg);
1854                         value = readl_relaxed(reg);
1855                         spin_unlock_irqrestore(&bank->slock, flags);
1856                         DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=%d,data[%d]=0x%08x,result=0x%08x,arg=%d\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data, value, arg);
1857                 }
1858
1859         }
1860
1861         else if((ctrl->type == RK3288) && (config_type == TYPE_DRV_REG))
1862         {
1863                 DBG_PINCTRL("%s:GPIO-%d %d data=0x%x,type=%d\n",__func__, bank->bank_num, pin_num, data,TYPE_DRV_REG);
1864         }
1865
1866         return 0;
1867 }
1868
1869
1870 /* set the pin config settings for a specified pin */
1871 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1872                                 unsigned long configs, unsigned group)
1873 {
1874         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1875         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1876         struct rockchip_pin_group *grp = &info->groups[group];
1877         enum pin_config_param param;
1878         u16 arg;
1879         int rc;
1880
1881
1882         param = pinconf_to_config_param(configs);
1883         arg = pinconf_to_config_argument(configs);
1884
1885         switch (param) {
1886         case PIN_CONFIG_BIAS_DISABLE:
1887                 rc =  rockchip_set_pull(bank, pin - bank->pin_base,
1888                         param);
1889                 if (rc)
1890                         return rc;
1891                 break;
1892         case PIN_CONFIG_BIAS_PULL_UP:
1893         case PIN_CONFIG_BIAS_PULL_DOWN:
1894         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1895         case PIN_CONFIG_BIAS_BUS_HOLD:
1896                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1897                         return -ENOTSUPP;
1898
1899                 if (!arg)
1900                         return -EINVAL;
1901
1902                 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1903                         param);
1904                 if (rc)
1905                         return rc;
1906                 break;
1907
1908         case PIN_CONFIG_POWER_SOURCE:
1909                 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, arg, TYPE_VOL_REG, group);
1910                 if (rc)
1911                 return rc;
1912                 break;
1913
1914         case PIN_CONFIG_DRIVE_STRENGTH:
1915                 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, arg, TYPE_DRV_REG, group);
1916                 if (rc)
1917                 return rc;
1918                 break;
1919         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1920                 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, arg, TYPE_TRI_REG, group);
1921                 if (rc)
1922                 return rc;
1923                 break;
1924         default:
1925                 return -ENOTSUPP;
1926                 break;
1927         }
1928
1929         /* cache the config value for rockchip_pinconf_get() */
1930         grp->gconfigs = configs;
1931
1932         DBG_PINCTRL("%s,bank_num=%d,pin=%d,param=%d, arg=%d\n",__func__,bank->bank_num, pin, param, arg);
1933
1934         return 0;
1935 }
1936
1937 #if 0
1938 /* get the pin config settings for a specified pin */
1939 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1940                                                         unsigned long *config, unsigned group)
1941 {
1942         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1943         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1944         enum pin_config_param param = pinconf_to_config_param(*config);
1945         int rc;
1946
1947         switch (param) {
1948         case PIN_CONFIG_BIAS_DISABLE:
1949                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1950                         return -EINVAL;
1951
1952                 *config = 0;
1953                 break;
1954         case PIN_CONFIG_BIAS_PULL_UP:
1955         case PIN_CONFIG_BIAS_PULL_DOWN:
1956         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1957         case PIN_CONFIG_BIAS_BUS_HOLD:
1958                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1959                         return -ENOTSUPP;
1960
1961                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1962                         return -EINVAL;
1963
1964                 *config = 1;
1965                 break;
1966
1967         case PIN_CONFIG_POWER_SOURCE:
1968                 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_VOL_REG, group);
1969                 if (rc)
1970                 return rc;
1971                 break;
1972
1973         case PIN_CONFIG_DRIVE_STRENGTH:
1974                 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_DRV_REG, group);
1975                 if (rc)
1976                 return rc;
1977                 break;
1978         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1979                 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_TRI_REG, group);
1980                 if (rc)
1981                 return rc;
1982                 break;
1983
1984         default:
1985                 return -ENOTSUPP;
1986                 break;
1987         }
1988
1989
1990         DBG_PINCTRL("%s:bank_num=%d, pin=%d, param=%d\n",__func__, bank->bank_num, pin, param);
1991
1992         return 0;
1993 }
1994 #endif
1995
1996 /* set the pin config settings for a specified pin group */
1997 static int rockchip_pinconf_group_set(struct pinctrl_dev *pctldev,
1998                         unsigned group, unsigned long config)
1999 {
2000         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2001         const unsigned int *pins;
2002         unsigned int cnt;
2003         struct rockchip_pin_bank *bank;
2004         int pin;
2005
2006         pins = info->groups[group].pins;
2007
2008         for (cnt = 0; cnt < info->groups[group].npins; cnt++)
2009         {
2010                 bank = pin_to_bank(info, pins[cnt]);
2011                 pin = pins[cnt];
2012                 DBG_PINCTRL("%s:group[%d]:%s, pins[%d]=%d\n",__func__, group, info->groups[group].name, cnt, pins[cnt]);
2013                 rockchip_pinconf_set(pctldev, pins[cnt], config, group);
2014         }
2015
2016         return 0;
2017 }
2018
2019 /* get the pin config settings for a specified pin group */
2020 static int rockchip_pinconf_group_get(struct pinctrl_dev *pctldev,
2021                                 unsigned int group, unsigned long *config)
2022 {
2023         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2024         const unsigned int *pins;
2025         struct rockchip_pin_bank *bank;
2026
2027         pins = info->groups[group].pins;
2028         bank = pin_to_bank(info, pins[0]);
2029
2030         //rockchip_pinconf_get(pctldev, pins[0], config, group);
2031         *config = info->groups[group].gconfigs;
2032         if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
2033         printk("%s:group[%d]:%s,config=0x%lx\n",__func__, group, info->groups[group].name, *config);
2034         return 0;
2035 }
2036
2037 static void rockchip_pinconf_dbg_show(struct pinctrl_dev *pctldev,
2038                                  struct seq_file *s, unsigned pin)
2039 {
2040         //to do
2041 }
2042
2043 static void rockchip_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
2044                                        struct seq_file *s, unsigned group)
2045 {
2046         //to do
2047 }
2048
2049
2050 static const struct pinconf_ops rockchip_pinconf_ops = {
2051         .pin_config_group_get           = rockchip_pinconf_group_get,
2052         .pin_config_group_set           = rockchip_pinconf_group_set,
2053         .pin_config_dbg_show            = rockchip_pinconf_dbg_show,
2054         .pin_config_group_dbg_show      = rockchip_pinconf_group_dbg_show,
2055 };
2056
2057 static const struct of_device_id rockchip_bank_match[] = {
2058         { .compatible = "rockchip,gpio-bank" },
2059         { .compatible = "rockchip,rk3188-gpio-bank0" },
2060         { .compatible = "rockchip,rk3288-gpio-bank0" },
2061         {},
2062 };
2063
2064 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2065                                                 struct device_node *np)
2066 {
2067         struct device_node *child;
2068
2069         for_each_child_of_node(np, child) {
2070                 if (of_match_node(rockchip_bank_match, child))
2071                         continue;
2072
2073                 info->nfunctions++;
2074                 info->ngroups += of_get_child_count(child);
2075         }
2076 }
2077
2078 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2079                                               struct rockchip_pin_group *grp,
2080                                               struct rockchip_pinctrl *info,
2081                                               u32 index)
2082 {
2083         struct rockchip_pin_bank *bank;
2084         int size;
2085         const __be32 *list;
2086         int i, j;
2087         struct union_mode m;
2088         int configlen = 0;
2089         unsigned long *pinconfig;
2090         u32 val;
2091
2092         //printk("%s:group(%d): %s\n", __func__, index, np->name);
2093
2094         /* Initialise group */
2095         grp->name = np->name;
2096
2097         /*
2098          * the binding format is rockchip,pins = <mux>,
2099          * do sanity check and calculate pins number
2100          */
2101         list = of_get_property(np, "rockchip,pins", &size);
2102         /* we do not check return since it's safe node passed down */
2103         size /= sizeof(*list);
2104         if (!size || size % 1) {
2105                 dev_err(info->dev, "wrong pins number or pins and configs should be by 1\n");
2106                 return -EINVAL;
2107         }
2108
2109         grp->npins = size / 1;
2110
2111         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
2112                                                 GFP_KERNEL);
2113         grp->data = devm_kzalloc(info->dev, grp->npins *
2114                                           sizeof(struct rockchip_pin_config),
2115                                         GFP_KERNEL);
2116         if (!grp->pins || !grp->data)
2117                 return -ENOMEM;
2118
2119         pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
2120
2121         for (i = 0; i < size; i++) {
2122                 m.mode = be32_to_cpu(*list++);
2123
2124                 bank = bank_num_to_bank(info, m.mux.bank);
2125                 if (IS_ERR(bank))
2126                         return PTR_ERR(bank);
2127
2128                 grp->pins[i] = bank->pin_base + (m.mux.goff - 0x0A) * 8 + m.mux.off;
2129                 grp->data[i].func = m.mode;
2130
2131
2132                 j = 0;
2133                 configlen = 0;
2134
2135                 if (of_find_property(np, "rockchip,pull", NULL))
2136                         configlen++;
2137                 if (of_find_property(np, "rockchip,voltage", NULL))
2138                         configlen++;
2139                 if (of_find_property(np, "rockchip,drive", NULL))
2140                         configlen++;
2141                 if (of_find_property(np, "rockchip,tristate", NULL))
2142                         configlen++;
2143
2144                 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
2145
2146                 if (!of_property_read_u32(np, "rockchip,pull", &val)) {
2147                         enum pin_config_param pull = PIN_CONFIG_END;
2148                         if (val == 0)
2149                                 pull = PIN_CONFIG_BIAS_DISABLE;
2150                         if (val == 1)
2151                                 pull = PIN_CONFIG_BIAS_PULL_UP;
2152                         else if (val == 2)
2153                                 pull = PIN_CONFIG_BIAS_PULL_DOWN;
2154                         else if (val == 3)
2155                                 pull = PIN_CONFIG_BIAS_BUS_HOLD;
2156                         else if (val == 4)
2157                                 pull = PIN_CONFIG_BIAS_PULL_PIN_DEFAULT;
2158
2159                         pinconfig[j++] = pinconf_to_config_packed(pull, val);
2160                 }
2161
2162                 if (!of_property_read_u32(np, "rockchip,voltage", &val)) {
2163                         pinconfig[j++] =
2164                                 pinconf_to_config_packed(PIN_CONFIG_POWER_SOURCE,
2165                                                          val);
2166                 }
2167
2168                 if (!of_property_read_u32(np, "rockchip,drive", &val)) {
2169                         pinconfig[j++] =
2170                                 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
2171                                                          val);
2172                 }
2173
2174                 if (!of_property_read_u32(np, "rockchip,tristate", &val)) {
2175                         pinconfig[j++] =
2176                                 pinconf_to_config_packed(PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
2177                                                          val);
2178                 }
2179
2180                 grp->data[i].configs = pinconfig;
2181                 grp->data[i].nconfigs = configlen;
2182
2183         }
2184
2185         return 0;
2186 }
2187
2188
2189 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2190                                                 struct rockchip_pinctrl *info,
2191                                                 u32 index)
2192 {
2193         struct device_node *child;
2194         struct rockchip_pmx_func *func;
2195         struct rockchip_pin_group *grp;
2196         int ret;
2197         static u32 grp_index;
2198         u32 i = 0;
2199
2200         //printk("%s:parse function(%d): %s\n", __func__, index, np->name);
2201
2202         func = &info->functions[index];
2203
2204         /* Initialise function */
2205         func->name = np->name;
2206         func->ngroups = of_get_child_count(np);
2207         if (func->ngroups <= 0)
2208                 return 0;
2209
2210         func->groups = devm_kzalloc(info->dev,
2211                         func->ngroups * sizeof(char *), GFP_KERNEL);
2212         if (!func->groups)
2213                 return -ENOMEM;
2214
2215         for_each_child_of_node(np, child) {
2216                 func->groups[i] = child->name;
2217                 grp = &info->groups[grp_index++];
2218                 grp->func_name = np->name;
2219                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2220                 if (ret)
2221                         return ret;
2222
2223                 //printk("%s:grp->func_name(%d): %s\n", __func__, grp_index, grp->func_name);
2224         }
2225
2226         return 0;
2227 }
2228
2229 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2230                                               struct rockchip_pinctrl *info)
2231 {
2232         struct device *dev = &pdev->dev;
2233         struct device_node *np = dev->of_node;
2234         struct device_node *child;
2235         int ret;
2236         int i;
2237
2238         rockchip_pinctrl_child_count(info, np);
2239
2240         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2241         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2242
2243         info->functions = devm_kzalloc(dev, info->nfunctions *
2244                                               sizeof(struct rockchip_pmx_func),
2245                                               GFP_KERNEL);
2246         if (!info->functions) {
2247                 dev_err(dev, "failed to allocate memory for function list\n");
2248                 return -EINVAL;
2249         }
2250
2251         info->groups = devm_kzalloc(dev, info->ngroups *
2252                                             sizeof(struct rockchip_pin_group),
2253                                             GFP_KERNEL);
2254         if (!info->groups) {
2255                 dev_err(dev, "failed allocate memory for ping group list\n");
2256                 return -EINVAL;
2257         }
2258
2259         i = 0;
2260
2261         for_each_child_of_node(np, child) {
2262                 if (of_match_node(rockchip_bank_match, child))
2263                         continue;
2264
2265                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2266                 if (ret) {
2267                         dev_err(&pdev->dev, "failed to parse function\n");
2268                         return ret;
2269                 }
2270         }
2271
2272         return 0;
2273 }
2274
2275 static int rockchip_pinctrl_register(struct platform_device *pdev,
2276                                         struct rockchip_pinctrl *info)
2277 {
2278         struct pinctrl_desc *ctrldesc = &info->pctl;
2279         struct pinctrl_pin_desc *pindesc, *pdesc;
2280         struct rockchip_pin_bank *pin_bank;
2281         int pin, bank, ret;
2282         int k;
2283
2284         ctrldesc->name = "rockchip-pinctrl";
2285         ctrldesc->owner = THIS_MODULE;
2286         ctrldesc->pctlops = &rockchip_pctrl_ops;
2287         ctrldesc->pmxops = &rockchip_pmx_ops;
2288         ctrldesc->confops = &rockchip_pinconf_ops;
2289
2290         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
2291                         info->ctrl->nr_pins, GFP_KERNEL);
2292         if (!pindesc) {
2293                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
2294                 return -ENOMEM;
2295         }
2296         ctrldesc->pins = pindesc;
2297         ctrldesc->npins = info->ctrl->nr_pins;
2298
2299         pdesc = pindesc;
2300         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2301                 pin_bank = &info->ctrl->pin_banks[bank];
2302                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2303                         pdesc->number = k;
2304                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2305                                                 pin_bank->name, pin);
2306                         pdesc++;
2307                 }
2308         }
2309
2310         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
2311         if (!info->pctl_dev) {
2312                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2313                 return -EINVAL;
2314         }
2315
2316         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2317                 pin_bank = &info->ctrl->pin_banks[bank];
2318                 pin_bank->grange.name = pin_bank->name;
2319                 pin_bank->grange.id = bank;
2320                 pin_bank->grange.pin_base = pin_bank->pin_base;
2321                 pin_bank->grange.base = pin_bank->gpio_chip.base;
2322                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2323                 pin_bank->grange.gc = &pin_bank->gpio_chip;
2324                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2325         }
2326
2327         ret = rockchip_pinctrl_parse_dt(pdev, info);
2328         if (ret) {
2329                 pinctrl_unregister(info->pctl_dev);
2330                 return ret;
2331         }
2332
2333         return 0;
2334 }
2335
2336 /*
2337  * GPIO handling
2338  */
2339
2340 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
2341 {
2342         struct rockchip_pin_bank *bank = gc_to_pin_bank(chip);
2343         struct rockchip_pinctrl *info = bank->drvdata;
2344         int pin = offset;
2345
2346         if(bank->bank_num == 15)
2347         {
2348                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2349                 return -1;
2350         }
2351
2352
2353         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
2354         return pinctrl_request_gpio(chip->base + offset);
2355 }
2356
2357 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
2358 {
2359         struct rockchip_pin_bank *bank = gc_to_pin_bank(chip);
2360         struct rockchip_pinctrl *info = bank->drvdata;
2361         int pin = offset;
2362
2363         if(bank->bank_num == 15)
2364         {
2365                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2366                 return ;
2367         }
2368         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
2369         pinctrl_free_gpio(chip->base + offset);
2370 }
2371
2372 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2373 {
2374         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2375         struct rockchip_pinctrl *info = bank->drvdata;
2376         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2377         unsigned long flags;
2378         u32 data;
2379         int pin = offset;
2380
2381         spin_lock_irqsave(&bank->slock, flags);
2382
2383         data = readl(reg);
2384         data &= ~BIT(offset);
2385         if (value)
2386                 data |= BIT(offset);
2387         writel(data, reg);
2388
2389         spin_unlock_irqrestore(&bank->slock, flags);
2390
2391         DBG_PINCTRL("%s:GPIO%d-%d level = %d\n", __func__, bank->bank_num, offset, value);
2392 }
2393
2394 /*
2395  * Returns the level of the pin for input direction and setting of the DR
2396  * register for output gpios.
2397  */
2398 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2399 {
2400         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2401         struct rockchip_pinctrl *info = bank->drvdata;
2402         u32 data;
2403         int pin = offset;
2404
2405         data = readl(bank->reg_base + GPIO_EXT_PORT);
2406         data >>= offset;
2407         data &= 1;
2408
2409         DBG_PINCTRL("%s:GPIO%d-%d level = %d\n", __func__, bank->bank_num, offset, data);
2410         return data;
2411 }
2412
2413 /*
2414  * gpiolib gpio_direction_input callback function. The setting of the pin
2415  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2416  * interface.
2417  */
2418 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2419 {
2420         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2421         struct rockchip_pinctrl *info = bank->drvdata;
2422         int pin = offset;
2423
2424         if(bank->bank_num == 15)
2425         {
2426                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2427                 return -1;
2428         }
2429
2430         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
2431         return pinctrl_gpio_direction_input(gc->base + offset);
2432 }
2433
2434 /*
2435  * gpiolib gpio_direction_output callback function. The setting of the pin
2436  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2437  * interface.
2438  */
2439 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2440                                           unsigned offset, int value)
2441 {
2442         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2443         struct rockchip_pinctrl *info = bank->drvdata;
2444         int pin = offset;
2445
2446         if(bank->bank_num == 15)
2447         {
2448                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2449                 return -1;
2450         }
2451
2452         rockchip_gpio_set(gc, offset, value);
2453
2454         DBG_PINCTRL("%s:set GPIO%d-%d level %d\n", __func__, bank->bank_num, offset, value);
2455         return pinctrl_gpio_direction_output(gc->base + offset);
2456 }
2457
2458 /*
2459  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2460  * and a virtual IRQ, if not already present.
2461  */
2462 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2463 {
2464         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2465         struct rockchip_pinctrl *info = bank->drvdata;
2466         int pin = offset;
2467
2468         unsigned int virq;
2469
2470         if(bank->bank_num == 15)
2471         {
2472                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2473                 return -1;
2474         }
2475
2476         if (!bank->domain)
2477                 return -ENXIO;
2478
2479         virq = irq_create_mapping(bank->domain, offset);
2480
2481         DBG_PINCTRL("%s:virq=%d, GPIO%d-%d\n", __func__, virq, bank->bank_num, offset);
2482
2483         return (virq) ? : -ENXIO;
2484 }
2485
2486 static const struct gpio_chip rockchip_gpiolib_chip = {
2487         .request = rockchip_gpio_request,
2488         .free = rockchip_gpio_free,
2489         .set = rockchip_gpio_set,
2490         .get = rockchip_gpio_get,
2491         .direction_input = rockchip_gpio_direction_input,
2492         .direction_output = rockchip_gpio_direction_output,
2493         .to_irq = rockchip_gpio_to_irq,
2494         .owner = THIS_MODULE,
2495 };
2496
2497 /*
2498  * Interrupt handling
2499  */
2500
2501 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
2502 {
2503         struct irq_chip *chip = irq_get_chip(irq);
2504         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
2505         struct rockchip_pinctrl *info = bank->drvdata;
2506         int pin;
2507
2508         u32 polarity = 0, data = 0;
2509         u32 pend;
2510         bool edge_changed = false;
2511
2512         chained_irq_enter(chip, desc);
2513
2514         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2515
2516         if (bank->toggle_edge_mode) {
2517                 polarity = readl_relaxed(bank->reg_base +
2518                                          GPIO_INT_POLARITY);
2519                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2520         }
2521
2522         while (pend) {
2523                 unsigned int virq;
2524
2525                 irq = __ffs(pend);
2526                 pend &= ~BIT(irq);
2527                 virq = irq_linear_revmap(bank->domain, irq);
2528
2529                 if (!virq) {
2530                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2531                         continue;
2532                 }
2533
2534                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2535
2536                 /*
2537                  * Triggering IRQ on both rising and falling edge
2538                  * needs manual intervention.
2539                  */
2540                 if (bank->toggle_edge_mode & BIT(irq)) {
2541                         if (data & BIT(irq))
2542                                 polarity &= ~BIT(irq);
2543                         else
2544                                 polarity |= BIT(irq);
2545
2546                         edge_changed = true;
2547                 }
2548
2549                 generic_handle_irq(virq);
2550
2551                 pin = irq;
2552                 DBG_PINCTRL("%s:irq=%d,%s\n",__func__, irq, bank->name);
2553         }
2554
2555         if (bank->toggle_edge_mode && edge_changed) {
2556                 /* Interrupt params should only be set with ints disabled */
2557                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
2558                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
2559                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
2560                 writel(data, bank->reg_base + GPIO_INTEN);
2561         }
2562
2563         chained_irq_exit(chip, desc);
2564 }
2565
2566 static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
2567 {
2568         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2569         struct rockchip_pinctrl *info = bank->drvdata;
2570         u32 mask = BIT(d->hwirq);
2571         u32 polarity;
2572         u32 level;
2573         u32 data;
2574         u32 mux;
2575         unsigned long flags;
2576         int pin = d->hwirq;
2577
2578         /* make sure the pin is configured as gpio input */
2579         mux = (bank->bank_num << 12) | (((d->hwirq / 8) + 0x0A) << 8) | ((d->hwirq % 8)<< 4) | RK_FUNC_GPIO;
2580         rockchip_set_mux(bank, d->hwirq, mux);
2581
2582         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2583         data &= ~mask;
2584         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2585
2586         if (type & IRQ_TYPE_EDGE_BOTH)
2587                 __irq_set_handler_locked(d->irq, handle_edge_irq);
2588         else
2589                 __irq_set_handler_locked(d->irq, handle_level_irq);
2590
2591         spin_lock_irqsave(&bank->slock, flags);
2592
2593         level = readl_relaxed(bank->reg_base + GPIO_INTTYPE_LEVEL);
2594         polarity = readl_relaxed(bank->reg_base + GPIO_INT_POLARITY);
2595
2596         switch (type) {
2597         case IRQ_TYPE_EDGE_BOTH:
2598                 bank->toggle_edge_mode |= mask;
2599                 level |= mask;
2600
2601                 /*
2602                  * Determine gpio state. If 1 next interrupt should be falling
2603                  * otherwise rising.
2604                  */
2605                 data = readl(bank->reg_base + GPIO_EXT_PORT);
2606                 if (data & mask)
2607                         polarity &= ~mask;
2608                 else
2609                         polarity |= mask;
2610                 break;
2611         case IRQ_TYPE_EDGE_RISING:
2612                 bank->toggle_edge_mode &= ~mask;
2613                 level |= mask;
2614                 polarity |= mask;
2615                 break;
2616         case IRQ_TYPE_EDGE_FALLING:
2617                 bank->toggle_edge_mode &= ~mask;
2618                 level |= mask;
2619                 polarity &= ~mask;
2620                 break;
2621         case IRQ_TYPE_LEVEL_HIGH:
2622                 bank->toggle_edge_mode &= ~mask;
2623                 level &= ~mask;
2624                 polarity |= mask;
2625                 break;
2626         case IRQ_TYPE_LEVEL_LOW:
2627                 bank->toggle_edge_mode &= ~mask;
2628                 level &= ~mask;
2629                 polarity &= ~mask;
2630                 break;
2631         default:
2632                 //spin_unlock_irqrestore(&bank->slock, flags);
2633                 return -EINVAL;
2634         }
2635
2636         writel_relaxed(level, bank->reg_base + GPIO_INTTYPE_LEVEL);
2637         writel_relaxed(polarity, bank->reg_base + GPIO_INT_POLARITY);
2638
2639         spin_unlock_irqrestore(&bank->slock, flags);
2640
2641         DBG_PINCTRL("%s:type=%d,irq=%d,hwirq=%d,ok\n",__func__,type, d->irq, (int)d->hwirq);
2642         return 0;
2643 }
2644
2645
2646 static inline void rockchip_gpio_bit_op(void __iomem *reg_base, unsigned int offset, u32 bit, unsigned char flag)
2647 {
2648         u32 val = __raw_readl(reg_base + offset);
2649         if (flag)
2650                 val |= BIT(bit);
2651         else
2652                 val &= ~BIT(bit);
2653
2654
2655         __raw_writel(val, reg_base + offset);
2656 }
2657
2658 static inline unsigned gpio_to_bit(struct rockchip_pin_bank *bank, unsigned gpio)
2659 {
2660         while (gpio >= (bank->pin_base + bank->nr_pins))
2661                 bank++;
2662
2663         return gpio - bank->pin_base;
2664 }
2665
2666 static inline unsigned offset_to_bit(unsigned offset)
2667 {
2668         return 1u << offset;
2669 }
2670
2671 static void GPIOEnableIntr(void __iomem *reg_base, unsigned int bit)
2672 {
2673         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 1);
2674 }
2675
2676 static void GPIODisableIntr(void __iomem *reg_base, unsigned int bit)
2677 {
2678         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 0);
2679 }
2680
2681 static void GPIOAckIntr(void __iomem *reg_base, unsigned int bit)
2682 {
2683         rockchip_gpio_bit_op(reg_base, GPIO_PORTS_EOI, bit, 1);
2684 }
2685
2686 static int rockchip_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
2687 {
2688         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2689         struct rockchip_pinctrl *info = bank->drvdata;
2690
2691         u32 bit = d->hwirq;
2692         unsigned long flags;
2693         int pin = d->hwirq;
2694
2695         spin_lock_irqsave(&bank->slock, flags);
2696
2697         if (on)
2698         {
2699                 bank->suspend_wakeup |= BIT(bit);
2700         }
2701         else
2702         {
2703                 bank->suspend_wakeup &= ~BIT(bit);
2704         }
2705         spin_unlock_irqrestore(&bank->slock, flags);
2706
2707         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2708         return 0;
2709 }
2710
2711 static void rockchip_gpio_irq_unmask(struct irq_data *d)
2712 {
2713         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2714         struct rockchip_pinctrl *info = bank->drvdata;
2715         u32 bit = d->hwirq;
2716         unsigned long flags;
2717         int pin = d->hwirq;
2718
2719         spin_lock_irqsave(&bank->slock, flags);
2720         GPIOEnableIntr(bank->reg_base, bit);
2721         spin_unlock_irqrestore(&bank->slock, flags);
2722
2723         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2724 }
2725
2726 static void rockchip_gpio_irq_mask(struct irq_data *d)
2727 {
2728         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2729         struct rockchip_pinctrl *info = bank->drvdata;
2730         //u32 bit = gpio_to_bit(bank, d->irq);
2731         u32 bit = d->hwirq;
2732         unsigned long flags;
2733         int pin = d->hwirq;
2734
2735         spin_lock_irqsave(&bank->slock, flags);
2736         GPIODisableIntr(bank->reg_base, bit);
2737         spin_unlock_irqrestore(&bank->slock, flags);
2738
2739         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2740 }
2741
2742 static void rockchip_gpio_irq_ack(struct irq_data *d)
2743 {
2744         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2745         struct rockchip_pinctrl *info = bank->drvdata;
2746         //u32 bit = gpio_to_bit(bank, d->irq);
2747         u32 bit = d->hwirq;
2748         int pin = d->hwirq;
2749
2750         GPIOAckIntr(bank->reg_base, bit);
2751
2752         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2753 }
2754
2755
2756 static struct irq_chip rockchip_gpio_irq_chip = {
2757         .name           = "GPIO",
2758         .irq_ack        = rockchip_gpio_irq_ack,
2759         .irq_disable    = rockchip_gpio_irq_mask,
2760         .irq_mask       = rockchip_gpio_irq_mask,
2761         .irq_unmask     = rockchip_gpio_irq_unmask,
2762         .irq_set_type   = rockchip_gpio_irq_set_type,
2763         .irq_set_wake   = rockchip_gpio_irq_set_wake,
2764 };
2765
2766
2767 static int rockchip_gpio_irq_map(struct irq_domain *d, unsigned int irq,
2768                                 irq_hw_number_t hwirq)
2769 {
2770         struct rockchip_pin_bank *bank = d->host_data;
2771         struct rockchip_pinctrl *info = bank->drvdata;
2772         struct irq_data *irq_data = irq_get_irq_data(irq);
2773         int pin = hwirq;
2774
2775         if (!bank)
2776         {
2777                 printk("%s:bank=0x%p,irq=%d\n",__func__,bank, irq);
2778                 return -EINVAL;
2779         }
2780
2781         irq_set_chip_and_handler(irq, &rockchip_gpio_irq_chip, handle_level_irq);
2782         irq_set_chip_data(irq, bank);
2783         set_irq_flags(irq, IRQF_VALID);
2784
2785         irq_data->hwirq = hwirq;
2786         irq_data->irq = irq;
2787
2788         DBG_PINCTRL("%s:irq=%d\n",__func__,irq);
2789         return 0;
2790 }
2791
2792 const struct irq_domain_ops rockchip_gpio_irq_ops = {
2793         .map = rockchip_gpio_irq_map,
2794         .xlate = irq_domain_xlate_twocell,
2795 };
2796
2797
2798 static int rockchip_interrupts_register(struct platform_device *pdev,
2799                                                 struct rockchip_pinctrl *info)
2800 {
2801         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2802         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2803         //unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2804         int i;
2805
2806         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2807                 if (!bank->valid) {
2808                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2809                                  bank->name);
2810                         continue;
2811                 }
2812
2813                 __raw_writel(0, bank->reg_base + GPIO_INTEN);
2814
2815                 bank->drvdata = info;
2816                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2817                                 &rockchip_gpio_irq_ops, bank);
2818                 if (!bank->domain) {
2819                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2820                                  bank->name);
2821                         continue;
2822                 }
2823
2824                 if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
2825                 printk("%s:bank_num=%d\n",__func__,bank->bank_num);
2826
2827                 irq_set_handler_data(bank->irq, bank);
2828                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
2829         }
2830
2831
2832         return 0;
2833 }
2834
2835
2836 static int rockchip_gpiolib_register(struct platform_device *pdev,
2837                                                 struct rockchip_pinctrl *info)
2838 {
2839         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2840         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2841         struct gpio_chip *gc;
2842         int ret;
2843         int i;
2844
2845         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2846                 if (!bank->valid) {
2847                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2848                                  bank->name);
2849                         continue;
2850                 }
2851
2852                 bank->gpio_chip = rockchip_gpiolib_chip;
2853
2854                 gc = &bank->gpio_chip;
2855                 gc->base = bank->pin_base;
2856                 gc->ngpio = bank->nr_pins;
2857                 gc->dev = &pdev->dev;
2858                 gc->of_node = bank->of_node;
2859                 gc->label = bank->name;
2860
2861                 ret = gpiochip_add(gc);
2862                 if (ret) {
2863                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2864                                                         gc->label, ret);
2865                         goto fail;
2866                 }
2867         }
2868
2869         rockchip_interrupts_register(pdev, info);
2870
2871         return 0;
2872
2873 fail:
2874         for (--i, --bank; i >= 0; --i, --bank) {
2875                 if (!bank->valid)
2876                         continue;
2877
2878                 if (gpiochip_remove(&bank->gpio_chip))
2879                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
2880                                                         bank->gpio_chip.label);
2881         }
2882         return ret;
2883 }
2884
2885 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2886                                                 struct rockchip_pinctrl *info)
2887 {
2888         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2889         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2890         int ret = 0;
2891         int i;
2892
2893         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
2894                 if (!bank->valid)
2895                         continue;
2896
2897                 ret = gpiochip_remove(&bank->gpio_chip);
2898         }
2899
2900         if (ret)
2901                 dev_err(&pdev->dev, "gpio chip remove failed\n");
2902
2903         return ret;
2904 }
2905
2906 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2907                                   struct device *dev)
2908 {
2909         struct resource res;
2910         int rk3188 = 0, rk3288 = 0;
2911
2912         //"base", "mux_bank0", "pull_bank0", "drv_bank0"
2913         if (of_address_to_resource(bank->of_node, 0, &res)) {
2914                 dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2915                 return -ENOENT;
2916         }
2917         bank->reg_base = devm_ioremap_resource(dev, &res);
2918         if (IS_ERR(bank->reg_base))
2919                 return PTR_ERR(bank->reg_base);
2920
2921         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2922
2923         /*
2924          * special case, where parts of the pull setting-registers are
2925          * part of the PMU register space
2926          */
2927         rk3188 = of_device_is_compatible(bank->of_node, "rockchip,rk3188-gpio-bank0");
2928
2929         rk3288 = of_device_is_compatible(bank->of_node, "rockchip,rk3288-gpio-bank0");
2930
2931         if(rk3188)
2932         {
2933                 bank->bank_type = RK3188_BANK0;
2934
2935                 if (of_address_to_resource(bank->of_node, 1, &res)) {
2936                         dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2937                         return -ENOENT;
2938                 }
2939                 bank->reg_pull_bank0 = devm_ioremap_resource(dev, &res);
2940                 if (IS_ERR(bank->reg_pull_bank0))
2941                 return PTR_ERR(bank->reg_pull_bank0);
2942
2943                 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2944
2945         }
2946         else if (rk3288)
2947         {
2948                 bank->bank_type = RK3288_BANK0;
2949                 if (of_address_to_resource(bank->of_node, 1, &res)) {
2950                         dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2951                         return -ENOENT;
2952                 }
2953                 bank->reg_mux_bank0 = devm_ioremap_resource(dev, &res);
2954                 if (IS_ERR(bank->reg_mux_bank0))
2955                 return PTR_ERR(bank->reg_mux_bank0);
2956
2957                 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2958
2959                 if (of_address_to_resource(bank->of_node, 2, &res)) {
2960                         dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2961                         return -ENOENT;
2962                 }
2963                 bank->reg_pull_bank0 = devm_ioremap_resource(dev, &res);
2964                 if (IS_ERR(bank->reg_pull_bank0))
2965                 return PTR_ERR(bank->reg_pull_bank0);
2966
2967                 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2968
2969                 if (of_address_to_resource(bank->of_node, 3, &res)) {
2970                         dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2971                         return -ENOENT;
2972                 }
2973                 bank->reg_drv_bank0 = devm_ioremap_resource(dev, &res);
2974                 if (IS_ERR(bank->reg_drv_bank0))
2975                 return PTR_ERR(bank->reg_drv_bank0);
2976
2977                 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2978
2979         }
2980         else
2981         {
2982                 bank->bank_type = COMMON_BANK;
2983         }
2984
2985         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2986
2987         bank->clk = of_clk_get(bank->of_node, 0);
2988         if (IS_ERR(bank->clk)) {
2989                 dev_warn(dev, "failed to get clk for bank %s\n", bank->name);
2990                 bank->clk = NULL;
2991         }
2992         clk_prepare_enable(bank->clk);
2993         return 0;
2994 }
2995
2996 static const struct of_device_id rockchip_pinctrl_dt_match[];
2997
2998 /* retrieve the soc specific data */
2999 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3000                                                 struct rockchip_pinctrl *d,
3001                                                 struct platform_device *pdev)
3002 {
3003         const struct of_device_id *match;
3004         struct device_node *node = pdev->dev.of_node;
3005         struct device_node *np;
3006         struct rockchip_pin_ctrl *ctrl;
3007         struct rockchip_pin_bank *bank;
3008         int i;
3009
3010         match = of_match_node(rockchip_pinctrl_dt_match, node);
3011         ctrl = (struct rockchip_pin_ctrl *)match->data;
3012
3013         for_each_child_of_node(node, np) {
3014                 if (!of_find_property(np, "gpio-controller", NULL))
3015                         continue;
3016
3017                 bank = ctrl->pin_banks;
3018                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3019                         if (!strcmp(bank->name, np->name)) {
3020                                 bank->of_node = np;
3021
3022                                 if (!rockchip_get_bank_data(bank, &pdev->dev))
3023                                         bank->valid = true;
3024                                 break;
3025                         }
3026                 }
3027         }
3028
3029         bank = ctrl->pin_banks;
3030         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3031                 spin_lock_init(&bank->slock);
3032                 bank->drvdata = d;
3033                 bank->pin_base = ctrl->nr_pins;
3034                 ctrl->nr_pins += bank->nr_pins;
3035         }
3036
3037         return ctrl;
3038 }
3039
3040
3041 #ifdef CONFIG_PM
3042 static int rockchip_pinctrl_suspend(void)
3043 {
3044         struct rockchip_pinctrl *info = g_info;
3045         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3046         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3047         int n;
3048         //int value = 0;
3049
3050         for(n=0; n<ctrl->nr_banks-1; n++)
3051         {
3052 #if 0
3053                 int i;
3054                 for(i=0; i<0x60; i=i+4)
3055                 {
3056                         value = readl_relaxed(bank->reg_base + i);
3057                         printk("%s:bank_num=%d,reg[0x%x+0x%x]=0x%x,bank_name=%s\n",__func__,bank->bank_num, bank->reg_base, i, value, bank->name);
3058                 }
3059 #endif
3060                 bank->saved_wakeup = __raw_readl(bank->reg_base + GPIO_INTEN);
3061                 __raw_writel(bank->suspend_wakeup, bank->reg_base + GPIO_INTEN);
3062
3063                 if (!bank->suspend_wakeup)
3064                 clk_disable_unprepare(bank->clk);
3065
3066                 if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
3067                 printk("%s:bank_num=%d, suspend_wakeup=0x%x\n",__func__, bank->bank_num, bank->suspend_wakeup);
3068                 bank++;
3069         }
3070
3071
3072         return 0;
3073 }
3074
3075 static void rockchip_pinctrl_resume(void)
3076 {
3077         struct rockchip_pinctrl *info = g_info;
3078         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3079         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3080         int n;
3081         u32 isr;
3082
3083         for(n=0; n<ctrl->nr_banks-1; n++)
3084         {
3085 #if 0
3086                 int i;
3087                 for(i=0; i<0x60; i=i+4)
3088                 {
3089                         u32 value = readl_relaxed(bank->reg_base + i);
3090                         printk("%s:bank_num=%d,reg[0x%x+0x%x]=0x%x,bank_name=%s\n",__func__,bank->bank_num, bank->reg_base, i, value, bank->name);
3091                 }
3092 #endif
3093                 if (!bank->suspend_wakeup)
3094                 clk_prepare_enable(bank->clk);
3095
3096                 /* keep enable for resume irq */
3097                  isr = __raw_readl(bank->reg_base + GPIO_INT_STATUS);
3098                 __raw_writel(bank->saved_wakeup | (bank->suspend_wakeup & isr), bank->reg_base + GPIO_INTEN);
3099
3100                 if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
3101                 printk("%s:bank_num=%d, suspend_wakeup=0x%x\n",__func__, bank->bank_num, bank->saved_wakeup | (bank->suspend_wakeup & isr));
3102
3103                 bank++;
3104         }
3105
3106 }
3107
3108 #endif
3109
3110
3111 static struct gpio_init_config *
3112 of_get_gpio_init_config(struct device *dev, struct device_node *np)
3113 {
3114         struct gpio_init_config *config;
3115         int gpio, i;
3116         enum of_gpio_flags flags;
3117
3118         config = devm_kzalloc(dev,
3119                         sizeof(struct gpio_init_config),
3120                         GFP_KERNEL);
3121         if (!config)
3122                 return ERR_PTR(-ENOMEM);
3123
3124         /* Fetch GPIOs. */
3125         config->nr_gpios = of_gpio_named_count(np, "init-gpios");
3126
3127         config->gpios = devm_kzalloc(dev,
3128                                 sizeof(struct gpio) * config->nr_gpios,
3129                                 GFP_KERNEL);
3130         if (!config->gpios)
3131                 return ERR_PTR(-ENOMEM);
3132
3133         for (i = 0; i < config->nr_gpios; i++) {
3134                 //gpio = of_get_named_gpio(np, "gpios", i);
3135                 gpio = of_get_named_gpio_flags(np, "init-gpios", i, &flags);
3136                 if (gpio < 0)
3137                         break;
3138                 config->gpios[i].gpio = gpio;
3139                 config->gpios[i].flags = flags & OF_GPIO_ACTIVE_LOW;
3140
3141                 printk("%s:gpio[%d] = %d, value = %lu\n",__func__, i, gpio, config->gpios[i].flags);
3142         }
3143
3144         return config;
3145 }
3146
3147
3148 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3149 {
3150         struct rockchip_pinctrl *info;
3151         struct device *dev = &pdev->dev;
3152         struct rockchip_pin_ctrl *ctrl;
3153         struct resource *res;
3154         int ret;
3155         struct device_node *np;
3156         int i;
3157
3158         if (!dev->of_node) {
3159                 dev_err(dev, "device tree node not found\n");
3160                 return -ENODEV;
3161         }
3162
3163         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
3164         if (!info)
3165                 return -ENOMEM;
3166
3167         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3168         if (!ctrl) {
3169                 dev_err(dev, "driver data not available\n");
3170                 return -EINVAL;
3171         }
3172         info->ctrl = ctrl;
3173         info->dev = dev;
3174
3175         g_info = info;
3176
3177         /*if debug GPIO0 then
3178         *atomic_set(&info->bank_debug_flag, 1);
3179         *atomic_set(&info->pin_debug_flag, 0);
3180         *if debug GPIO0-10 then
3181         *atomic_set(&info->bank_debug_flag, 1);
3182         *atomic_set(&info->pin_debug_flag, 11);
3183         */
3184         atomic_set(&info->bank_debug_flag, 8);
3185         atomic_set(&info->pin_debug_flag, 14);
3186
3187         printk("%s:name=%s,type=%d\n",__func__, ctrl->label, (int)ctrl->type);
3188
3189         //"base", "mux", "pull", "drv";
3190         switch(ctrl->type)
3191         {
3192                 case RK2928:
3193                 case RK3066B:
3194                         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3195                         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
3196                         if (IS_ERR(info->reg_base))
3197                         return PTR_ERR(info->reg_base);
3198                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3199                         break;
3200
3201                 case RK3188:
3202                 case RK3036:
3203                 case RK312X:
3204                         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3205                         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
3206                         if (IS_ERR(info->reg_base))
3207                         return PTR_ERR(info->reg_base);
3208                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3209
3210                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3211                         info->reg_mux = devm_ioremap_resource(&pdev->dev, res);
3212                         if (IS_ERR(info->reg_mux))
3213                         return PTR_ERR(info->reg_mux);
3214                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3215
3216                         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
3217                         info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
3218                         if (IS_ERR(info->reg_pull))
3219                         return PTR_ERR(info->reg_pull);
3220                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3221
3222                         res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
3223                         info->reg_drv = devm_ioremap_resource(&pdev->dev, res);
3224                         if (IS_ERR(info->reg_drv))
3225                         return PTR_ERR(info->reg_drv);
3226                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3227
3228                         break;
3229
3230                 case RK3288:
3231                         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3232                         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
3233                         if (IS_ERR(info->reg_base))
3234                         return PTR_ERR(info->reg_base);
3235                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3236
3237                         info->reg_mux = info->reg_base;
3238
3239                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3240                         info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
3241                         if (IS_ERR(info->reg_pull))
3242                         return PTR_ERR(info->reg_pull);
3243                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3244
3245                         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
3246                         info->reg_drv = devm_ioremap_resource(&pdev->dev, res);
3247                         if (IS_ERR(info->reg_drv))
3248                         return PTR_ERR(info->reg_drv);
3249                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3250
3251                         break;
3252
3253                 default:
3254                         printk("%s:unknown chip type %d\n",__func__, (int)ctrl->type);
3255                         return -1;
3256
3257         }
3258
3259
3260         ret = rockchip_gpiolib_register(pdev, info);
3261         if (ret)
3262                 return ret;
3263
3264         ret = rockchip_pinctrl_register(pdev, info);
3265         if (ret) {
3266                 rockchip_gpiolib_unregister(pdev, info);
3267                 return ret;
3268         }
3269
3270         np = dev->of_node;
3271         if (of_find_property(np, "init-gpios", NULL))
3272         {
3273                 info->config = of_get_gpio_init_config(&pdev->dev, np);
3274                 if (IS_ERR(info->config))
3275                 return PTR_ERR(info->config);
3276
3277                 ret = gpio_request_array(info->config->gpios, info->config->nr_gpios);
3278                 if (ret) {
3279                         dev_err(&pdev->dev, "Could not obtain init GPIOs: %d\n", ret);
3280                         return ret;
3281                 }
3282
3283                 for(i=0; i<info->config->nr_gpios; i++)
3284                 {
3285                         gpio_direction_output(info->config->gpios[i].gpio, info->config->gpios[i].flags);
3286                 }
3287         }
3288
3289         pinctrl_debugfs_init(info);
3290
3291         platform_set_drvdata(pdev, info);
3292
3293         printk("%s:init ok\n",__func__);
3294         return 0;
3295 }
3296
3297 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3298         PIN_BANK(0, 32, "gpio0"),
3299         PIN_BANK(1, 32, "gpio1"),
3300         PIN_BANK(2, 32, "gpio2"),
3301         PIN_BANK(3, 32, "gpio3"),
3302
3303         PIN_BANK(15, 32, "gpio15"),//virtual bank
3304 };
3305
3306 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3307                 .pin_banks              = rk2928_pin_banks,
3308                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
3309                 .label                  = "RK2928-GPIO",
3310                 .type                   = RK2928,
3311                 .mux_offset             = 0xa8,
3312                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3313 };
3314
3315 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3316         PIN_BANK(0, 32, "gpio0"),
3317         PIN_BANK(1, 32, "gpio1"),
3318         PIN_BANK(2, 32, "gpio2"),
3319         PIN_BANK(3, 32, "gpio3"),
3320         PIN_BANK(4, 32, "gpio4"),
3321         PIN_BANK(6, 16, "gpio6"),
3322         PIN_BANK(15, 32, "gpio15"),//virtual bank
3323 };
3324
3325 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3326                 .pin_banks              = rk3066a_pin_banks,
3327                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
3328                 .label                  = "RK3066a-GPIO",
3329                 .type                   = RK2928,
3330                 .mux_offset             = 0xa8,
3331                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3332 };
3333
3334 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3335         PIN_BANK(0, 32, "gpio0"),
3336         PIN_BANK(1, 32, "gpio1"),
3337         PIN_BANK(2, 32, "gpio2"),
3338         PIN_BANK(3, 32, "gpio3"),
3339
3340         PIN_BANK(15, 32, "gpio15"),//virtual bank
3341 };
3342
3343 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3344                 .pin_banks      = rk3066b_pin_banks,
3345                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
3346                 .label          = "RK3066b-GPIO",
3347                 .type           = RK3066B,
3348                 .mux_offset     = 0x60,
3349 };
3350
3351 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3352         PIN_BANK(0, 32, "gpio0"),
3353         PIN_BANK(1, 32, "gpio1"),
3354         PIN_BANK(2, 32, "gpio2"),
3355         PIN_BANK(3, 32, "gpio3"),
3356
3357         PIN_BANK(15, 32, "gpio15"),//virtual bank
3358 };
3359
3360 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3361                 .pin_banks              = rk3188_pin_banks,
3362                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
3363                 .label                  = "RK3188-GPIO",
3364                 .type                   = RK3188,
3365                 .mux_offset             = 0x60,
3366                 .pull_calc_reg  = rk3188_calc_pull_reg_and_bit,
3367 };
3368
3369
3370 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3371         PIN_BANK(0, 32, "gpio0"),
3372         PIN_BANK(1, 32, "gpio1"),
3373         PIN_BANK(2, 32, "gpio2"),
3374         PIN_BANK(3, 32, "gpio3"),
3375         PIN_BANK(4, 32, "gpio4"),
3376         PIN_BANK(5, 32, "gpio5"),
3377         PIN_BANK(6, 32, "gpio6"),
3378         PIN_BANK(7, 32, "gpio7"),
3379         PIN_BANK(8, 32, "gpio8"),
3380
3381
3382         PIN_BANK(15, 32, "gpio15"),//virtual bank
3383 };
3384
3385 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3386                 .pin_banks              = rk3288_pin_banks,
3387                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3388                 .label                  = "RK3288-GPIO",
3389                 .type                   = RK3288,
3390                 .mux_offset             = 0x0,
3391                 .pull_calc_reg  = rk3288_calc_pull_reg_and_bit,
3392                 .drv_calc_reg   = rk3288_calc_drv_reg_and_bit,
3393 };
3394
3395
3396 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3397         PIN_BANK(0, 32, "gpio0"),
3398         PIN_BANK(1, 32, "gpio1"),
3399         PIN_BANK(2, 32, "gpio2"),
3400
3401         PIN_BANK(15, 32, "gpio15"),//virtual bank
3402 };
3403
3404 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3405                 .pin_banks              = rk3036_pin_banks,
3406                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
3407                 .label                  = "rk3036-GPIO",
3408                 .type                   = RK3036,
3409                 .mux_offset             = 0xa8,
3410                 .pull_calc_reg  = rk3036_calc_pull_reg_and_bit,
3411 };
3412
3413
3414 static struct rockchip_pin_bank rk312x_pin_banks[] = {
3415         PIN_BANK(0, 32, "gpio0"),
3416         PIN_BANK(1, 32, "gpio1"),
3417         PIN_BANK(2, 32, "gpio2"),
3418         PIN_BANK(3, 32, "gpio3"),
3419
3420         PIN_BANK(15, 32, "gpio15"),//virtual bank
3421 };
3422
3423 static struct rockchip_pin_ctrl rk312x_pin_ctrl = {
3424                 .pin_banks              = rk312x_pin_banks,
3425                 .nr_banks               = ARRAY_SIZE(rk312x_pin_banks),
3426                 .label                  = "rk312x-GPIO",
3427                 .type                   = RK312X,
3428                 .mux_offset             = 0xa8,
3429                 .pull_calc_reg  = rk312x_calc_pull_reg_and_bit,
3430 };
3431
3432
3433
3434 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3435         { .compatible = "rockchip,rk2928-pinctrl",
3436                 .data = (void *)&rk2928_pin_ctrl },
3437         { .compatible = "rockchip,rk3066a-pinctrl",
3438                 .data = (void *)&rk3066a_pin_ctrl },
3439         { .compatible = "rockchip,rk3066b-pinctrl",
3440                 .data = (void *)&rk3066b_pin_ctrl },
3441         { .compatible = "rockchip,rk3188-pinctrl",
3442                 .data = (void *)&rk3188_pin_ctrl },
3443         { .compatible = "rockchip,rk3288-pinctrl",
3444                 .data = (void *)&rk3288_pin_ctrl },
3445         { .compatible = "rockchip,rk3036-pinctrl",
3446                 .data = (void *)&rk3036_pin_ctrl },
3447         { .compatible = "rockchip,rk312x-pinctrl",
3448                 .data = (void *)&rk312x_pin_ctrl },
3449         {},
3450 };
3451 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
3452
3453 static struct platform_driver rockchip_pinctrl_driver = {
3454         .probe          = rockchip_pinctrl_probe,
3455         .driver = {
3456                 .name   = "rockchip-pinctrl",
3457                 .owner  = THIS_MODULE,
3458                 .of_match_table = rockchip_pinctrl_dt_match,
3459         },
3460 };
3461
3462 #ifdef CONFIG_PM
3463 static struct syscore_ops rockchip_gpio_syscore_ops = {
3464         .suspend        = rockchip_pinctrl_suspend,
3465         .resume         = rockchip_pinctrl_resume,
3466 };
3467 #endif
3468
3469 static int __init rockchip_pinctrl_drv_register(void)
3470 {
3471 #ifdef CONFIG_PM
3472         register_syscore_ops(&rockchip_gpio_syscore_ops);
3473 #endif
3474         return platform_driver_register(&rockchip_pinctrl_driver);
3475 }
3476 postcore_initcall(rockchip_pinctrl_drv_register);
3477
3478 MODULE_AUTHOR("Luo Wei <lw@rock-chips.com>");
3479 MODULE_DESCRIPTION("Rockchip pinctrl driver");
3480 MODULE_LICENSE("GPL v2");