drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/irq.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of_address.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/pinctrl/machine.h>
  36 #include <linux/pinctrl/pinconf.h>
  37 #include <linux/pinctrl/pinctrl.h>
  38 #include <linux/pinctrl/pinmux.h>
  39 #include <linux/pinctrl/pinconf-generic.h>
  40 #include <linux/irqchip/chained_irq.h>
  41 #include <linux/clk.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43 #include <dt-bindings/pinctrl/rockchip-rk3188.h>
  44
  45
  46 #include <linux/of.h>
  47 #include <linux/of_device.h>
  48 #include <linux/pinctrl/consumer.h>
  49 #include <linux/slab.h>
  50
  51
  52 #include "core.h"
  53 #include "pinconf.h"
  54
  55
  56 #if 1
  57 #define DBG_PINCTRL(x...)  if(atomic_read(&info->debug_flag) == 1) printk(x)
  58 #else
  59 #define DBG_PINCTRL(x...)
  60 #endif
  61
  62
  63 /* GPIO control registers */
  64 #define GPIO_SWPORT_DR          0x00
  65 #define GPIO_SWPORT_DDR         0x04
  66 #define GPIO_INTEN              0x30
  67 #define GPIO_INTMASK            0x34
  68 #define GPIO_INTTYPE_LEVEL      0x38
  69 #define GPIO_INT_POLARITY       0x3c
  70 #define GPIO_INT_STATUS         0x40
  71 #define GPIO_INT_RAWSTATUS      0x44
  72 #define GPIO_DEBOUNCE           0x48
  73 #define GPIO_PORTS_EOI          0x4c
  74 #define GPIO_EXT_PORT           0x50
  75 #define GPIO_LS_SYNC            0x60
  76
  77 enum rockchip_pinctrl_type {
  78         RK2928,
  79         RK3066B,
  80         RK3188,
  81 };
  82
  83 enum rockchip_pin_bank_type {
  84         COMMON_BANK,
  85         RK3188_BANK0,
  86 };
  87
  88 /**
  89  * @reg_base: register base of the gpio bank
  90  * @reg_pull: optional separate register for additional pull settings
  91  * @clk: clock of the gpio bank
  92  * @irq: interrupt of the gpio bank
  93  * @pin_base: first pin number
  94  * @nr_pins: number of pins in this bank
  95  * @name: name of the bank
  96  * @bank_num: number of the bank, to account for holes
  97  * @valid: are all necessary informations present
  98  * @of_node: dt node of this bank
  99  * @drvdata: common pinctrl basedata
 100  * @domain: irqdomain of the gpio bank
 101  * @gpio_chip: gpiolib chip
 102  * @grange: gpio range
 103  * @slock: spinlock for the gpio bank
 104  */
 105 struct rockchip_pin_bank {
 106         void __iomem                    *reg_base;
 107         void __iomem                    *reg_pull;
 108         struct clk                      *clk;
 109         int                             irq;
 110         u32                             pin_base;
 111         u8                              nr_pins;
 112         char                            *name;
 113         u8                              bank_num;
 114         enum rockchip_pin_bank_type     bank_type;
 115         bool                            valid;
 116         struct device_node              *of_node;
 117         struct rockchip_pinctrl         *drvdata;
 118         struct irq_domain               *domain;
 119         struct gpio_chip                gpio_chip;
 120         struct pinctrl_gpio_range       grange;
 121         spinlock_t                      slock;
 122         u32                             toggle_edge_mode;
 123         u32                             suspend_wakeup;
 124         u32                             saved_wakeup;
 125 };
 126
 127 #define PIN_BANK(id, pins, label)                       \
 128         {                                               \
 129                 .bank_num       = id,                   \
 130                 .nr_pins        = pins,                 \
 131                 .name           = label,                \
 132         }
 133
 134 /**
 135  */
 136 struct rockchip_pin_ctrl {
 137         struct rockchip_pin_bank        *pin_banks;
 138         u32                             nr_banks;
 139         u32                             nr_pins;
 140         char                            *label;
 141         enum rockchip_pinctrl_type      type;
 142         int                             mux_offset;
 143         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
 144                                  void __iomem **reg, u8 *bit);
 145 };
 146
 147 struct rockchip_pin_config {
 148         unsigned int            func;
 149         unsigned long           *configs;
 150         unsigned int            nconfigs;
 151 };
 152
 153 /**
 154  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 155  * @name: name of the pin group, used to lookup the group.
 156  * @pins: the pins included in this group.
 157  * @npins: number of pins included in this group.
 158  * @func: the mux function number to be programmed when selected.
 159  * @configs: the config values to be set for each pin
 160  * @nconfigs: number of configs for each pin
 161  */
 162 struct rockchip_pin_group {
 163         const char                      *name;
 164         const char                      *func_name;
 165         unsigned int                    npins;
 166         unsigned int                    *pins;
 167         struct rockchip_pin_config      *data;
 168 };
 169
 170 /**
 171  * struct rockchip_pmx_func: represent a pin function.
 172  * @name: name of the pin function, used to lookup the function.
 173  * @groups: one or more names of pin groups that provide this function.
 174  * @num_groups: number of groups included in @groups.
 175  */
 176 struct rockchip_pmx_func {
 177         const char              *name;
 178         const char              **groups;
 179         u8                      ngroups;
 180 };
 181
 182 struct rockchip_pinctrl {
 183         void __iomem                    *reg_base;
 184         void __iomem                    *reg_pull;
 185         struct device                   *dev;
 186         struct rockchip_pin_ctrl        *ctrl;
 187         struct pinctrl_desc             pctl;
 188         struct pinctrl_dev              *pctl_dev;
 189         struct rockchip_pin_group       *groups;
 190         unsigned int                    ngroups;
 191         struct rockchip_pmx_func        *functions;
 192         unsigned int                    nfunctions;
 193
 194         atomic_t                        debug_flag;
 195 };
 196
 197 struct iomux_mode{
 198         unsigned int mode:4,
 199                      off:4,
 200                      goff:4,
 201                      bank:4,
 202                      reserve:16;
 203 };
 204
 205 struct union_mode{
 206         union{
 207                 struct iomux_mode mux;
 208                 unsigned int mode;
 209         };
 210 };
 211
 212 struct func_to_reg_offset {
 213         unsigned int reg_type;
 214         const char *func_name;
 215         unsigned int reg_offset;
 216         unsigned int bit_offset;
 217         unsigned int bit_mask;
 218 };
 219
 220 #define FUNC_TO_REG_OFFSET(type, label, reg, bit, mask) \
 221         {                                               \
 222                 .reg_type       = type,         \
 223                 .func_name      = label,        \
 224                 .reg_offset     = reg,          \
 225                 .bit_offset     = bit,          \
 226                 .bit_mask       = mask,         \
 227         }
 228
 229
 230
 231 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 232 {
 233         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 234 }
 235
 236 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 237                                         const struct rockchip_pinctrl *info,
 238                                         const char *name)
 239 {
 240         int i;
 241
 242         for (i = 0; i < info->ngroups; i++) {
 243                 if (!strcmp(info->groups[i].name, name))
 244                         return &info->groups[i];
 245         }
 246
 247         return NULL;
 248 }
 249
 250 /*
 251  * given a pin number that is local to a pin controller, find out the pin bank
 252  * and the register base of the pin bank.
 253  */
 254 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 255                                                                 unsigned pin)
 256 {
 257         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 258
 259         while (pin >= (b->pin_base + b->nr_pins))
 260                 b++;
 261
 262         return b;
 263 }
 264
 265 static struct rockchip_pin_bank *bank_num_to_bank(
 266                                         struct rockchip_pinctrl *info,
 267                                         unsigned num)
 268 {
 269         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 270         int i;
 271
 272         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 273                 if (b->bank_num == num)
 274                         return b;
 275         }
 276
 277         return ERR_PTR(-EINVAL);
 278 }
 279
 280 /*
 281  * Pinctrl_ops handling
 282  */
 283
 284 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 285 {
 286         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 287
 288         return info->ngroups;
 289 }
 290
 291 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 292                                                         unsigned selector)
 293 {
 294         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 295
 296         return info->groups[selector].name;
 297 }
 298
 299 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 300                                       unsigned selector, const unsigned **pins,
 301                                       unsigned *npins)
 302 {
 303         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 304
 305         if (selector >= info->ngroups)
 306                 return -EINVAL;
 307
 308         *pins = info->groups[selector].pins;
 309         *npins = info->groups[selector].npins;
 310
 311         return 0;
 312 }
 313
 314 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 315                                  struct device_node *np,
 316                                  struct pinctrl_map **map, unsigned *num_maps)
 317 {
 318         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 319         const struct rockchip_pin_group *grp;
 320         struct pinctrl_map *new_map;
 321         struct device_node *parent;
 322         int map_num = 1;
 323         int i;
 324
 325         /*
 326          * first find the group of this node and check if we need to create
 327          * config maps for pins
 328          */
 329         grp = pinctrl_name_to_group(info, np->name);
 330         if (!grp) {
 331                 dev_err(info->dev, "unable to find group for node %s\n",
 332                         np->name);
 333                 return -EINVAL;
 334         }
 335
 336         map_num += grp->npins;
 337         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 338                                                                 GFP_KERNEL);
 339         if (!new_map)
 340                 return -ENOMEM;
 341
 342         *map = new_map;
 343         *num_maps = map_num;
 344
 345         /* create mux map */
 346         parent = of_get_parent(np);
 347         if (!parent) {
 348                 devm_kfree(pctldev->dev, new_map);
 349                 return -EINVAL;
 350         }
 351         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 352         new_map[0].data.mux.function = parent->name;
 353         new_map[0].data.mux.group = np->name;
 354         of_node_put(parent);
 355
 356         /* create config map */
 357         new_map++;
 358         for (i = 0; i < grp->npins; i++) {
 359                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 360                 new_map[i].data.configs.group_or_pin = grp->name;
 361                                 //pin_get_name(pctldev, grp->pins[i]);
 362                 new_map[i].data.configs.configs = grp->data[i].configs;
 363                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 364         }
 365
 366         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 367                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 368
 369         return 0;
 370 }
 371
 372 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 373                                     struct pinctrl_map *map, unsigned num_maps)
 374 {
 375 }
 376
 377 static const struct pinctrl_ops rockchip_pctrl_ops = {
 378         .get_groups_count       = rockchip_get_groups_count,
 379         .get_group_name         = rockchip_get_group_name,
 380         .get_group_pins         = rockchip_get_group_pins,
 381         .dt_node_to_map         = rockchip_dt_node_to_map,
 382         .dt_free_map            = rockchip_dt_free_map,
 383 };
 384
 385
 386
 387 /*
 388  * Set a new mux function for a pin.
 389  *
 390  * The register is divided into the upper and lower 16 bit. When changing
 391  * a value, the previous register value is not read and changed. Instead
 392  * it seems the changed bits are marked in the upper 16 bit, while the
 393  * changed value gets set in the same offset in the lower 16 bit.
 394  * All pin settings seem to be 2 bit wide in both the upper and lower
 395  * parts.
 396  * @bank: pin bank to change
 397  * @pin: pin to change
 398  * @mux: new mux function to set
 399  */
 400 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 401 {
 402         struct rockchip_pinctrl *info = bank->drvdata;
 403         void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 404         unsigned long flags;
 405         u8 bit;
 406         u32 data;
 407         struct union_mode m;
 408
 409         /* GPIO0_C */
 410         /*GPIO0_C0 = 0x0c00, NAND_D8, */
 411         /*GPIO0_C1 = 0x0c10, NAND_D9, */
 412
 413         m.mode = mux;
 414
 415         if((m.mux.bank != bank->bank_num) || (((m.mux.goff - 0x0A) * 8 + m.mux.off ) != pin))
 416         {
 417                 printk("%s:error:mux_bank(%d) != gpio_bank(%d), mux_offset(%d) != gpio_offset(%d)\n",__func__,
 418                 m.mux.bank, bank->bank_num, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), pin);
 419                 return;
 420         }
 421
 422         /* get basic quadrupel of mux registers and the correct reg inside */
 423         reg += bank->bank_num * 0x10;
 424         reg += (pin / 8) * 4;
 425         bit = (pin % 8) * 2;
 426
 427         spin_lock_irqsave(&bank->slock, flags);
 428
 429         data = (3 << (bit + 16));
 430         data |= (mux & 3) << bit;
 431         writel(data, reg);
 432
 433         spin_unlock_irqrestore(&bank->slock, flags);
 434
 435         DBG_PINCTRL("%s:setting GPIO%d-%d to mux:0x%x\n", __func__, m.mux.bank, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), mux);
 436
 437         //DBG_PINCTRL("%s:setting mux of GPIO%d-%d to %d\n", __func__, bank->bank_num, pin, mux&0x3);
 438 }
 439
 440
 441 /*
 442  * Pinmux_ops handling
 443  */
 444
 445 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 446 {
 447         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 448
 449         return info->nfunctions;
 450 }
 451
 452 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 453                                           unsigned selector)
 454 {
 455         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 456
 457         return info->functions[selector].name;
 458 }
 459
 460 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 461                                 unsigned selector, const char * const **groups,
 462                                 unsigned * const num_groups)
 463 {
 464         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 465
 466         *groups = info->functions[selector].groups;
 467         *num_groups = info->functions[selector].ngroups;
 468
 469         return 0;
 470 }
 471
 472 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 473                                                             unsigned group)
 474 {
 475         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 476         const unsigned int *pins = info->groups[group].pins;
 477         const struct rockchip_pin_config *data = info->groups[group].data;
 478         struct rockchip_pin_bank *bank;
 479         int cnt;
 480
 481         DBG_PINCTRL("%s:enable function %s group %s\n",
 482                 __func__, info->functions[selector].name, info->groups[group].name);
 483
 484         /*
 485          * for each pin in the pin group selected, program the correspoding pin
 486          * pin function number in the config register.
 487          */
 488         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 489                 bank = pin_to_bank(info, pins[cnt]);
 490                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 491                                  data[cnt].func);
 492         }
 493
 494         return 0;
 495 }
 496
 497 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 498                                         unsigned selector, unsigned group)
 499 {
 500         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 501         const unsigned int *pins = info->groups[group].pins;
 502         struct rockchip_pin_bank *bank;
 503         int cnt;
 504
 505         DBG_PINCTRL("%s:disable function %s group %s\n",
 506                 __func__, info->functions[selector].name, info->groups[group].name);
 507
 508         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 509                 bank = pin_to_bank(info, pins[cnt]);
 510                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 511         }
 512 }
 513
 514 /*
 515  * The calls to gpio_direction_output() and gpio_direction_input()
 516  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 517  * function called from the gpiolib interface).
 518  */
 519 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 520                                               struct pinctrl_gpio_range *range,
 521                                               unsigned offset, bool input)
 522 {
 523         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 524         struct rockchip_pin_bank *bank;
 525         struct gpio_chip *chip;
 526         int pin;
 527         u32 data;
 528         u32 mux;
 529
 530         chip = range->gc;
 531         bank = gc_to_pin_bank(chip);
 532         pin = offset - chip->base;
 533
 534         DBG_PINCTRL("%s:gpio_direction for pin %u as %s-%d to %s\n",
 535                  __func__, offset, range->name, pin, input ? "input" : "output");
 536
 537         mux = (bank->bank_num << 12) | (((pin / 8) + 0x0A) << 8) | ((pin % 8)<< 4) | RK_FUNC_GPIO;
 538
 539         rockchip_set_mux(bank, pin, mux);
 540
 541         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 542         /* set bit to 1 for output, 0 for input */
 543         if (!input)
 544                 data |= BIT(pin);
 545         else
 546                 data &= ~BIT(pin);
 547         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 548
 549         return 0;
 550 }
 551
 552 static const struct pinmux_ops rockchip_pmx_ops = {
 553         .get_functions_count    = rockchip_pmx_get_funcs_count,
 554         .get_function_name      = rockchip_pmx_get_func_name,
 555         .get_function_groups    = rockchip_pmx_get_groups,
 556         .enable                 = rockchip_pmx_enable,
 557         .disable                = rockchip_pmx_disable,
 558         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 559 };
 560
 561
 562
 563 /*
 564  * Hardware access
 565  */
 566 #define TYPE_PULL_REG           0x01
 567 #define TYPE_VOL_REG            0x02
 568 #define TYPE_DRV_REG            0x03
 569 #define TYPE_TRI_REG            0x04
 570
 571 #define RK3188_GRF_IO_CON0      0xf4
 572 #define RK3188_GRF_IO_CON1      0xf8
 573 #define RK3188_GRF_IO_CON2      0xfc
 574 #define RK3188_GRF_IO_CON3      0x100
 575 #define RK3188_GRF_IO_CON4      0x104
 576
 577 static struct func_to_reg_offset rk3188_func_to_reg_offset[] =
 578 {
 579         FUNC_TO_REG_OFFSET(TYPE_DRV_REG,  "reserve", RK3188_GRF_IO_CON0, 0 ,3),
 580         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio0_flash", RK3188_GRF_IO_CON0, 2, 3),
 581         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio0_flash", RK3188_GRF_IO_CON0, 4 ,3),
 582         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio0_d", RK3188_GRF_IO_CON0, 6 ,3),
 583         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_uart0", RK3188_GRF_IO_CON0, 8 ,3),
 584         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_uart1", RK3188_GRF_IO_CON0, 10 ,3),
 585         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_spi0", RK3188_GRF_IO_CON0, 10 ,3),
 586         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_uart2", RK3188_GRF_IO_CON0, 12 ,3),
 587         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_uart3", RK3188_GRF_IO_CON0, 14 ,3),
 588         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_spi1", RK3188_GRF_IO_CON0, 14 ,3),
 589
 590         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_i2s0", RK3188_GRF_IO_CON1, 0 ,3),
 591         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_i2s0", RK3188_GRF_IO_CON1, 2 ,3),
 592         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_c", RK3188_GRF_IO_CON1, 4 ,3),
 593         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_i2c0", RK3188_GRF_IO_CON1, 6 ,3),
 594         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_i2c1", RK3188_GRF_IO_CON1, 8 ,3),
 595         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_i2c2", RK3188_GRF_IO_CON1, 10 ,3),
 596         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio1_i2c4", RK3188_GRF_IO_CON1, 12 ,3),
 597         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio2_lcdc1", RK3188_GRF_IO_CON1, 14 ,3),
 598
 599         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio2_lcdc1", RK3188_GRF_IO_CON2, 0 ,3),
 600         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio2_smc", RK3188_GRF_IO_CON2, 2 ,3),
 601         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "reserve", RK3188_GRF_IO_CON2, 4 ,3),
 602         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio3_sdmmc", RK3188_GRF_IO_CON2, 6 ,3),
 603         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio3_sdmmc", RK3188_GRF_IO_CON2, 8 ,3),
 604         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio3_b", RK3188_GRF_IO_CON2, 10 ,3),
 605         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio3_cif", RK3188_GRF_IO_CON2, 12 ,3),
 606         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio3_cif", RK3188_GRF_IO_CON2, 14 ,3),
 607
 608
 609         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio3_sdio", RK3188_GRF_IO_CON3, 0 ,3),
 610         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio3_sdio", RK3188_GRF_IO_CON3, 2 ,3),
 611         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio3_pwm", RK3188_GRF_IO_CON3, 4 ,3),
 612         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "gpio3_d", RK3188_GRF_IO_CON3, 6 ,3),
 613         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "flash", RK3188_GRF_IO_CON3, 8 ,3),
 614         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "flash", RK3188_GRF_IO_CON3, 10 ,3),
 615         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "cif", RK3188_GRF_IO_CON3, 12 ,3),
 616         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc0", RK3188_GRF_IO_CON3, 14 ,3),
 617
 618         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc0", RK3188_GRF_IO_CON4, 0 ,3),
 619         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "jtag", RK3188_GRF_IO_CON4, 2 ,3),
 620         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "misc", RK3188_GRF_IO_CON4, 4 ,3),
 621         FUNC_TO_REG_OFFSET(TYPE_DRV_REG, "reserve", RK3188_GRF_IO_CON4, 6 ,3),
 622
 623         FUNC_TO_REG_OFFSET(TYPE_VOL_REG, "ap0_io", RK3188_GRF_IO_CON4, 8 ,1),
 624         FUNC_TO_REG_OFFSET(TYPE_VOL_REG, "ap1_io", RK3188_GRF_IO_CON4, 9 ,1),
 625         FUNC_TO_REG_OFFSET(TYPE_VOL_REG, "cif_io", RK3188_GRF_IO_CON4, 10 ,1),
 626         FUNC_TO_REG_OFFSET(TYPE_VOL_REG, "flash_io", RK3188_GRF_IO_CON4, 11 ,1),
 627         FUNC_TO_REG_OFFSET(TYPE_VOL_REG, "vccio0_io", RK3188_GRF_IO_CON4, 12 ,1),
 628         FUNC_TO_REG_OFFSET(TYPE_VOL_REG, "vccio1_io", RK3188_GRF_IO_CON4, 13 ,1),
 629         FUNC_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc0_io", RK3188_GRF_IO_CON4, 14 ,1),
 630         FUNC_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc1_io", RK3188_GRF_IO_CON4, 15 ,1),
 631
 632 };
 633
 634
 635 static int rockchip_get_pin_config(struct rockchip_pin_bank *bank,
 636                                         int pin_num, int param, int config_type)
 637 {
 638         struct rockchip_pinctrl *info = bank->drvdata;
 639         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 640         struct func_to_reg_offset reg_offset[4];//same name count should be less four
 641         int i = 0, j = 0;
 642         int value = 0;
 643         unsigned long flags;
 644         void __iomem *reg;
 645
 646         for(i = 0; i < ARRAY_SIZE(rk3188_func_to_reg_offset); i++)
 647         {
 648                 if(!strcmp(info->groups->func_name, rk3188_func_to_reg_offset[i].func_name))
 649                 {
 650                         reg_offset[j++] = rk3188_func_to_reg_offset[i];
 651                 }
 652         }
 653
 654         if(j <= 0)
 655         {
 656                 printk("%s:could find config register for PIN%d-%d\n",__func__, bank->bank_num, pin_num);
 657                 return -1;
 658         }
 659
 660
 661         switch(ctrl->type)
 662         {
 663                 case RK2928:
 664                 break;
 665
 666                 case RK3188:
 667
 668                 switch(config_type)
 669                 {
 670                         case TYPE_PULL_REG:
 671
 672                         break;
 673
 674                         case TYPE_VOL_REG:
 675
 676                         break;
 677
 678                         case TYPE_DRV_REG:
 679                         for(i=0; i < j; i++)
 680                         {
 681                                 reg = bank->reg_base + reg_offset[i].reg_offset;
 682                                 value |= ((param & reg_offset[i].bit_mask) << (16 + reg_offset[i].bit_offset));
 683                                 value |= ((param & reg_offset[i].bit_mask) << reg_offset[i].bit_offset);
 684                                 spin_lock_irqsave(&bank->slock, flags);
 685                                 //writel_relaxed(value, reg);
 686                                 spin_unlock_irqrestore(&bank->slock, flags);
 687
 688                                 DBG_PINCTRL("%s:reg[%d]=0x%p,value[%d]=0x%x\n",__func__, i, reg, i, value);
 689                         }
 690                         break;
 691
 692                         case TYPE_TRI_REG:
 693
 694                         break;
 695                         default:
 696                         break;
 697
 698                 }
 699
 700                 break;
 701
 702                 default:
 703                 break;
 704         }
 705
 706
 707
 708         DBG_PINCTRL("%s:GPIO%d-%d,group=%s, function=%s, gpio=%s, type=%d\n", __func__, bank->bank_num, pin_num, info->groups->name, info->groups->func_name, bank->of_node->name, config_type);
 709
 710         return 0;
 711 }
 712
 713
 714
 715 static int rockchip_set_pin_config(struct rockchip_pin_bank *bank,
 716                                         int pin_num, int param, int config_type)
 717 {
 718         struct rockchip_pinctrl *info = bank->drvdata;
 719         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 720         struct func_to_reg_offset reg_offset[4];//same name count should be less four
 721         int i = 0, j = 0;
 722         int value = 0;
 723         unsigned long flags;
 724         void __iomem *reg;
 725
 726         for(i = 0; i < ARRAY_SIZE(rk3188_func_to_reg_offset); i++)
 727         {
 728                 if(!strcmp(info->groups->func_name, rk3188_func_to_reg_offset[i].func_name))
 729                 {
 730                         reg_offset[j++] = rk3188_func_to_reg_offset[i];
 731                 }
 732         }
 733
 734         if(j <= 0)
 735         {
 736                 printk("%s:could find config register for PIN%d-%d\n",__func__, bank->bank_num, pin_num);
 737                 return -1;
 738         }
 739
 740
 741         switch(ctrl->type)
 742         {
 743                 case RK2928:
 744                 break;
 745
 746                 case RK3188:
 747
 748                 switch(config_type)
 749                 {
 750                         case TYPE_PULL_REG:
 751
 752                         break;
 753
 754                         case TYPE_VOL_REG:
 755
 756                         break;
 757
 758                         case TYPE_DRV_REG:
 759                         for(i=0; i < j; i++)
 760                         {
 761                                 reg = bank->reg_base + reg_offset[i].reg_offset;
 762                                 value |= ((param & reg_offset[i].bit_mask) << (16 + reg_offset[i].bit_offset));
 763                                 value |= ((param & reg_offset[i].bit_mask) << reg_offset[i].bit_offset);
 764                                 spin_lock_irqsave(&bank->slock, flags);
 765                                 //writel_relaxed(value, reg);
 766                                 spin_unlock_irqrestore(&bank->slock, flags);
 767
 768                                 DBG_PINCTRL("%s:reg[%d]=0x%p,value[%d]=0x%x\n",__func__, i, reg, i, value);
 769                         }
 770                         break;
 771
 772                         case TYPE_TRI_REG:
 773
 774                         break;
 775                         default:
 776                         break;
 777
 778                 }
 779
 780                 break;
 781
 782                 default:
 783                 break;
 784         }
 785
 786
 787
 788         DBG_PINCTRL("%s:GPIO%d-%d,group=%s, function=%s, gpio=%s, type=%d\n", __func__, bank->bank_num, pin_num, info->groups[0].name, info->groups[0].func_name, bank->of_node->name, config_type);
 789
 790         return 0;
 791 }
 792
 793
 794
 795 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 796                                     int pin_num, void __iomem **reg, u8 *bit)
 797 {
 798         struct rockchip_pinctrl *info = bank->drvdata;
 799
 800         *reg = info->reg_base + RK2928_PULL_OFFSET;
 801         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 802         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 803
 804         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 805
 806         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%p, bit=%d\n", __func__, bank->bank_num, pin_num, *reg, *bit);
 807 };
 808
 809
 810 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 811                                     int pin_num, void __iomem **reg, u8 *bit)
 812 {
 813         struct rockchip_pinctrl *info = bank->drvdata;
 814
 815         /* The first 12 pins of the first bank are located elsewhere */
 816         if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
 817                 *reg = bank->reg_pull +
 818                                 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 819                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 820                 *bit *= RK3188_PULL_BITS_PER_PIN;
 821         } else {
 822                 *reg = info->reg_pull - 4;
 823                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 824                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 825
 826                 /*
 827                  * The bits in these registers have an inverse ordering
 828                  * with the lowest pin being in bits 15:14 and the highest
 829                  * pin in bits 1:0
 830                  */
 831                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 832                 *bit *= RK3188_PULL_BITS_PER_PIN;
 833         }
 834
 835         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%p, bit=%d\n", __func__, bank->bank_num, pin_num, *reg, *bit);
 836 }
 837
 838 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 839 {
 840         struct rockchip_pinctrl *info = bank->drvdata;
 841         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 842         void __iomem *reg;
 843         u8 bit;
 844         u32 data;
 845
 846         /* rk3066b does support any pulls */
 847         if (ctrl->type == RK3066B)
 848                 return PIN_CONFIG_BIAS_DISABLE;
 849
 850         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 851
 852         switch (ctrl->type) {
 853         case RK2928:
 854                 return !(readl_relaxed(reg) & BIT(bit))
 855                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 856                                 : PIN_CONFIG_BIAS_DISABLE;
 857         case RK3188:
 858                 data = readl_relaxed(reg) >> bit;
 859                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 860
 861                 switch (data) {
 862                 case 0:
 863                         return PIN_CONFIG_BIAS_DISABLE;
 864                 case 1:
 865                         return PIN_CONFIG_BIAS_PULL_UP;
 866                 case 2:
 867                         return PIN_CONFIG_BIAS_PULL_DOWN;
 868                 case 3:
 869                         return PIN_CONFIG_BIAS_BUS_HOLD;
 870                 }
 871
 872                 dev_err(info->dev, "unknown pull setting\n");
 873                 return -EIO;
 874         default:
 875                 dev_err(info->dev, "unsupported pinctrl type\n");
 876                 return -EINVAL;
 877         };
 878
 879         DBG_PINCTRL("%s:GPIO%d-%d pull is 0x%x\n", __func__, bank->bank_num, pin_num, data);
 880 }
 881
 882 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 883                                         int pin_num, int pull)
 884 {
 885         struct rockchip_pinctrl *info = bank->drvdata;
 886         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 887         void __iomem *reg;
 888         unsigned long flags;
 889         u8 bit;
 890         u32 data;
 891
 892
 893         /* rk3066b does support any pulls */
 894         if (ctrl->type == RK3066B)
 895                 return pull ? -EINVAL : 0;
 896
 897         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 898
 899         switch (ctrl->type) {
 900         case RK2928:
 901                 spin_lock_irqsave(&bank->slock, flags);
 902
 903                 data = BIT(bit + 16);
 904                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 905                         data |= BIT(bit);
 906                 writel(data, reg);
 907
 908                 spin_unlock_irqrestore(&bank->slock, flags);
 909                 break;
 910         case RK3188:
 911                 spin_lock_irqsave(&bank->slock, flags);
 912
 913                 /* enable the write to the equivalent lower bits */
 914                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 915
 916                 switch (pull) {
 917                 case PIN_CONFIG_BIAS_DISABLE:
 918                         break;
 919                 case PIN_CONFIG_BIAS_PULL_UP:
 920                         data |= (1 << bit);
 921                         break;
 922                 case PIN_CONFIG_BIAS_PULL_DOWN:
 923                         data |= (2 << bit);
 924                         break;
 925                 case PIN_CONFIG_BIAS_BUS_HOLD:
 926                         data |= (3 << bit);
 927                         break;
 928                 default:
 929                         dev_err(info->dev, "unsupported pull setting %d\n",
 930                                 pull);
 931                         return -EINVAL;
 932                 }
 933
 934                 writel(data, reg);
 935
 936                 spin_unlock_irqrestore(&bank->slock, flags);
 937                 break;
 938         default:
 939                 dev_err(info->dev, "unsupported pinctrl type\n");
 940                 return -EINVAL;
 941         }
 942
 943
 944         DBG_PINCTRL("%s:GPIO%d-%d pull is 0x%x\n", __func__, bank->bank_num, pin_num, data);
 945
 946         return 0;
 947 }
 948
 949 /*
 950  * Pinconf_ops handling
 951  */
 952
 953 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 954                                         enum pin_config_param pull)
 955 {
 956         switch (ctrl->type) {
 957         case RK2928:
 958                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 959                                         pull == PIN_CONFIG_BIAS_DISABLE);
 960         case RK3066B:
 961                 return pull ? false : true;
 962         case RK3188:
 963                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 964         }
 965
 966         return false;
 967 }
 968
 969 /* set the pin config settings for a specified pin */
 970 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 971                                 unsigned long configs)
 972 {
 973         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 974         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 975         enum pin_config_param param;
 976         u16 arg;
 977         int rc;
 978
 979
 980         param = pinconf_to_config_param(configs);
 981         arg = pinconf_to_config_argument(configs);
 982
 983         switch (param) {
 984         case PIN_CONFIG_BIAS_DISABLE:
 985                 rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 986                         param);
 987                 if (rc)
 988                         return rc;
 989                 break;
 990         case PIN_CONFIG_BIAS_PULL_UP:
 991         case PIN_CONFIG_BIAS_PULL_DOWN:
 992         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 993         case PIN_CONFIG_BIAS_BUS_HOLD:
 994                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 995                         return -ENOTSUPP;
 996
 997                 if (!arg)
 998                         return -EINVAL;
 999
1000                 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1001                         param);
1002                 if (rc)
1003                         return rc;
1004                 break;
1005
1006         case PIN_CONFIG_POWER_SOURCE:
1007                 rc = rockchip_set_pin_config(bank, pin - bank->pin_base, param, TYPE_VOL_REG);
1008                 if (rc)
1009                 return rc;
1010                 break;
1011
1012         case PIN_CONFIG_DRIVE_STRENGTH:
1013                 rc = rockchip_set_pin_config(bank, pin - bank->pin_base, param, TYPE_DRV_REG);
1014                 if (rc)
1015                 return rc;
1016                 break;
1017         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1018                 rc = rockchip_set_pin_config(bank, pin - bank->pin_base, param, TYPE_TRI_REG);
1019                 if (rc)
1020                 return rc;
1021                 break;
1022         default:
1023                 return -ENOTSUPP;
1024                 break;
1025         }
1026
1027         DBG_PINCTRL("%s,pin=%d,param=%d\n",__func__,pin, param);
1028
1029         return 0;
1030 }
1031
1032 /* get the pin config settings for a specified pin */
1033 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1034                                                         unsigned long *config)
1035 {
1036         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1037         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1038         enum pin_config_param param = pinconf_to_config_param(*config);
1039         int rc;
1040
1041         switch (param) {
1042         case PIN_CONFIG_BIAS_DISABLE:
1043                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1044                         return -EINVAL;
1045
1046                 *config = 0;
1047                 break;
1048         case PIN_CONFIG_BIAS_PULL_UP:
1049         case PIN_CONFIG_BIAS_PULL_DOWN:
1050         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1051         case PIN_CONFIG_BIAS_BUS_HOLD:
1052                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1053                         return -ENOTSUPP;
1054
1055                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1056                         return -EINVAL;
1057
1058                 *config = 1;
1059                 break;
1060
1061         case PIN_CONFIG_POWER_SOURCE:
1062                 rc = rockchip_get_pin_config(bank, pin - bank->pin_base, param, TYPE_VOL_REG);
1063                 if (rc)
1064                 return rc;
1065                 break;
1066
1067         case PIN_CONFIG_DRIVE_STRENGTH:
1068                 rc = rockchip_get_pin_config(bank, pin - bank->pin_base, param, TYPE_DRV_REG);
1069                 if (rc)
1070                 return rc;
1071                 break;
1072         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1073                 rc = rockchip_get_pin_config(bank, pin - bank->pin_base, param, TYPE_TRI_REG);
1074                 if (rc)
1075                 return rc;
1076                 break;
1077
1078         default:
1079                 return -ENOTSUPP;
1080                 break;
1081         }
1082
1083
1084         DBG_PINCTRL("%s:pin=%d, param=%d\n",__func__, pin, param);
1085
1086         return 0;
1087 }
1088
1089 /* set the pin config settings for a specified pin group */
1090 static int rockchip_pinconf_group_set(struct pinctrl_dev *pctldev,
1091                         unsigned group, unsigned long config)
1092 {
1093         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1094         const unsigned int *pins;
1095         unsigned int cnt;
1096
1097         DBG_PINCTRL("%s:group[%d]:%s\n",__func__, group, info->groups[group].name);
1098         pins = info->groups[group].pins;
1099
1100         for (cnt = 0; cnt < info->groups[group].npins; cnt++)
1101                 rockchip_pinconf_set(pctldev, pins[cnt], config);
1102
1103         return 0;
1104 }
1105
1106 /* get the pin config settings for a specified pin group */
1107 static int rockchip_pinconf_group_get(struct pinctrl_dev *pctldev,
1108                                 unsigned int group, unsigned long *config)
1109 {
1110         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1111         const unsigned int *pins;
1112
1113         pins = info->groups[group].pins;
1114         rockchip_pinconf_get(pctldev, pins[0], config);
1115
1116         DBG_PINCTRL("%s:group[%d]:%s\n",__func__, group, info->groups[group].name);
1117         return 0;
1118 }
1119
1120 static void rockchip_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1121                                  struct seq_file *s, unsigned pin)
1122 {
1123         //to do
1124 }
1125
1126 static void rockchip_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
1127                                        struct seq_file *s, unsigned group)
1128 {
1129         //to do
1130 }
1131
1132
1133 static const struct pinconf_ops rockchip_pinconf_ops = {
1134         .pin_config_get                 = rockchip_pinconf_get,
1135         .pin_config_set                 = rockchip_pinconf_set,
1136         .pin_config_group_get           = rockchip_pinconf_group_get,
1137         .pin_config_group_set           = rockchip_pinconf_group_set,
1138         .pin_config_dbg_show            = rockchip_pinconf_dbg_show,
1139         .pin_config_group_dbg_show      = rockchip_pinconf_group_dbg_show,
1140 };
1141
1142 static const struct of_device_id rockchip_bank_match[] = {
1143         { .compatible = "rockchip,gpio-bank" },
1144         { .compatible = "rockchip,rk3188-gpio-bank0" },
1145         {},
1146 };
1147
1148 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1149                                                 struct device_node *np)
1150 {
1151         struct device_node *child;
1152
1153         for_each_child_of_node(np, child) {
1154                 if (of_match_node(rockchip_bank_match, child))
1155                         continue;
1156
1157                 info->nfunctions++;
1158                 info->ngroups += of_get_child_count(child);
1159         }
1160 }
1161
1162 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1163                                               struct rockchip_pin_group *grp,
1164                                               struct rockchip_pinctrl *info,
1165                                               u32 index)
1166 {
1167         struct rockchip_pin_bank *bank;
1168         int size;
1169         const __be32 *list;
1170         int i, j;
1171         struct union_mode m;
1172         int configlen = 0;
1173         unsigned long *pinconfig;
1174         u32 val;
1175
1176         DBG_PINCTRL("%s:group(%d): %s\n", __func__, index, np->name);
1177
1178         /* Initialise group */
1179         grp->name = np->name;
1180
1181         /*
1182          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1183          * do sanity check and calculate pins number
1184          */
1185         list = of_get_property(np, "rockchip,pins", &size);
1186         /* we do not check return since it's safe node passed down */
1187         size /= sizeof(*list);
1188         if (!size || size % 1) {
1189                 dev_err(info->dev, "wrong pins number or pins and configs should be by 1\n");
1190                 return -EINVAL;
1191         }
1192
1193         grp->npins = size / 1;
1194
1195         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1196                                                 GFP_KERNEL);
1197         grp->data = devm_kzalloc(info->dev, grp->npins *
1198                                           sizeof(struct rockchip_pin_config),
1199                                         GFP_KERNEL);
1200         if (!grp->pins || !grp->data)
1201                 return -ENOMEM;
1202
1203         pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
1204
1205         for (i = 0; i < size; i++) {
1206                 m.mode = be32_to_cpu(*list++);
1207
1208                 bank = bank_num_to_bank(info, m.mux.bank);
1209                 if (IS_ERR(bank))
1210                         return PTR_ERR(bank);
1211
1212                 grp->pins[i] = bank->pin_base + (m.mux.goff - 0x0A) * 8 + m.mux.off;
1213                 grp->data[i].func = m.mode;
1214
1215
1216                 j = 0;
1217                 configlen = 0;
1218
1219                 if (of_find_property(np, "rockchip,pull", NULL))
1220                         configlen++;
1221                 if (of_find_property(np, "rockchip,voltage", NULL))
1222                         configlen++;
1223                 if (of_find_property(np, "rockchip,drive", NULL))
1224                         configlen++;
1225                 if (of_find_property(np, "rockchip,tristate", NULL))
1226                         configlen++;
1227
1228                 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
1229
1230                 if (!of_property_read_u32(np, "allwinner,pull", &val)) {
1231                         enum pin_config_param pull = PIN_CONFIG_END;
1232                         if (val == 1)
1233                                 pull = PIN_CONFIG_BIAS_PULL_UP;
1234                         else if (val == 2)
1235                                 pull = PIN_CONFIG_BIAS_PULL_DOWN;
1236
1237                         pinconfig[j++] = pinconf_to_config_packed(pull, 0);
1238                 }
1239
1240                 if (!of_property_read_u32(np, "rockchip,voltage", &val)) {
1241                         pinconfig[j++] =
1242                                 pinconf_to_config_packed(PIN_CONFIG_POWER_SOURCE,
1243                                                          val);
1244                 }
1245
1246                 if (!of_property_read_u32(np, "rockchip,drive", &val)) {
1247                         pinconfig[j++] =
1248                                 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
1249                                                          val);
1250                 }
1251
1252                 if (!of_property_read_u32(np, "rockchip,tristate", &val)) {
1253                         pinconfig[j++] =
1254                                 pinconf_to_config_packed(PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
1255                                                          val);
1256                 }
1257
1258                 grp->data[i].configs = pinconfig;
1259                 grp->data[i].nconfigs = configlen;
1260
1261         }
1262
1263         return 0;
1264 }
1265
1266
1267 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1268                                                 struct rockchip_pinctrl *info,
1269                                                 u32 index)
1270 {
1271         struct device_node *child;
1272         struct rockchip_pmx_func *func;
1273         struct rockchip_pin_group *grp;
1274         int ret;
1275         static u32 grp_index;
1276         u32 i = 0;
1277
1278         DBG_PINCTRL("%s:parse function(%d): %s\n", __func__, index, np->name);
1279
1280         func = &info->functions[index];
1281
1282         /* Initialise function */
1283         func->name = np->name;
1284         func->ngroups = of_get_child_count(np);
1285         if (func->ngroups <= 0)
1286                 return 0;
1287
1288         func->groups = devm_kzalloc(info->dev,
1289                         func->ngroups * sizeof(char *), GFP_KERNEL);
1290         if (!func->groups)
1291                 return -ENOMEM;
1292
1293         for_each_child_of_node(np, child) {
1294                 func->groups[i] = child->name;
1295                 grp = &info->groups[grp_index++];
1296                 grp->func_name = np->name;
1297                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1298                 if (ret)
1299                         return ret;
1300
1301                 DBG_PINCTRL("%s:grp->func_name(%d): %s\n", __func__, grp_index, grp->func_name);
1302         }
1303
1304         return 0;
1305 }
1306
1307 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1308                                               struct rockchip_pinctrl *info)
1309 {
1310         struct device *dev = &pdev->dev;
1311         struct device_node *np = dev->of_node;
1312         struct device_node *child;
1313         int ret;
1314         int i;
1315
1316         rockchip_pinctrl_child_count(info, np);
1317
1318         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1319         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1320
1321         info->functions = devm_kzalloc(dev, info->nfunctions *
1322                                               sizeof(struct rockchip_pmx_func),
1323                                               GFP_KERNEL);
1324         if (!info->functions) {
1325                 dev_err(dev, "failed to allocate memory for function list\n");
1326                 return -EINVAL;
1327         }
1328
1329         info->groups = devm_kzalloc(dev, info->ngroups *
1330                                             sizeof(struct rockchip_pin_group),
1331                                             GFP_KERNEL);
1332         if (!info->groups) {
1333                 dev_err(dev, "failed allocate memory for ping group list\n");
1334                 return -EINVAL;
1335         }
1336
1337         i = 0;
1338
1339         for_each_child_of_node(np, child) {
1340                 if (of_match_node(rockchip_bank_match, child))
1341                         continue;
1342
1343                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1344                 if (ret) {
1345                         dev_err(&pdev->dev, "failed to parse function\n");
1346                         return ret;
1347                 }
1348         }
1349
1350         return 0;
1351 }
1352
1353 static int rockchip_pinctrl_register(struct platform_device *pdev,
1354                                         struct rockchip_pinctrl *info)
1355 {
1356         struct pinctrl_desc *ctrldesc = &info->pctl;
1357         struct pinctrl_pin_desc *pindesc, *pdesc;
1358         struct rockchip_pin_bank *pin_bank;
1359         int pin, bank, ret;
1360         int k;
1361
1362         ctrldesc->name = "rockchip-pinctrl";
1363         ctrldesc->owner = THIS_MODULE;
1364         ctrldesc->pctlops = &rockchip_pctrl_ops;
1365         ctrldesc->pmxops = &rockchip_pmx_ops;
1366         ctrldesc->confops = &rockchip_pinconf_ops;
1367
1368         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1369                         info->ctrl->nr_pins, GFP_KERNEL);
1370         if (!pindesc) {
1371                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1372                 return -ENOMEM;
1373         }
1374         ctrldesc->pins = pindesc;
1375         ctrldesc->npins = info->ctrl->nr_pins;
1376
1377         pdesc = pindesc;
1378         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1379                 pin_bank = &info->ctrl->pin_banks[bank];
1380                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1381                         pdesc->number = k;
1382                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1383                                                 pin_bank->name, pin);
1384                         pdesc++;
1385                 }
1386         }
1387
1388         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1389         if (!info->pctl_dev) {
1390                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1391                 return -EINVAL;
1392         }
1393
1394         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1395                 pin_bank = &info->ctrl->pin_banks[bank];
1396                 pin_bank->grange.name = pin_bank->name;
1397                 pin_bank->grange.id = bank;
1398                 pin_bank->grange.pin_base = pin_bank->pin_base;
1399                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1400                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1401                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1402                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1403         }
1404
1405         ret = rockchip_pinctrl_parse_dt(pdev, info);
1406         if (ret) {
1407                 pinctrl_unregister(info->pctl_dev);
1408                 return ret;
1409         }
1410
1411         return 0;
1412 }
1413
1414 /*
1415  * GPIO handling
1416  */
1417
1418 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1419 {
1420         struct rockchip_pin_bank *bank = gc_to_pin_bank(chip);
1421         struct rockchip_pinctrl *info = bank->drvdata;
1422         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
1423         return pinctrl_request_gpio(chip->base + offset);
1424 }
1425
1426 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1427 {
1428         struct rockchip_pin_bank *bank = gc_to_pin_bank(chip);
1429         struct rockchip_pinctrl *info = bank->drvdata;
1430         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
1431         pinctrl_free_gpio(chip->base + offset);
1432 }
1433
1434 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1435 {
1436         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1437         struct rockchip_pinctrl *info = bank->drvdata;
1438         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1439         unsigned long flags;
1440         u32 data;
1441
1442         spin_lock_irqsave(&bank->slock, flags);
1443
1444         data = readl(reg);
1445         data &= ~BIT(offset);
1446         if (value)
1447                 data |= BIT(offset);
1448         writel(data, reg);
1449
1450         spin_unlock_irqrestore(&bank->slock, flags);
1451
1452         DBG_PINCTRL("%s:GPIO%d-%d level = %d\n", __func__, bank->bank_num, offset, value);
1453 }
1454
1455 /*
1456  * Returns the level of the pin for input direction and setting of the DR
1457  * register for output gpios.
1458  */
1459 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1460 {
1461         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1462         struct rockchip_pinctrl *info = bank->drvdata;
1463         u32 data;
1464
1465         data = readl(bank->reg_base + GPIO_EXT_PORT);
1466         data >>= offset;
1467         data &= 1;
1468
1469         DBG_PINCTRL("%s:GPIO%d-%d level = %d\n", __func__, bank->bank_num, offset, data);
1470         return data;
1471 }
1472
1473 /*
1474  * gpiolib gpio_direction_input callback function. The setting of the pin
1475  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1476  * interface.
1477  */
1478 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1479 {
1480         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1481         struct rockchip_pinctrl *info = bank->drvdata;
1482
1483         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
1484         return pinctrl_gpio_direction_input(gc->base + offset);
1485 }
1486
1487 /*
1488  * gpiolib gpio_direction_output callback function. The setting of the pin
1489  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1490  * interface.
1491  */
1492 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1493                                           unsigned offset, int value)
1494 {
1495         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1496         struct rockchip_pinctrl *info = bank->drvdata;
1497         rockchip_gpio_set(gc, offset, value);
1498
1499         DBG_PINCTRL("%s:set GPIO%d-%d level %d\n", __func__, bank->bank_num, offset, value);
1500         return pinctrl_gpio_direction_output(gc->base + offset);
1501 }
1502
1503 /*
1504  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1505  * and a virtual IRQ, if not already present.
1506  */
1507 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1508 {
1509         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1510         struct rockchip_pinctrl *info = bank->drvdata;
1511
1512         unsigned int virq;
1513
1514         if (!bank->domain)
1515                 return -ENXIO;
1516
1517         virq = irq_create_mapping(bank->domain, offset);
1518
1519         DBG_PINCTRL("%s:virq=%d, GPIO%d-%d\n", __func__, virq, bank->bank_num, offset);
1520
1521         return (virq) ? : -ENXIO;
1522 }
1523
1524 static const struct gpio_chip rockchip_gpiolib_chip = {
1525         .request = rockchip_gpio_request,
1526         .free = rockchip_gpio_free,
1527         .set = rockchip_gpio_set,
1528         .get = rockchip_gpio_get,
1529         .direction_input = rockchip_gpio_direction_input,
1530         .direction_output = rockchip_gpio_direction_output,
1531         .to_irq = rockchip_gpio_to_irq,
1532         .owner = THIS_MODULE,
1533 };
1534
1535 /*
1536  * Interrupt handling
1537  */
1538
1539 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1540 {
1541         struct irq_chip *chip = irq_get_chip(irq);
1542         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1543         struct rockchip_pinctrl *info = bank->drvdata;
1544
1545         u32 polarity = 0, data = 0;
1546         u32 pend;
1547         bool edge_changed = false;
1548
1549         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1550
1551         chained_irq_enter(chip, desc);
1552
1553         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1554
1555         if (bank->toggle_edge_mode) {
1556                 polarity = readl_relaxed(bank->reg_base +
1557                                          GPIO_INT_POLARITY);
1558                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1559         }
1560
1561         while (pend) {
1562                 unsigned int virq;
1563
1564                 irq = __ffs(pend);
1565                 pend &= ~BIT(irq);
1566                 virq = irq_linear_revmap(bank->domain, irq);
1567
1568                 if (!virq) {
1569                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1570                         continue;
1571                 }
1572
1573                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1574
1575                 /*
1576                  * Triggering IRQ on both rising and falling edge
1577                  * needs manual intervention.
1578                  */
1579                 if (bank->toggle_edge_mode & BIT(irq)) {
1580                         if (data & BIT(irq))
1581                                 polarity &= ~BIT(irq);
1582                         else
1583                                 polarity |= BIT(irq);
1584
1585                         edge_changed = true;
1586                 }
1587
1588                 generic_handle_irq(virq);
1589
1590
1591                 DBG_PINCTRL("%s:irq=%d\n",__func__, irq);
1592         }
1593
1594         if (bank->toggle_edge_mode && edge_changed) {
1595                 /* Interrupt params should only be set with ints disabled */
1596                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1597                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1598                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1599                 writel(data, bank->reg_base + GPIO_INTEN);
1600         }
1601
1602         chained_irq_exit(chip, desc);
1603 }
1604
1605 static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1606 {
1607         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1608         struct rockchip_pinctrl *info = bank->drvdata;
1609         u32 mask = BIT(d->hwirq);
1610         u32 polarity;
1611         u32 level;
1612         u32 data;
1613         u32 mux;
1614         unsigned long flags;
1615
1616         DBG_PINCTRL("%s:type=%d,irq=%d,hwirq=%d\n",__func__,type, d->irq, (int)d->hwirq);
1617
1618         /* make sure the pin is configured as gpio input */
1619         mux = (bank->bank_num << 12) | (((d->hwirq / 8) + 0x0A) << 8) | ((d->hwirq % 8)<< 4) | RK_FUNC_GPIO;
1620         rockchip_set_mux(bank, d->hwirq, mux);
1621
1622         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1623         data &= ~mask;
1624         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1625
1626         if (type & IRQ_TYPE_EDGE_BOTH)
1627                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1628         else
1629                 __irq_set_handler_locked(d->irq, handle_level_irq);
1630
1631         spin_lock_irqsave(&bank->slock, flags);
1632
1633         level = readl_relaxed(bank->reg_base + GPIO_INTTYPE_LEVEL);
1634         polarity = readl_relaxed(bank->reg_base + GPIO_INT_POLARITY);
1635
1636         switch (type) {
1637         case IRQ_TYPE_EDGE_BOTH:
1638                 bank->toggle_edge_mode |= mask;
1639                 level |= mask;
1640
1641                 /*
1642                  * Determine gpio state. If 1 next interrupt should be falling
1643                  * otherwise rising.
1644                  */
1645                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1646                 if (data & mask)
1647                         polarity &= ~mask;
1648                 else
1649                         polarity |= mask;
1650                 break;
1651         case IRQ_TYPE_EDGE_RISING:
1652                 bank->toggle_edge_mode &= ~mask;
1653                 level |= mask;
1654                 polarity |= mask;
1655                 break;
1656         case IRQ_TYPE_EDGE_FALLING:
1657                 bank->toggle_edge_mode &= ~mask;
1658                 level |= mask;
1659                 polarity &= ~mask;
1660                 break;
1661         case IRQ_TYPE_LEVEL_HIGH:
1662                 bank->toggle_edge_mode &= ~mask;
1663                 level &= ~mask;
1664                 polarity |= mask;
1665                 break;
1666         case IRQ_TYPE_LEVEL_LOW:
1667                 bank->toggle_edge_mode &= ~mask;
1668                 level &= ~mask;
1669                 polarity &= ~mask;
1670                 break;
1671         default:
1672                 //spin_unlock_irqrestore(&bank->slock, flags);
1673                 return -EINVAL;
1674         }
1675
1676         writel_relaxed(level, bank->reg_base + GPIO_INTTYPE_LEVEL);
1677         writel_relaxed(polarity, bank->reg_base + GPIO_INT_POLARITY);
1678
1679         spin_unlock_irqrestore(&bank->slock, flags);
1680
1681         DBG_PINCTRL("%s:type=%d,irq=%d,hwirq=%d,ok\n",__func__,type, d->irq, (int)d->hwirq);
1682         return 0;
1683 }
1684 #if 0
1685 static int rockchip_interrupts_register(struct platform_device *pdev,
1686                                                 struct rockchip_pinctrl *info)
1687 {
1688         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1689         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1690         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1691         struct irq_chip_generic *gc;
1692         int ret;
1693         int i;
1694
1695         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1696                 if (!bank->valid) {
1697                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1698                                  bank->name);
1699                         continue;
1700                 }
1701
1702                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1703                                                 &irq_generic_chip_ops, NULL);
1704                 if (!bank->domain) {
1705                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1706                                  bank->name);
1707                         continue;
1708                 }
1709
1710                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1711                                          "rockchip_gpio_irq", handle_level_irq,
1712                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1713                 if (ret) {
1714                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1715                                 bank->name);
1716                         irq_domain_remove(bank->domain);
1717                         continue;
1718                 }
1719
1720                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1721                 gc->reg_base = bank->reg_base;
1722                 gc->private = bank;
1723                 gc->chip_types[0].regs.mask = GPIO_INTEN;
1724                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1725                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1726                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1727                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1728                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1729                 gc->chip_types[0].chip.irq_set_type = rockchip_gpio_irq_set_type;
1730
1731                 irq_set_handler_data(bank->irq, bank);
1732                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1733         }
1734
1735         return 0;
1736 }
1737 #else
1738
1739 static inline void rockchip_gpio_bit_op(void __iomem *reg_base, unsigned int offset, u32 bit, unsigned char flag)
1740 {
1741         u32 val = __raw_readl(reg_base + offset);
1742         if (flag)
1743                 val |= bit;
1744         else
1745                 val &= ~bit;
1746         __raw_writel(val, reg_base + offset);
1747 }
1748
1749 static inline unsigned gpio_to_bit(struct rockchip_pin_bank *bank, unsigned gpio)
1750 {
1751         while (gpio >= (bank->pin_base + bank->nr_pins))
1752                 bank++;
1753
1754         return gpio - bank->pin_base;
1755 }
1756
1757 static inline unsigned offset_to_bit(unsigned offset)
1758 {
1759         return 1u << offset;
1760 }
1761 #if 0
1762 static void GPIOSetPinLevel(void __iomem *reg_base, unsigned int bit, eGPIOPinLevel_t level)
1763 {
1764         rockchip_gpio_bit_op(reg_base, GPIO_SWPORT_DDR, bit, 1);
1765         rockchip_gpio_bit_op(reg_base, GPIO_SWPORT_DR, bit, level);
1766 }
1767
1768 static int GPIOGetPinLevel(void __iomem *reg_base, unsigned int bit)
1769 {
1770         return ((__raw_readl(reg_base + GPIO_EXT_PORT) & bit) != 0);
1771 }
1772
1773 static void GPIOSetPinDirection(void __iomem *reg_base, unsigned int bit, eGPIOPinDirection_t direction)
1774 {
1775         rockchip_gpio_bit_op(reg_base, GPIO_SWPORT_DDR, bit, direction);
1776         /* Enable debounce may halt cpu on wfi, disable it by default */
1777         //rockchip_gpio_bit_op(reg_base, GPIO_DEBOUNCE, bit, 1);
1778 }
1779 #endif
1780 static void GPIOEnableIntr(void __iomem *reg_base, unsigned int bit)
1781 {
1782         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 1);
1783 }
1784
1785 static void GPIODisableIntr(void __iomem *reg_base, unsigned int bit)
1786 {
1787         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 0);
1788 }
1789
1790 static void GPIOAckIntr(void __iomem *reg_base, unsigned int bit)
1791 {
1792         rockchip_gpio_bit_op(reg_base, GPIO_PORTS_EOI, bit, 1);
1793 }
1794 #if 0
1795 static void GPIOSetIntrType(void __iomem *reg_base, unsigned int bit, eGPIOIntType_t type)
1796 {
1797         switch (type) {
1798         case GPIOLevelLow:
1799                 rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 0);
1800                 rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 0);
1801                 break;
1802         case GPIOLevelHigh:
1803                 rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 0);
1804                 rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 1);
1805                 break;
1806         case GPIOEdgelFalling:
1807                 rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 1);
1808                 rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 0);
1809                 break;
1810         case GPIOEdgelRising:
1811                 rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 1);
1812                 rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 1);
1813                 break;
1814         }
1815 }
1816
1817 static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1818 {
1819         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1820         u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
1821         eGPIOIntType_t int_type;
1822         unsigned long flags;
1823
1824         switch (type) {
1825         case IRQ_TYPE_EDGE_RISING:
1826                 int_type = GPIOEdgelRising;
1827                 break;
1828         case IRQ_TYPE_EDGE_FALLING:
1829                 int_type = GPIOEdgelFalling;
1830                 break;
1831         case IRQ_TYPE_LEVEL_HIGH:
1832                 int_type = GPIOLevelHigh;
1833                 break;
1834         case IRQ_TYPE_LEVEL_LOW:
1835                 int_type = GPIOLevelLow;
1836                 break;
1837         default:
1838                 return -EINVAL;
1839         }
1840
1841         spin_lock_irqsave(&bank->slock, flags);
1842         //ÉèÖÃÎªÖÐ¶ÏÖ®Ç°£¬±ØÐëÏÈÉèÖÃÎªÊäÈë×´Ì¬
1843         GPIOSetPinDirection(bank->reg_base, bit, 0);
1844         GPIOSetIntrType(bank->reg_base, bit, int_type);
1845         spin_unlock_irqrestore(&bank->slock, flags);
1846
1847         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
1848                 __irq_set_handler_locked(d->irq, handle_level_irq);
1849         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
1850                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1851
1852         return 0;
1853 }
1854 #endif
1855 static int rockchip_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1856 {
1857         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1858         struct rockchip_pinctrl *info = bank->drvdata;
1859
1860         //u32 bit = gpio_to_bit(bank, d->irq);
1861         u32 bit = d->hwirq;
1862         unsigned long flags;
1863
1864         spin_lock_irqsave(&bank->slock, flags);
1865
1866         if (on)
1867                 bank->suspend_wakeup |= bit;
1868         else
1869                 bank->suspend_wakeup &= ~bit;
1870         spin_unlock_irqrestore(&bank->slock, flags);
1871
1872         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
1873         return 0;
1874 }
1875
1876 static void rockchip_gpio_irq_unmask(struct irq_data *d)
1877 {
1878         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1879         struct rockchip_pinctrl *info = bank->drvdata;
1880         //u32 bit = gpio_to_bit(bank, d->irq);
1881         u32 bit = d->hwirq;
1882         unsigned long flags;
1883
1884         spin_lock_irqsave(&bank->slock, flags);
1885         GPIOEnableIntr(bank->reg_base, bit);
1886         spin_unlock_irqrestore(&bank->slock, flags);
1887
1888         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
1889 }
1890
1891 static void rockchip_gpio_irq_mask(struct irq_data *d)
1892 {
1893         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1894         struct rockchip_pinctrl *info = bank->drvdata;
1895         //u32 bit = gpio_to_bit(bank, d->irq);
1896         u32 bit = d->hwirq;
1897         unsigned long flags;
1898
1899         spin_lock_irqsave(&bank->slock, flags);
1900         GPIODisableIntr(bank->reg_base, bit);
1901         spin_unlock_irqrestore(&bank->slock, flags);
1902
1903         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
1904 }
1905
1906 static void rockchip_gpio_irq_ack(struct irq_data *d)
1907 {
1908         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1909         struct rockchip_pinctrl *info = bank->drvdata;
1910         //u32 bit = gpio_to_bit(bank, d->irq);
1911         u32 bit = d->hwirq;
1912
1913         GPIOAckIntr(bank->reg_base, bit);
1914
1915         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
1916 }
1917
1918
1919 static struct irq_chip rockchip_gpio_irq_chip = {
1920         .name           = "GPIO",
1921         .irq_ack        = rockchip_gpio_irq_ack,
1922         .irq_disable    = rockchip_gpio_irq_mask,
1923         .irq_mask       = rockchip_gpio_irq_mask,
1924         .irq_unmask     = rockchip_gpio_irq_unmask,
1925         .irq_set_type   = rockchip_gpio_irq_set_type,
1926         .irq_set_wake   = rockchip_gpio_irq_set_wake,
1927 };
1928
1929
1930 static int rockchip_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1931                                 irq_hw_number_t hwirq)
1932 {
1933         struct rockchip_pin_bank *bank = d->host_data;
1934         struct rockchip_pinctrl *info = bank->drvdata;
1935         struct irq_data *irq_data = irq_get_irq_data(irq);
1936
1937         if (!bank)
1938         {
1939                 printk("%s:bank=0x%p,irq=%d\n",__func__,bank, irq);
1940                 return -EINVAL;
1941         }
1942
1943         irq_set_chip_and_handler(irq, &rockchip_gpio_irq_chip, handle_level_irq);
1944         irq_set_chip_data(irq, bank);
1945         set_irq_flags(irq, IRQF_VALID);
1946
1947         irq_data->hwirq = hwirq;
1948         irq_data->irq = irq;
1949
1950         DBG_PINCTRL("%s:irq=%d\n",__func__,irq);
1951         return 0;
1952 }
1953
1954 const struct irq_domain_ops rockchip_gpio_irq_ops = {
1955         .map = rockchip_gpio_irq_map,
1956         .xlate = irq_domain_xlate_twocell,
1957 };
1958
1959
1960 static int rockchip_interrupts_register(struct platform_device *pdev,
1961                                                 struct rockchip_pinctrl *info)
1962 {
1963         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1964         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1965         //unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1966         int i;
1967
1968         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1969                 if (!bank->valid) {
1970                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1971                                  bank->name);
1972                         continue;
1973                 }
1974
1975                 __raw_writel(0, bank->reg_base + GPIO_INTEN);
1976
1977                 bank->drvdata = info;
1978                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1979                                 &rockchip_gpio_irq_ops, bank);
1980                 if (!bank->domain) {
1981                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1982                                  bank->name);
1983                         continue;
1984                 }
1985
1986
1987                 DBG_PINCTRL("%s:bank=%d\n",__func__,i);
1988
1989                 irq_set_handler_data(bank->irq, bank);
1990                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1991         }
1992
1993
1994         return 0;
1995 }
1996
1997
1998 #endif
1999 static int rockchip_gpiolib_register(struct platform_device *pdev,
2000                                                 struct rockchip_pinctrl *info)
2001 {
2002         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2003         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2004         struct gpio_chip *gc;
2005         int ret;
2006         int i;
2007
2008         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2009                 if (!bank->valid) {
2010                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2011                                  bank->name);
2012                         continue;
2013                 }
2014
2015                 bank->gpio_chip = rockchip_gpiolib_chip;
2016
2017                 gc = &bank->gpio_chip;
2018                 gc->base = bank->pin_base;
2019                 gc->ngpio = bank->nr_pins;
2020                 gc->dev = &pdev->dev;
2021                 gc->of_node = bank->of_node;
2022                 gc->label = bank->name;
2023
2024                 ret = gpiochip_add(gc);
2025                 if (ret) {
2026                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2027                                                         gc->label, ret);
2028                         goto fail;
2029                 }
2030         }
2031
2032         rockchip_interrupts_register(pdev, info);
2033
2034         return 0;
2035
2036 fail:
2037         for (--i, --bank; i >= 0; --i, --bank) {
2038                 if (!bank->valid)
2039                         continue;
2040
2041                 if (gpiochip_remove(&bank->gpio_chip))
2042                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
2043                                                         bank->gpio_chip.label);
2044         }
2045         return ret;
2046 }
2047
2048 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2049                                                 struct rockchip_pinctrl *info)
2050 {
2051         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2052         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2053         int ret = 0;
2054         int i;
2055
2056         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
2057                 if (!bank->valid)
2058                         continue;
2059
2060                 ret = gpiochip_remove(&bank->gpio_chip);
2061         }
2062
2063         if (ret)
2064                 dev_err(&pdev->dev, "gpio chip remove failed\n");
2065
2066         return ret;
2067 }
2068
2069 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2070                                   struct device *dev)
2071 {
2072         struct resource res;
2073
2074         if (of_address_to_resource(bank->of_node, 0, &res)) {
2075                 dev_err(dev, "cannot find IO resource for bank\n");
2076                 return -ENOENT;
2077         }
2078
2079         bank->reg_base = devm_ioremap_resource(dev, &res);
2080         if (IS_ERR(bank->reg_base))
2081                 return PTR_ERR(bank->reg_base);
2082
2083         /*
2084          * special case, where parts of the pull setting-registers are
2085          * part of the PMU register space
2086          */
2087         if (of_device_is_compatible(bank->of_node,
2088                                     "rockchip,rk3188-gpio-bank0")) {
2089                 bank->bank_type = RK3188_BANK0;
2090
2091                 if (of_address_to_resource(bank->of_node, 1, &res)) {
2092                         dev_err(dev, "cannot find IO resource for bank\n");
2093                         return -ENOENT;
2094                 }
2095
2096                 bank->reg_pull = devm_ioremap_resource(dev, &res);
2097                 if (IS_ERR(bank->reg_pull))
2098                         return PTR_ERR(bank->reg_pull);
2099         } else {
2100                 bank->bank_type = COMMON_BANK;
2101         }
2102
2103         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2104
2105         bank->clk = of_clk_get(bank->of_node, 0);
2106         //if (IS_ERR(bank->clk))
2107                 //return PTR_ERR(bank->clk);
2108         return 0;
2109         //return clk_prepare_enable(bank->clk);
2110 }
2111
2112 static const struct of_device_id rockchip_pinctrl_dt_match[];
2113
2114 /* retrieve the soc specific data */
2115 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2116                                                 struct rockchip_pinctrl *d,
2117                                                 struct platform_device *pdev)
2118 {
2119         const struct of_device_id *match;
2120         struct device_node *node = pdev->dev.of_node;
2121         struct device_node *np;
2122         struct rockchip_pin_ctrl *ctrl;
2123         struct rockchip_pin_bank *bank;
2124         int i;
2125
2126         match = of_match_node(rockchip_pinctrl_dt_match, node);
2127         ctrl = (struct rockchip_pin_ctrl *)match->data;
2128
2129         for_each_child_of_node(node, np) {
2130                 if (!of_find_property(np, "gpio-controller", NULL))
2131                         continue;
2132
2133                 bank = ctrl->pin_banks;
2134                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2135                         if (!strcmp(bank->name, np->name)) {
2136                                 bank->of_node = np;
2137
2138                                 if (!rockchip_get_bank_data(bank, &pdev->dev))
2139                                         bank->valid = true;
2140
2141                                 break;
2142                         }
2143                 }
2144         }
2145
2146         bank = ctrl->pin_banks;
2147         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2148                 spin_lock_init(&bank->slock);
2149                 bank->drvdata = d;
2150                 bank->pin_base = ctrl->nr_pins;
2151                 ctrl->nr_pins += bank->nr_pins;
2152         }
2153
2154         return ctrl;
2155 }
2156 #if 0
2157 static irqreturn_t pinctrl_interrupt_test(int irq, void *dev_id)
2158 {
2159         printk("%s:line=%d\n",__func__, __LINE__);
2160         return IRQ_HANDLED;
2161 }
2162 #endif
2163 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2164 {
2165         struct rockchip_pinctrl *info;
2166         struct device *dev = &pdev->dev;
2167         struct rockchip_pin_ctrl *ctrl;
2168         struct resource *res;
2169         int ret;
2170
2171         if (!dev->of_node) {
2172                 dev_err(dev, "device tree node not found\n");
2173                 return -ENODEV;
2174         }
2175
2176         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2177         if (!info)
2178                 return -ENOMEM;
2179
2180         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2181         if (!ctrl) {
2182                 dev_err(dev, "driver data not available\n");
2183                 return -EINVAL;
2184         }
2185         info->ctrl = ctrl;
2186         info->dev = dev;
2187
2188         atomic_set(&info->debug_flag, 1);
2189
2190         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2191         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
2192         if (IS_ERR(info->reg_base))
2193                 return PTR_ERR(info->reg_base);
2194
2195         /* The RK3188 has its pull registers in a separate place */
2196         if (ctrl->type == RK3188) {
2197                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2198                 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
2199                 if (IS_ERR(info->reg_base))
2200                         return PTR_ERR(info->reg_base);
2201         }
2202
2203         ret = rockchip_gpiolib_register(pdev, info);
2204         if (ret)
2205                 return ret;
2206
2207         ret = rockchip_pinctrl_register(pdev, info);
2208         if (ret) {
2209                 rockchip_gpiolib_unregister(pdev, info);
2210                 return ret;
2211         }
2212
2213         platform_set_drvdata(pdev, info);
2214 #if 0
2215         int i = 0;
2216         for(i=1; i<32*4; i++)
2217         {
2218                 if(i>23 && i<32+16)
2219                 continue;
2220                 gpio_request(i, NULL);
2221                 gpio_direction_input(i);
2222
2223                 ret = request_irq(gpio_to_irq(i), pinctrl_interrupt_test, IRQ_TYPE_EDGE_RISING, "test", info);
2224                 disable_irq(gpio_to_irq(i));
2225         }
2226 #endif
2227         printk("%s:init ok\n",__func__);
2228         return 0;
2229 }
2230
2231 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2232         PIN_BANK(0, 32, "gpio0"),
2233         PIN_BANK(1, 32, "gpio1"),
2234         PIN_BANK(2, 32, "gpio2"),
2235         PIN_BANK(3, 32, "gpio3"),
2236 };
2237
2238 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2239                 .pin_banks              = rk2928_pin_banks,
2240                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2241                 .label                  = "RK2928-GPIO",
2242                 .type                   = RK2928,
2243                 .mux_offset             = 0xa8,
2244                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2245 };
2246
2247 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2248         PIN_BANK(0, 32, "gpio0"),
2249         PIN_BANK(1, 32, "gpio1"),
2250         PIN_BANK(2, 32, "gpio2"),
2251         PIN_BANK(3, 32, "gpio3"),
2252         PIN_BANK(4, 32, "gpio4"),
2253         PIN_BANK(6, 16, "gpio6"),
2254 };
2255
2256 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2257                 .pin_banks              = rk3066a_pin_banks,
2258                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2259                 .label                  = "RK3066a-GPIO",
2260                 .type                   = RK2928,
2261                 .mux_offset             = 0xa8,
2262                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2263 };
2264
2265 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2266         PIN_BANK(0, 32, "gpio0"),
2267         PIN_BANK(1, 32, "gpio1"),
2268         PIN_BANK(2, 32, "gpio2"),
2269         PIN_BANK(3, 32, "gpio3"),
2270 };
2271
2272 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2273                 .pin_banks      = rk3066b_pin_banks,
2274                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2275                 .label          = "RK3066b-GPIO",
2276                 .type           = RK3066B,
2277                 .mux_offset     = 0x60,
2278 };
2279
2280 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2281         PIN_BANK(0, 32, "gpio0"),
2282         PIN_BANK(1, 32, "gpio1"),
2283         PIN_BANK(2, 32, "gpio2"),
2284         PIN_BANK(3, 32, "gpio3"),
2285 };
2286
2287 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2288                 .pin_banks              = rk3188_pin_banks,
2289                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2290                 .label                  = "RK3188-GPIO",
2291                 .type                   = RK3188,
2292                 .mux_offset             = 0x60,
2293                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2294 };
2295
2296 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2297         { .compatible = "rockchip,rk2928-pinctrl",
2298                 .data = (void *)&rk2928_pin_ctrl },
2299         { .compatible = "rockchip,rk3066a-pinctrl",
2300                 .data = (void *)&rk3066a_pin_ctrl },
2301         { .compatible = "rockchip,rk3066b-pinctrl",
2302                 .data = (void *)&rk3066b_pin_ctrl },
2303         { .compatible = "rockchip,rk3188-pinctrl",
2304                 .data = (void *)&rk3188_pin_ctrl },
2305         {},
2306 };
2307 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2308
2309 static struct platform_driver rockchip_pinctrl_driver = {
2310         .probe          = rockchip_pinctrl_probe,
2311         .driver = {
2312                 .name   = "rockchip-pinctrl",
2313                 .owner  = THIS_MODULE,
2314                 .of_match_table = rockchip_pinctrl_dt_match,
2315         },
2316 };
2317
2318 static int __init rockchip_pinctrl_drv_register(void)
2319 {
2320         return platform_driver_register(&rockchip_pinctrl_driver);
2321 }
2322 postcore_initcall(rockchip_pinctrl_drv_register);
2323
2324 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2325 MODULE_DESCRIPTION("Rockchip pinctrl driver");
2326 MODULE_LICENSE("GPL v2");