drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/irq.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of_address.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/pinctrl/machine.h>
  36 #include <linux/pinctrl/pinconf.h>
  37 #include <linux/pinctrl/pinctrl.h>
  38 #include <linux/pinctrl/pinmux.h>
  39 #include <linux/pinctrl/pinconf-generic.h>
  40 #include <linux/irqchip/chained_irq.h>
  41 #include <linux/clk.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43 #include <dt-bindings/pinctrl/rockchip-rk3188.h>
  44
  45
  46 #include <linux/of.h>
  47 #include <linux/of_device.h>
  48 #include <linux/pinctrl/consumer.h>
  49 #include <linux/slab.h>
  50
  51
  52 #include "core.h"
  53 #include "pinconf.h"
  54
  55
  56 #if 1
  57 #define DBG_PINCTRL(x...)  if(atomic_read(&info->debug_flag) == 1) printk(x)
  58 #else
  59 #define DBG_PINCTRL(x...)
  60 #endif
  61
  62
  63 /* GPIO control registers */
  64 #define GPIO_SWPORT_DR          0x00
  65 #define GPIO_SWPORT_DDR         0x04
  66 #define GPIO_INTEN              0x30
  67 #define GPIO_INTMASK            0x34
  68 #define GPIO_INTTYPE_LEVEL      0x38
  69 #define GPIO_INT_POLARITY       0x3c
  70 #define GPIO_INT_STATUS         0x40
  71 #define GPIO_INT_RAWSTATUS      0x44
  72 #define GPIO_DEBOUNCE           0x48
  73 #define GPIO_PORTS_EOI          0x4c
  74 #define GPIO_EXT_PORT           0x50
  75 #define GPIO_LS_SYNC            0x60
  76
  77 enum rockchip_pinctrl_type {
  78         RK2928,
  79         RK3066B,
  80         RK3188,
  81 };
  82
  83 enum rockchip_pin_bank_type {
  84         COMMON_BANK,
  85         RK3188_BANK0,
  86 };
  87
  88 /**
  89  * @reg_base: register base of the gpio bank
  90  * @reg_pull: optional separate register for additional pull settings
  91  * @clk: clock of the gpio bank
  92  * @irq: interrupt of the gpio bank
  93  * @pin_base: first pin number
  94  * @nr_pins: number of pins in this bank
  95  * @name: name of the bank
  96  * @bank_num: number of the bank, to account for holes
  97  * @valid: are all necessary informations present
  98  * @of_node: dt node of this bank
  99  * @drvdata: common pinctrl basedata
 100  * @domain: irqdomain of the gpio bank
 101  * @gpio_chip: gpiolib chip
 102  * @grange: gpio range
 103  * @slock: spinlock for the gpio bank
 104  */
 105 struct rockchip_pin_bank {
 106         void __iomem                    *reg_base;
 107         void __iomem                    *reg_pull;
 108         struct clk                      *clk;
 109         int                             irq;
 110         u32                             pin_base;
 111         u8                              nr_pins;
 112         char                            *name;
 113         u8                              bank_num;
 114         enum rockchip_pin_bank_type     bank_type;
 115         bool                            valid;
 116         struct device_node              *of_node;
 117         struct rockchip_pinctrl         *drvdata;
 118         struct irq_domain               *domain;
 119         struct gpio_chip                gpio_chip;
 120         struct pinctrl_gpio_range       grange;
 121         spinlock_t                      slock;
 122         u32                             toggle_edge_mode;
 123         u32                             suspend_wakeup;
 124         u32                             saved_wakeup;
 125 };
 126
 127 #define PIN_BANK(id, pins, label)                       \
 128         {                                               \
 129                 .bank_num       = id,                   \
 130                 .nr_pins        = pins,                 \
 131                 .name           = label,                \
 132         }
 133
 134 /**
 135  */
 136 struct rockchip_pin_ctrl {
 137         struct rockchip_pin_bank        *pin_banks;
 138         u32                             nr_banks;
 139         u32                             nr_pins;
 140         char                            *label;
 141         enum rockchip_pinctrl_type      type;
 142         int                             mux_offset;
 143         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
 144                                  void __iomem **reg, u8 *bit);
 145 };
 146
 147 struct rockchip_pin_config {
 148         unsigned int            func;
 149         unsigned long           *configs;
 150         unsigned int            nconfigs;
 151 };
 152
 153 /**
 154  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 155  * @name: name of the pin group, used to lookup the group.
 156  * @pins: the pins included in this group.
 157  * @npins: number of pins included in this group.
 158  * @func: the mux function number to be programmed when selected.
 159  * @configs: the config values to be set for each pin
 160  * @nconfigs: number of configs for each pin
 161  */
 162 struct rockchip_pin_group {
 163         const char                      *name;
 164         const char                      *func_name;
 165         unsigned int                    npins;
 166         unsigned int                    *pins;
 167         struct rockchip_pin_config      *data;
 168 };
 169
 170 /**
 171  * struct rockchip_pmx_func: represent a pin function.
 172  * @name: name of the pin function, used to lookup the function.
 173  * @groups: one or more names of pin groups that provide this function.
 174  * @num_groups: number of groups included in @groups.
 175  */
 176 struct rockchip_pmx_func {
 177         const char              *name;
 178         const char              **groups;
 179         u8                      ngroups;
 180 };
 181
 182 struct rockchip_pinctrl {
 183         void __iomem                    *reg_base;
 184         void __iomem                    *reg_pull;
 185         struct device                   *dev;
 186         struct rockchip_pin_ctrl        *ctrl;
 187         struct pinctrl_desc             pctl;
 188         struct pinctrl_dev              *pctl_dev;
 189         struct rockchip_pin_group       *groups;
 190         unsigned int                    ngroups;
 191         struct rockchip_pmx_func        *functions;
 192         unsigned int                    nfunctions;
 193
 194         atomic_t                        debug_flag;
 195 };
 196
 197 struct iomux_mode{
 198         unsigned int mode:4,
 199                      off:4,
 200                      goff:4,
 201                      bank:4,
 202                      reserve:16;
 203 };
 204
 205 struct union_mode{
 206         union{
 207                 struct iomux_mode mux;
 208                 unsigned int mode;
 209         };
 210 };
 211
 212 struct func_to_reg_offset {
 213         unsigned int reg_type;
 214         const char *vol_name;
 215         const char *func_name;
 216         const char *group_name;
 217         unsigned int reg_offset;
 218         unsigned int bit_offset;
 219         unsigned int bit_mask;
 220 };
 221
 222 #define FUNC_GROUP_TO_REG_OFFSET(type, vol, func, group, reg, bit, mask)        \
 223         {                                               \
 224                 .reg_type       = type,         \
 225                 .vol_name       = vol,          \
 226                 .func_name      = func,         \
 227                 .group_name     = group,        \
 228                 .reg_offset     = reg,          \
 229                 .bit_offset     = bit,          \
 230                 .bit_mask       = mask,         \
 231         }
 232
 233
 234
 235 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 236 {
 237         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 238 }
 239
 240 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 241                                         const struct rockchip_pinctrl *info,
 242                                         const char *name)
 243 {
 244         int i;
 245
 246         for (i = 0; i < info->ngroups; i++) {
 247                 if (!strcmp(info->groups[i].name, name))
 248                         return &info->groups[i];
 249         }
 250
 251         return NULL;
 252 }
 253
 254 /*
 255  * given a pin number that is local to a pin controller, find out the pin bank
 256  * and the register base of the pin bank.
 257  */
 258 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 259                                                                 unsigned pin)
 260 {
 261         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 262
 263         while (pin >= (b->pin_base + b->nr_pins))
 264                 b++;
 265
 266         return b;
 267 }
 268
 269 static struct rockchip_pin_bank *bank_num_to_bank(
 270                                         struct rockchip_pinctrl *info,
 271                                         unsigned num)
 272 {
 273         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 274         int i;
 275
 276         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 277                 if (b->bank_num == num)
 278                         return b;
 279         }
 280
 281         return ERR_PTR(-EINVAL);
 282 }
 283
 284 /*
 285  * Pinctrl_ops handling
 286  */
 287
 288 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 289 {
 290         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 291
 292         return info->ngroups;
 293 }
 294
 295 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 296                                                         unsigned selector)
 297 {
 298         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 299
 300         return info->groups[selector].name;
 301 }
 302
 303 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 304                                       unsigned selector, const unsigned **pins,
 305                                       unsigned *npins)
 306 {
 307         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 308
 309         if (selector >= info->ngroups)
 310                 return -EINVAL;
 311
 312         *pins = info->groups[selector].pins;
 313         *npins = info->groups[selector].npins;
 314
 315         return 0;
 316 }
 317
 318 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 319                                  struct device_node *np,
 320                                  struct pinctrl_map **map, unsigned *num_maps)
 321 {
 322         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 323         const struct rockchip_pin_group *grp;
 324         struct pinctrl_map *new_map;
 325         struct device_node *parent;
 326         int map_num = 1;
 327         int i;
 328
 329         /*
 330          * first find the group of this node and check if we need to create
 331          * config maps for pins
 332          */
 333         grp = pinctrl_name_to_group(info, np->name);
 334         if (!grp) {
 335                 dev_err(info->dev, "unable to find group for node %s\n",
 336                         np->name);
 337                 return -EINVAL;
 338         }
 339
 340         map_num += grp->npins;
 341         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 342                                                                 GFP_KERNEL);
 343         if (!new_map)
 344                 return -ENOMEM;
 345
 346         *map = new_map;
 347         *num_maps = map_num;
 348
 349         /* create mux map */
 350         parent = of_get_parent(np);
 351         if (!parent) {
 352                 devm_kfree(pctldev->dev, new_map);
 353                 return -EINVAL;
 354         }
 355         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 356         new_map[0].data.mux.function = parent->name;
 357         new_map[0].data.mux.group = np->name;
 358         of_node_put(parent);
 359
 360         /* create config map */
 361         new_map++;
 362         for (i = 0; i < grp->npins; i++) {
 363                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 364                 new_map[i].data.configs.group_or_pin = grp->name;
 365                                 //pin_get_name(pctldev, grp->pins[i]);
 366                 new_map[i].data.configs.configs = grp->data[i].configs;
 367                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 368         }
 369
 370         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 371                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 372
 373         return 0;
 374 }
 375
 376 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 377                                     struct pinctrl_map *map, unsigned num_maps)
 378 {
 379 }
 380
 381 static const struct pinctrl_ops rockchip_pctrl_ops = {
 382         .get_groups_count       = rockchip_get_groups_count,
 383         .get_group_name         = rockchip_get_group_name,
 384         .get_group_pins         = rockchip_get_group_pins,
 385         .dt_node_to_map         = rockchip_dt_node_to_map,
 386         .dt_free_map            = rockchip_dt_free_map,
 387 };
 388
 389
 390
 391 /*
 392  * Set a new mux function for a pin.
 393  *
 394  * The register is divided into the upper and lower 16 bit. When changing
 395  * a value, the previous register value is not read and changed. Instead
 396  * it seems the changed bits are marked in the upper 16 bit, while the
 397  * changed value gets set in the same offset in the lower 16 bit.
 398  * All pin settings seem to be 2 bit wide in both the upper and lower
 399  * parts.
 400  * @bank: pin bank to change
 401  * @pin: pin to change
 402  * @mux: new mux function to set
 403  */
 404 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 405 {
 406         struct rockchip_pinctrl *info = bank->drvdata;
 407         void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 408         unsigned long flags;
 409         u8 bit;
 410         u32 data;
 411         struct union_mode m;
 412
 413         /* GPIO0_C */
 414         /*GPIO0_C0 = 0x0c00, NAND_D8, */
 415         /*GPIO0_C1 = 0x0c10, NAND_D9, */
 416
 417         if(bank->bank_num == 15)
 418         {
 419                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
 420                 return ;
 421         }
 422
 423         m.mode = mux;
 424
 425         if((m.mux.bank != bank->bank_num) || (((m.mux.goff - 0x0A) * 8 + m.mux.off ) != pin))
 426         {
 427                 printk("%s:error:mux_bank(%d) != gpio_bank(%d), mux_offset(%d) != gpio_offset(%d)\n",__func__,
 428                 m.mux.bank, bank->bank_num, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), pin);
 429                 return;
 430         }
 431
 432         /* get basic quadrupel of mux registers and the correct reg inside */
 433         reg += bank->bank_num * 0x10;
 434         reg += (pin / 8) * 4;
 435         bit = (pin % 8) * 2;
 436
 437         spin_lock_irqsave(&bank->slock, flags);
 438
 439         data = (3 << (bit + 16));
 440         data |= (mux & 3) << bit;
 441         writel(data, reg);
 442
 443         spin_unlock_irqrestore(&bank->slock, flags);
 444
 445         DBG_PINCTRL("%s:setting GPIO%d-%d to mux:0x%x\n", __func__, m.mux.bank, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), mux);
 446
 447         //DBG_PINCTRL("%s:setting mux of GPIO%d-%d to %d\n", __func__, bank->bank_num, pin, mux&0x3);
 448 }
 449
 450
 451 /*
 452  * Pinmux_ops handling
 453  */
 454
 455 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 456 {
 457         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 458
 459         return info->nfunctions;
 460 }
 461
 462 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 463                                           unsigned selector)
 464 {
 465         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 466
 467         return info->functions[selector].name;
 468 }
 469
 470 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 471                                 unsigned selector, const char * const **groups,
 472                                 unsigned * const num_groups)
 473 {
 474         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 475
 476         *groups = info->functions[selector].groups;
 477         *num_groups = info->functions[selector].ngroups;
 478
 479         return 0;
 480 }
 481
 482 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 483                                                             unsigned group)
 484 {
 485         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 486         const unsigned int *pins = info->groups[group].pins;
 487         const struct rockchip_pin_config *data = info->groups[group].data;
 488         struct rockchip_pin_bank *bank;
 489         int cnt;
 490
 491         DBG_PINCTRL("%s:enable function %s group %s\n",
 492                 __func__, info->functions[selector].name, info->groups[group].name);
 493
 494         /*
 495          * for each pin in the pin group selected, program the correspoding pin
 496          * pin function number in the config register.
 497          */
 498         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 499                 bank = pin_to_bank(info, pins[cnt]);
 500                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 501                                  data[cnt].func);
 502         }
 503
 504         return 0;
 505 }
 506
 507 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 508                                         unsigned selector, unsigned group)
 509 {
 510         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 511         const unsigned int *pins = info->groups[group].pins;
 512         struct rockchip_pin_bank *bank;
 513         int cnt;
 514
 515         DBG_PINCTRL("%s:disable function %s group %s\n",
 516                 __func__, info->functions[selector].name, info->groups[group].name);
 517
 518         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 519                 bank = pin_to_bank(info, pins[cnt]);
 520                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 521         }
 522 }
 523
 524 /*
 525  * The calls to gpio_direction_output() and gpio_direction_input()
 526  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 527  * function called from the gpiolib interface).
 528  */
 529 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 530                                               struct pinctrl_gpio_range *range,
 531                                               unsigned offset, bool input)
 532 {
 533         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 534         struct rockchip_pin_bank *bank;
 535         struct gpio_chip *chip;
 536         int pin;
 537         u32 data;
 538         u32 mux;
 539
 540         chip = range->gc;
 541         bank = gc_to_pin_bank(chip);
 542         pin = offset - chip->base;
 543
 544         DBG_PINCTRL("%s:gpio_direction for pin %u as %s-%d to %s\n",
 545                  __func__, offset, range->name, pin, input ? "input" : "output");
 546
 547         mux = (bank->bank_num << 12) | (((pin / 8) + 0x0A) << 8) | ((pin % 8)<< 4) | RK_FUNC_GPIO;
 548
 549         rockchip_set_mux(bank, pin, mux);
 550
 551         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 552         /* set bit to 1 for output, 0 for input */
 553         if (!input)
 554                 data |= BIT(pin);
 555         else
 556                 data &= ~BIT(pin);
 557         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 558
 559         return 0;
 560 }
 561
 562 static const struct pinmux_ops rockchip_pmx_ops = {
 563         .get_functions_count    = rockchip_pmx_get_funcs_count,
 564         .get_function_name      = rockchip_pmx_get_func_name,
 565         .get_function_groups    = rockchip_pmx_get_groups,
 566         .enable                 = rockchip_pmx_enable,
 567         .disable                = rockchip_pmx_disable,
 568         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 569 };
 570
 571
 572
 573 /*
 574  * Hardware access
 575  */
 576
 577 static struct func_to_reg_offset rk3188_func_to_drv_reg_offset[] =
 578 {
 579         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL",  "reserve" ,"NULL", RK3188_GRF_IO_CON0, 0 ,3),
 580         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_flash" ,"NULL", RK3188_GRF_IO_CON0, 2, 3),
 581         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_flash" ,"NULL", RK3188_GRF_IO_CON0, 4 ,3),
 582         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_d" ,"NULL", RK3188_GRF_IO_CON0, 6 ,3),
 583         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio1_uart0" ,"NULL", RK3188_GRF_IO_CON0, 8 ,3),
 584         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_uart1" ,"NULL", RK3188_GRF_IO_CON0, 10 ,3),
 585         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_spi0" ,"NULL", RK3188_GRF_IO_CON0, 10 ,3),
 586         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "gpio1_uart2" ,"NULL", RK3188_GRF_IO_CON0, 12 ,3),
 587         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio1_uart3" ,"NULL", RK3188_GRF_IO_CON0, 14 ,3),
 588         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio1_spi1" ,"NULL", RK3188_GRF_IO_CON0, 14 ,3),
 589
 590         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2s0" ,"NULL", RK3188_GRF_IO_CON1, 0 ,3),
 591         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2s0" ,"NULL", RK3188_GRF_IO_CON1, 2 ,3),
 592         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_c" ,"NULL", RK3188_GRF_IO_CON1, 4 ,3),
 593         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c0" ,"NULL", RK3188_GRF_IO_CON1, 6 ,3),
 594         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c1" ,"NULL", RK3188_GRF_IO_CON1, 8 ,3),
 595         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c2" ,"NULL", RK3188_GRF_IO_CON1, 10 ,3),
 596         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2c4" ,"NULL", RK3188_GRF_IO_CON1, 12 ,3),
 597         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_lcdc1" ,"NULL", RK3188_GRF_IO_CON1, 14 ,3),
 598
 599         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_lcdc1" ,"NULL", RK3188_GRF_IO_CON2, 0 ,3),
 600         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_smc" ,"NULL", RK3188_GRF_IO_CON2, 2 ,3),
 601         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "reserve" ,"NULL", RK3188_GRF_IO_CON2, 4 ,3),
 602         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_sdmmc" ,"NULL", RK3188_GRF_IO_CON2, 6 ,3),
 603         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_sdmmc" ,"NULL", RK3188_GRF_IO_CON2, 8 ,3),
 604         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_b" ,"NULL", RK3188_GRF_IO_CON2, 10 ,3),
 605         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_cif" ,"NULL", RK3188_GRF_IO_CON2, 12 ,3),
 606         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_cif" ,"NULL", RK3188_GRF_IO_CON2, 14 ,3),
 607
 608         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_sdio" ,"NULL", RK3188_GRF_IO_CON3, 0 ,3),
 609         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_sdio" ,"NULL", RK3188_GRF_IO_CON3, 2 ,3),
 610         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_pwm" ,"NULL", RK3188_GRF_IO_CON3, 4 ,3),
 611         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_d" ,"NULL", RK3188_GRF_IO_CON3, 6 ,3),
 612         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "flash" ,"NULL", RK3188_GRF_IO_CON3, 8 ,3),
 613         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "flash" ,"NULL", RK3188_GRF_IO_CON3, 10 ,3),
 614         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "cif" ,"NULL", RK3188_GRF_IO_CON3, 12 ,3),
 615         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc0-vcc", "lcdc0" ,"NULL", RK3188_GRF_IO_CON3, 14 ,3),
 616
 617         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc0-vcc", "lcdc0" ,"NULL", RK3188_GRF_IO_CON4, 0 ,3),
 618         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "jtag" ,"NULL", RK3188_GRF_IO_CON4, 2 ,3),
 619         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "misc" ,"NULL", RK3188_GRF_IO_CON4, 4 ,3),
 620         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "reserve" ,"NULL", RK3188_GRF_IO_CON4, 6 ,3),
 621
 622 };
 623
 624 static struct func_to_reg_offset rk3188_func_to_vol_reg_offset[] =
 625 {
 626         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "ap0-vcc", "vol_domain", "ap0-vcc", RK3188_GRF_IO_CON4, 8 ,1),
 627         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "ap1-vcc", "vol_domain", "ap1-vcc", RK3188_GRF_IO_CON4, 9 ,1),
 628         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "cif-vcc", "vol_domain", "cif-vcc", RK3188_GRF_IO_CON4, 10 ,1),
 629         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash-vcc", "vol_domain", "flash-vcc", RK3188_GRF_IO_CON4, 11 ,1),
 630         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "vccio0-vcc", "vol_domain", "vccio0-vcc", RK3188_GRF_IO_CON4, 12 ,1),
 631         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "vccio1-vcc", "vol_domain", "vccio1-vcc", RK3188_GRF_IO_CON4, 13 ,1),
 632         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc0-vcc", "vol_domain", "lcdc0-vcc", RK3188_GRF_IO_CON4, 14 ,1),
 633         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc1-vcc", "vol_domain", "lcdc1-vcc", RK3188_GRF_IO_CON4, 15 ,1),
 634 };
 635
 636 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 637                                     int pin_num, void __iomem **reg, u8 *bit)
 638 {
 639         struct rockchip_pinctrl *info = bank->drvdata;
 640
 641         *reg = info->reg_base + RK2928_PULL_OFFSET;
 642         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 643         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 644
 645         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 646
 647         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%p, bit=%d\n", __func__, bank->bank_num, pin_num, *reg, *bit);
 648 };
 649
 650
 651 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 652                                     int pin_num, void __iomem **reg, u8 *bit)
 653 {
 654         struct rockchip_pinctrl *info = bank->drvdata;
 655
 656         /* The first 12 pins of the first bank are located elsewhere */
 657         if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
 658                 *reg = bank->reg_pull +
 659                                 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 660                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 661                 *bit *= RK3188_PULL_BITS_PER_PIN;
 662         } else {
 663                 *reg = info->reg_pull - 4;
 664                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 665                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 666
 667                 /*
 668                  * The bits in these registers have an inverse ordering
 669                  * with the lowest pin being in bits 15:14 and the highest
 670                  * pin in bits 1:0
 671                  */
 672                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 673                 *bit *= RK3188_PULL_BITS_PER_PIN;
 674         }
 675
 676         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%p, bit=%d\n", __func__, bank->bank_num, pin_num, *reg, *bit);
 677 }
 678
 679 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 680 {
 681         struct rockchip_pinctrl *info = bank->drvdata;
 682         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 683         void __iomem *reg;
 684         u8 bit;
 685         u32 data;
 686
 687         /* rk3066b does support any pulls */
 688         if (ctrl->type == RK3066B)
 689                 return PIN_CONFIG_BIAS_DISABLE;
 690
 691         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 692
 693         switch (ctrl->type) {
 694         case RK2928:
 695                 return !(readl_relaxed(reg) & BIT(bit))
 696                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 697                                 : PIN_CONFIG_BIAS_DISABLE;
 698         case RK3188:
 699                 data = readl_relaxed(reg) >> bit;
 700                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 701
 702                 switch (data) {
 703                 case 0:
 704                         return PIN_CONFIG_BIAS_DISABLE;
 705                 case 1:
 706                         return PIN_CONFIG_BIAS_PULL_UP;
 707                 case 2:
 708                         return PIN_CONFIG_BIAS_PULL_DOWN;
 709                 case 3:
 710                         return PIN_CONFIG_BIAS_BUS_HOLD;
 711                 }
 712
 713                 dev_err(info->dev, "unknown pull setting\n");
 714                 return -EIO;
 715         default:
 716                 dev_err(info->dev, "unsupported pinctrl type\n");
 717                 return -EINVAL;
 718         };
 719
 720         DBG_PINCTRL("%s:GPIO%d-%d pull is 0x%x\n", __func__, bank->bank_num, pin_num, data);
 721 }
 722
 723 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 724                                         int pin_num, int pull)
 725 {
 726         struct rockchip_pinctrl *info = bank->drvdata;
 727         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 728         void __iomem *reg;
 729         unsigned long flags;
 730         u8 bit;
 731         u32 data;
 732
 733
 734         /* rk3066b does support any pulls */
 735         if (ctrl->type == RK3066B)
 736                 return pull ? -EINVAL : 0;
 737
 738         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 739
 740         switch (ctrl->type) {
 741         case RK2928:
 742                 spin_lock_irqsave(&bank->slock, flags);
 743
 744                 data = BIT(bit + 16);
 745                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 746                         data |= BIT(bit);
 747                 writel(data, reg);
 748
 749                 spin_unlock_irqrestore(&bank->slock, flags);
 750                 break;
 751         case RK3188:
 752                 spin_lock_irqsave(&bank->slock, flags);
 753
 754                 /* enable the write to the equivalent lower bits */
 755                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 756
 757                 switch (pull) {
 758                 case PIN_CONFIG_BIAS_DISABLE:
 759                         break;
 760                 case PIN_CONFIG_BIAS_PULL_UP:
 761                         data |= (1 << bit);
 762                         break;
 763                 case PIN_CONFIG_BIAS_PULL_DOWN:
 764                         data |= (2 << bit);
 765                         break;
 766                 case PIN_CONFIG_BIAS_BUS_HOLD:
 767                         data |= (3 << bit);
 768                         break;
 769                 default:
 770                         dev_err(info->dev, "unsupported pull setting %d\n",
 771                                 pull);
 772                         return -EINVAL;
 773                 }
 774
 775                 writel(data, reg);
 776
 777                 spin_unlock_irqrestore(&bank->slock, flags);
 778                 break;
 779         default:
 780                 dev_err(info->dev, "unsupported pinctrl type\n");
 781                 return -EINVAL;
 782         }
 783
 784
 785         DBG_PINCTRL("%s:GPIO%d-%d pull is 0x%x\n", __func__, bank->bank_num, pin_num, data);
 786
 787         return 0;
 788 }
 789
 790 /*
 791  * Pinconf_ops handling
 792  */
 793
 794 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 795                                         enum pin_config_param pull)
 796 {
 797         switch (ctrl->type) {
 798         case RK2928:
 799                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 800                                         pull == PIN_CONFIG_BIAS_DISABLE);
 801         case RK3066B:
 802                 return pull ? false : true;
 803         case RK3188:
 804                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 805         }
 806
 807         return false;
 808 }
 809
 810 static int _rockchip_pinconf_get(struct rockchip_pin_bank *bank,
 811                                         int pin_num, unsigned long *config, int config_type, unsigned group)
 812 {
 813         struct rockchip_pinctrl *info = bank->drvdata;
 814         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 815         struct func_to_reg_offset reg_offset[4];//same name count should be less four
 816         struct func_to_reg_offset *func_to_reg;
 817         int i = 0, ii = 0, j = 0, jj = 0, num = 0;
 818         int data = 0;
 819         unsigned long flags;
 820         void __iomem *reg;
 821
 822
 823         if(group < 0)
 824                 return -1;
 825
 826         DBG_PINCTRL("%s:GPIO%d-%d,group=%s, function=%s, type=%d\n", __func__, bank->bank_num, pin_num, info->groups[group].name, info->groups[group].func_name, config_type);
 827
 828         switch(ctrl->type)
 829         {
 830                 case RK2928:
 831                 //to do
 832                 break;
 833
 834                 case RK3066B:
 835
 836                 break;
 837
 838                 case RK3188:
 839
 840                 switch(config_type)
 841                 {
 842                         case TYPE_PULL_REG:
 843                         //compare pin num
 844
 845                         break;
 846
 847                         case TYPE_VOL_REG:
 848                         //compare group_name
 849                         func_to_reg = rk3188_func_to_vol_reg_offset;
 850                         num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
 851                         for(i = 0; i < num; i++)
 852                         {
 853                                 if(!strcmp(info->groups[group].name, func_to_reg[i].group_name))
 854                                 {
 855                                         reg_offset[j++] = func_to_reg[i];
 856                                         DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[i].group_name);
 857                                 }
 858                         }
 859
 860                         if(j == 0)
 861                         {
 862                                 func_to_reg = rk3188_func_to_drv_reg_offset;
 863                                 num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
 864                                 for(i = 0; i < num; i++)
 865                                 {
 866                                         if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
 867                                         {
 868
 869                                                 func_to_reg = rk3188_func_to_vol_reg_offset;
 870                                                 num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
 871                                                 for(ii = 0; ii < num; ii++)
 872                                                 {
 873                                                         if(!strcmp(func_to_reg[i].vol_name, func_to_reg[ii].group_name))
 874                                                         {
 875                                                                 reg_offset[jj++] = func_to_reg[ii];
 876                                                                 DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[ii].group_name);
 877                                                         }
 878                                                 }
 879
 880                                         }
 881                                 }
 882
 883
 884                                 j = jj;
 885
 886                         }
 887
 888
 889                         break;
 890
 891                         case TYPE_DRV_REG:
 892                         //compare func_name
 893                         func_to_reg = rk3188_func_to_drv_reg_offset;
 894                         num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
 895                         for(i = 0; i < num; i++)
 896                         {
 897                                 if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
 898                                 {
 899                                         reg_offset[j++] = func_to_reg[i];
 900                                         DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[i].func_name);
 901                                 }
 902                         }
 903
 904                         break;
 905
 906                         case TYPE_TRI_REG:
 907                         break;
 908
 909                         default:
 910                         break;
 911
 912                 }
 913
 914                 break;
 915
 916                 default:
 917                 break;
 918         }
 919
 920         if(j <= 0)
 921         {
 922                 printk("%s:could find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num);
 923                 return -1;
 924         }
 925
 926
 927         for(i=0; i < j; i++)
 928         {
 929                 reg = info->reg_base + reg_offset[i].reg_offset;
 930                 spin_lock_irqsave(&bank->slock, flags);
 931                 data = readl_relaxed(reg) >> reg_offset[i].bit_offset;
 932                 data &= reg_offset[i].bit_mask;
 933                 spin_unlock_irqrestore(&bank->slock, flags);
 934
 935                 *config = data;
 936
 937                 DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=0x%x,data[%d]=0x%x\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data);
 938         }
 939
 940
 941         return 0;
 942 }
 943
 944
 945
 946 static int _rockchip_pinconf_set(struct rockchip_pin_bank *bank,
 947                                         int pin_num, int param, int config_type, unsigned group)
 948 {
 949         struct rockchip_pinctrl *info = bank->drvdata;
 950         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 951         struct func_to_reg_offset reg_offset[4];//same name count should be less four
 952         struct func_to_reg_offset *func_to_reg;
 953         int i = 0, ii = 0, j = 0, jj = 0, num = 0;
 954         int data = 0;
 955         unsigned long flags;
 956         void __iomem *reg;
 957
 958
 959         if(group < 0)
 960                 return -1;
 961
 962         DBG_PINCTRL("%s:GPIO%d-%d,group=%s, function=%s, type=%d\n", __func__, bank->bank_num, pin_num, info->groups[group].name, info->groups[group].func_name, config_type);
 963
 964         switch(ctrl->type)
 965         {
 966                 case RK2928:
 967                 //to do
 968                 break;
 969
 970                 case RK3066B:
 971
 972                 break;
 973
 974                 case RK3188:
 975
 976                 switch(config_type)
 977                 {
 978                         case TYPE_PULL_REG:
 979                         //compare pin num
 980
 981                         break;
 982
 983                         case TYPE_VOL_REG:
 984                         //compare group_name
 985                         func_to_reg = rk3188_func_to_vol_reg_offset;
 986                         num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
 987                         for(i = 0; i < num; i++)
 988                         {
 989                                 if(!strcmp(info->groups[group].name, func_to_reg[i].group_name))
 990                                 {
 991                                         reg_offset[j++] = func_to_reg[i];
 992                                         DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[i].group_name);
 993                                 }
 994                         }
 995
 996                         if(j == 0)
 997                         {
 998                                 func_to_reg = rk3188_func_to_drv_reg_offset;
 999                                 num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1000                                 for(i = 0; i < num; i++)
1001                                 {
1002                                         if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1003                                         {
1004
1005                                                 func_to_reg = rk3188_func_to_vol_reg_offset;
1006                                                 num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1007                                                 for(ii = 0; ii < num; ii++)
1008                                                 {
1009                                                         if(!strcmp(rk3188_func_to_drv_reg_offset[i].vol_name, func_to_reg[ii].group_name))
1010                                                         {
1011                                                                 reg_offset[jj++] = func_to_reg[ii];
1012                                                                 DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[ii].group_name);
1013                                                         }
1014                                                 }
1015
1016                                         }
1017                                 }
1018
1019
1020                                 j = jj;
1021
1022                         }
1023
1024
1025                         break;
1026
1027                         case TYPE_DRV_REG:
1028                         //compare func_name
1029                         func_to_reg = rk3188_func_to_drv_reg_offset;
1030                         num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1031                         for(i = 0; i < num; i++)
1032                         {
1033                                 if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1034                                 {
1035                                         reg_offset[j++] = func_to_reg[i];
1036                                         DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[i].func_name);
1037                                 }
1038                         }
1039
1040                         break;
1041
1042                         case TYPE_TRI_REG:
1043                         break;
1044
1045                         default:
1046                         break;
1047
1048                 }
1049
1050                 break;
1051
1052                 default:
1053                 break;
1054         }
1055
1056         if(j <= 0)
1057         {
1058                 printk("%s:could find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num);
1059                 return -1;
1060         }
1061
1062         for(i=0; i < j; i++)
1063         {
1064                 reg = info->reg_base + reg_offset[i].reg_offset;
1065                 data |= ((param & reg_offset[i].bit_mask) << (16 + reg_offset[i].bit_offset));
1066                 data |= ((param & reg_offset[i].bit_mask) << reg_offset[i].bit_offset);
1067                 spin_lock_irqsave(&bank->slock, flags);
1068                 //writel_relaxed(data, reg);
1069                 spin_unlock_irqrestore(&bank->slock, flags);
1070
1071                 DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=0x%x,value[%d]=0x%x\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data);
1072         }
1073
1074
1075         return 0;
1076 }
1077
1078
1079
1080
1081
1082 /* set the pin config settings for a specified pin */
1083 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1084                                 unsigned long configs, unsigned group)
1085 {
1086         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1087         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1088         enum pin_config_param param;
1089         u16 arg;
1090         int rc;
1091
1092
1093         param = pinconf_to_config_param(configs);
1094         arg = pinconf_to_config_argument(configs);
1095
1096         switch (param) {
1097         case PIN_CONFIG_BIAS_DISABLE:
1098                 rc =  rockchip_set_pull(bank, pin - bank->pin_base,
1099                         param);
1100                 if (rc)
1101                         return rc;
1102                 break;
1103         case PIN_CONFIG_BIAS_PULL_UP:
1104         case PIN_CONFIG_BIAS_PULL_DOWN:
1105         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1106         case PIN_CONFIG_BIAS_BUS_HOLD:
1107                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1108                         return -ENOTSUPP;
1109
1110                 if (!arg)
1111                         return -EINVAL;
1112
1113                 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1114                         param);
1115                 if (rc)
1116                         return rc;
1117                 break;
1118
1119         case PIN_CONFIG_POWER_SOURCE:
1120                 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, param, TYPE_VOL_REG, group);
1121                 if (rc)
1122                 return rc;
1123                 break;
1124
1125         case PIN_CONFIG_DRIVE_STRENGTH:
1126                 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, param, TYPE_DRV_REG, group);
1127                 if (rc)
1128                 return rc;
1129                 break;
1130         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1131                 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, param, TYPE_TRI_REG, group);
1132                 if (rc)
1133                 return rc;
1134                 break;
1135         default:
1136                 return -ENOTSUPP;
1137                 break;
1138         }
1139
1140         DBG_PINCTRL("%s,pin=%d,param=%d\n",__func__,pin, param);
1141
1142         return 0;
1143 }
1144
1145 /* get the pin config settings for a specified pin */
1146 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1147                                                         unsigned long *config, unsigned group)
1148 {
1149         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1150         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1151         enum pin_config_param param = pinconf_to_config_param(*config);
1152         int rc;
1153
1154         switch (param) {
1155         case PIN_CONFIG_BIAS_DISABLE:
1156                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1157                         return -EINVAL;
1158
1159                 *config = 0;
1160                 break;
1161         case PIN_CONFIG_BIAS_PULL_UP:
1162         case PIN_CONFIG_BIAS_PULL_DOWN:
1163         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1164         case PIN_CONFIG_BIAS_BUS_HOLD:
1165                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1166                         return -ENOTSUPP;
1167
1168                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1169                         return -EINVAL;
1170
1171                 *config = 1;
1172                 break;
1173
1174         case PIN_CONFIG_POWER_SOURCE:
1175                 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_VOL_REG, group);
1176                 if (rc)
1177                 return rc;
1178                 break;
1179
1180         case PIN_CONFIG_DRIVE_STRENGTH:
1181                 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_DRV_REG, group);
1182                 if (rc)
1183                 return rc;
1184                 break;
1185         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1186                 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_TRI_REG, group);
1187                 if (rc)
1188                 return rc;
1189                 break;
1190
1191         default:
1192                 return -ENOTSUPP;
1193                 break;
1194         }
1195
1196
1197         DBG_PINCTRL("%s:pin=%d, param=%d\n",__func__, pin, param);
1198
1199         return 0;
1200 }
1201
1202 /* set the pin config settings for a specified pin group */
1203 static int rockchip_pinconf_group_set(struct pinctrl_dev *pctldev,
1204                         unsigned group, unsigned long config)
1205 {
1206         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1207         const unsigned int *pins;
1208         unsigned int cnt;
1209
1210         DBG_PINCTRL("%s:group[%d]:%s\n",__func__, group, info->groups[group].name);
1211         pins = info->groups[group].pins;
1212
1213         for (cnt = 0; cnt < info->groups[group].npins; cnt++)
1214                 rockchip_pinconf_set(pctldev, pins[cnt], config, group);
1215
1216         return 0;
1217 }
1218
1219 /* get the pin config settings for a specified pin group */
1220 static int rockchip_pinconf_group_get(struct pinctrl_dev *pctldev,
1221                                 unsigned int group, unsigned long *config)
1222 {
1223         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1224         const unsigned int *pins;
1225
1226         pins = info->groups[group].pins;
1227         rockchip_pinconf_get(pctldev, pins[0], config, group);
1228
1229         DBG_PINCTRL("%s:group[%d]:%s\n",__func__, group, info->groups[group].name);
1230         return 0;
1231 }
1232
1233 static void rockchip_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1234                                  struct seq_file *s, unsigned pin)
1235 {
1236         //to do
1237 }
1238
1239 static void rockchip_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
1240                                        struct seq_file *s, unsigned group)
1241 {
1242         //to do
1243 }
1244
1245
1246 static const struct pinconf_ops rockchip_pinconf_ops = {
1247         .pin_config_group_get           = rockchip_pinconf_group_get,
1248         .pin_config_group_set           = rockchip_pinconf_group_set,
1249         .pin_config_dbg_show            = rockchip_pinconf_dbg_show,
1250         .pin_config_group_dbg_show      = rockchip_pinconf_group_dbg_show,
1251 };
1252
1253 static const struct of_device_id rockchip_bank_match[] = {
1254         { .compatible = "rockchip,gpio-bank" },
1255         { .compatible = "rockchip,rk3188-gpio-bank0" },
1256         {},
1257 };
1258
1259 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1260                                                 struct device_node *np)
1261 {
1262         struct device_node *child;
1263
1264         for_each_child_of_node(np, child) {
1265                 if (of_match_node(rockchip_bank_match, child))
1266                         continue;
1267
1268                 info->nfunctions++;
1269                 info->ngroups += of_get_child_count(child);
1270         }
1271 }
1272
1273 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1274                                               struct rockchip_pin_group *grp,
1275                                               struct rockchip_pinctrl *info,
1276                                               u32 index)
1277 {
1278         struct rockchip_pin_bank *bank;
1279         int size;
1280         const __be32 *list;
1281         int i, j;
1282         struct union_mode m;
1283         int configlen = 0;
1284         unsigned long *pinconfig;
1285         u32 val;
1286
1287         DBG_PINCTRL("%s:group(%d): %s\n", __func__, index, np->name);
1288
1289         /* Initialise group */
1290         grp->name = np->name;
1291
1292         /*
1293          * the binding format is rockchip,pins = <mux>,
1294          * do sanity check and calculate pins number
1295          */
1296         list = of_get_property(np, "rockchip,pins", &size);
1297         /* we do not check return since it's safe node passed down */
1298         size /= sizeof(*list);
1299         if (!size || size % 1) {
1300                 dev_err(info->dev, "wrong pins number or pins and configs should be by 1\n");
1301                 return -EINVAL;
1302         }
1303
1304         grp->npins = size / 1;
1305
1306         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1307                                                 GFP_KERNEL);
1308         grp->data = devm_kzalloc(info->dev, grp->npins *
1309                                           sizeof(struct rockchip_pin_config),
1310                                         GFP_KERNEL);
1311         if (!grp->pins || !grp->data)
1312                 return -ENOMEM;
1313
1314         pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
1315
1316         for (i = 0; i < size; i++) {
1317                 m.mode = be32_to_cpu(*list++);
1318
1319                 bank = bank_num_to_bank(info, m.mux.bank);
1320                 if (IS_ERR(bank))
1321                         return PTR_ERR(bank);
1322
1323                 grp->pins[i] = bank->pin_base + (m.mux.goff - 0x0A) * 8 + m.mux.off;
1324                 grp->data[i].func = m.mode;
1325
1326
1327                 j = 0;
1328                 configlen = 0;
1329
1330                 if (of_find_property(np, "rockchip,pull", NULL))
1331                         configlen++;
1332                 if (of_find_property(np, "rockchip,voltage", NULL))
1333                         configlen++;
1334                 if (of_find_property(np, "rockchip,drive", NULL))
1335                         configlen++;
1336                 if (of_find_property(np, "rockchip,tristate", NULL))
1337                         configlen++;
1338
1339                 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
1340
1341                 if (!of_property_read_u32(np, "allwinner,pull", &val)) {
1342                         enum pin_config_param pull = PIN_CONFIG_END;
1343                         if (val == 1)
1344                                 pull = PIN_CONFIG_BIAS_PULL_UP;
1345                         else if (val == 2)
1346                                 pull = PIN_CONFIG_BIAS_PULL_DOWN;
1347
1348                         pinconfig[j++] = pinconf_to_config_packed(pull, 0);
1349                 }
1350
1351                 if (!of_property_read_u32(np, "rockchip,voltage", &val)) {
1352                         pinconfig[j++] =
1353                                 pinconf_to_config_packed(PIN_CONFIG_POWER_SOURCE,
1354                                                          val);
1355                 }
1356
1357                 if (!of_property_read_u32(np, "rockchip,drive", &val)) {
1358                         pinconfig[j++] =
1359                                 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
1360                                                          val);
1361                 }
1362
1363                 if (!of_property_read_u32(np, "rockchip,tristate", &val)) {
1364                         pinconfig[j++] =
1365                                 pinconf_to_config_packed(PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
1366                                                          val);
1367                 }
1368
1369                 grp->data[i].configs = pinconfig;
1370                 grp->data[i].nconfigs = configlen;
1371
1372         }
1373
1374         return 0;
1375 }
1376
1377
1378 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1379                                                 struct rockchip_pinctrl *info,
1380                                                 u32 index)
1381 {
1382         struct device_node *child;
1383         struct rockchip_pmx_func *func;
1384         struct rockchip_pin_group *grp;
1385         int ret;
1386         static u32 grp_index;
1387         u32 i = 0;
1388
1389         DBG_PINCTRL("%s:parse function(%d): %s\n", __func__, index, np->name);
1390
1391         func = &info->functions[index];
1392
1393         /* Initialise function */
1394         func->name = np->name;
1395         func->ngroups = of_get_child_count(np);
1396         if (func->ngroups <= 0)
1397                 return 0;
1398
1399         func->groups = devm_kzalloc(info->dev,
1400                         func->ngroups * sizeof(char *), GFP_KERNEL);
1401         if (!func->groups)
1402                 return -ENOMEM;
1403
1404         for_each_child_of_node(np, child) {
1405                 func->groups[i] = child->name;
1406                 grp = &info->groups[grp_index++];
1407                 grp->func_name = np->name;
1408                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1409                 if (ret)
1410                         return ret;
1411
1412                 //DBG_PINCTRL("%s:grp->func_name(%d): %s\n", __func__, grp_index, grp->func_name);
1413         }
1414
1415         return 0;
1416 }
1417
1418 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1419                                               struct rockchip_pinctrl *info)
1420 {
1421         struct device *dev = &pdev->dev;
1422         struct device_node *np = dev->of_node;
1423         struct device_node *child;
1424         int ret;
1425         int i;
1426
1427         rockchip_pinctrl_child_count(info, np);
1428
1429         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1430         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1431
1432         info->functions = devm_kzalloc(dev, info->nfunctions *
1433                                               sizeof(struct rockchip_pmx_func),
1434                                               GFP_KERNEL);
1435         if (!info->functions) {
1436                 dev_err(dev, "failed to allocate memory for function list\n");
1437                 return -EINVAL;
1438         }
1439
1440         info->groups = devm_kzalloc(dev, info->ngroups *
1441                                             sizeof(struct rockchip_pin_group),
1442                                             GFP_KERNEL);
1443         if (!info->groups) {
1444                 dev_err(dev, "failed allocate memory for ping group list\n");
1445                 return -EINVAL;
1446         }
1447
1448         i = 0;
1449
1450         for_each_child_of_node(np, child) {
1451                 if (of_match_node(rockchip_bank_match, child))
1452                         continue;
1453
1454                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1455                 if (ret) {
1456                         dev_err(&pdev->dev, "failed to parse function\n");
1457                         return ret;
1458                 }
1459         }
1460
1461         return 0;
1462 }
1463
1464 static int rockchip_pinctrl_register(struct platform_device *pdev,
1465                                         struct rockchip_pinctrl *info)
1466 {
1467         struct pinctrl_desc *ctrldesc = &info->pctl;
1468         struct pinctrl_pin_desc *pindesc, *pdesc;
1469         struct rockchip_pin_bank *pin_bank;
1470         int pin, bank, ret;
1471         int k;
1472
1473         ctrldesc->name = "rockchip-pinctrl";
1474         ctrldesc->owner = THIS_MODULE;
1475         ctrldesc->pctlops = &rockchip_pctrl_ops;
1476         ctrldesc->pmxops = &rockchip_pmx_ops;
1477         ctrldesc->confops = &rockchip_pinconf_ops;
1478
1479         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1480                         info->ctrl->nr_pins, GFP_KERNEL);
1481         if (!pindesc) {
1482                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1483                 return -ENOMEM;
1484         }
1485         ctrldesc->pins = pindesc;
1486         ctrldesc->npins = info->ctrl->nr_pins;
1487
1488         pdesc = pindesc;
1489         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1490                 pin_bank = &info->ctrl->pin_banks[bank];
1491                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1492                         pdesc->number = k;
1493                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1494                                                 pin_bank->name, pin);
1495                         pdesc++;
1496                 }
1497         }
1498
1499         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1500         if (!info->pctl_dev) {
1501                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1502                 return -EINVAL;
1503         }
1504
1505         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1506                 pin_bank = &info->ctrl->pin_banks[bank];
1507                 pin_bank->grange.name = pin_bank->name;
1508                 pin_bank->grange.id = bank;
1509                 pin_bank->grange.pin_base = pin_bank->pin_base;
1510                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1511                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1512                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1513                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1514         }
1515
1516         ret = rockchip_pinctrl_parse_dt(pdev, info);
1517         if (ret) {
1518                 pinctrl_unregister(info->pctl_dev);
1519                 return ret;
1520         }
1521
1522         return 0;
1523 }
1524
1525 /*
1526  * GPIO handling
1527  */
1528
1529 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1530 {
1531         struct rockchip_pin_bank *bank = gc_to_pin_bank(chip);
1532         struct rockchip_pinctrl *info = bank->drvdata;
1533
1534         if(bank->bank_num == 15)
1535         {
1536                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
1537                 return -1;
1538         }
1539
1540
1541         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
1542         return pinctrl_request_gpio(chip->base + offset);
1543 }
1544
1545 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1546 {
1547         struct rockchip_pin_bank *bank = gc_to_pin_bank(chip);
1548         struct rockchip_pinctrl *info = bank->drvdata;
1549         if(bank->bank_num == 15)
1550         {
1551                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
1552                 return ;
1553         }
1554         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
1555         pinctrl_free_gpio(chip->base + offset);
1556 }
1557
1558 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1559 {
1560         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1561         struct rockchip_pinctrl *info = bank->drvdata;
1562         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1563         unsigned long flags;
1564         u32 data;
1565
1566         spin_lock_irqsave(&bank->slock, flags);
1567
1568         data = readl(reg);
1569         data &= ~BIT(offset);
1570         if (value)
1571                 data |= BIT(offset);
1572         writel(data, reg);
1573
1574         spin_unlock_irqrestore(&bank->slock, flags);
1575
1576         DBG_PINCTRL("%s:GPIO%d-%d level = %d\n", __func__, bank->bank_num, offset, value);
1577 }
1578
1579 /*
1580  * Returns the level of the pin for input direction and setting of the DR
1581  * register for output gpios.
1582  */
1583 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1584 {
1585         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1586         struct rockchip_pinctrl *info = bank->drvdata;
1587         u32 data;
1588
1589         data = readl(bank->reg_base + GPIO_EXT_PORT);
1590         data >>= offset;
1591         data &= 1;
1592
1593         DBG_PINCTRL("%s:GPIO%d-%d level = %d\n", __func__, bank->bank_num, offset, data);
1594         return data;
1595 }
1596
1597 /*
1598  * gpiolib gpio_direction_input callback function. The setting of the pin
1599  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1600  * interface.
1601  */
1602 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1603 {
1604         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1605         struct rockchip_pinctrl *info = bank->drvdata;
1606
1607         if(bank->bank_num == 15)
1608         {
1609                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
1610                 return -1;
1611         }
1612
1613         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
1614         return pinctrl_gpio_direction_input(gc->base + offset);
1615 }
1616
1617 /*
1618  * gpiolib gpio_direction_output callback function. The setting of the pin
1619  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1620  * interface.
1621  */
1622 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1623                                           unsigned offset, int value)
1624 {
1625         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1626         struct rockchip_pinctrl *info = bank->drvdata;
1627
1628         if(bank->bank_num == 15)
1629         {
1630                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
1631                 return -1;
1632         }
1633
1634         rockchip_gpio_set(gc, offset, value);
1635
1636         DBG_PINCTRL("%s:set GPIO%d-%d level %d\n", __func__, bank->bank_num, offset, value);
1637         return pinctrl_gpio_direction_output(gc->base + offset);
1638 }
1639
1640 /*
1641  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1642  * and a virtual IRQ, if not already present.
1643  */
1644 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1645 {
1646         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1647         struct rockchip_pinctrl *info = bank->drvdata;
1648
1649         unsigned int virq;
1650
1651         if(bank->bank_num == 15)
1652         {
1653                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
1654                 return -1;
1655         }
1656
1657         if (!bank->domain)
1658                 return -ENXIO;
1659
1660         virq = irq_create_mapping(bank->domain, offset);
1661
1662         DBG_PINCTRL("%s:virq=%d, GPIO%d-%d\n", __func__, virq, bank->bank_num, offset);
1663
1664         return (virq) ? : -ENXIO;
1665 }
1666
1667 static const struct gpio_chip rockchip_gpiolib_chip = {
1668         .request = rockchip_gpio_request,
1669         .free = rockchip_gpio_free,
1670         .set = rockchip_gpio_set,
1671         .get = rockchip_gpio_get,
1672         .direction_input = rockchip_gpio_direction_input,
1673         .direction_output = rockchip_gpio_direction_output,
1674         .to_irq = rockchip_gpio_to_irq,
1675         .owner = THIS_MODULE,
1676 };
1677
1678 /*
1679  * Interrupt handling
1680  */
1681
1682 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1683 {
1684         struct irq_chip *chip = irq_get_chip(irq);
1685         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1686         struct rockchip_pinctrl *info = bank->drvdata;
1687
1688         u32 polarity = 0, data = 0;
1689         u32 pend;
1690         bool edge_changed = false;
1691
1692         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1693
1694         chained_irq_enter(chip, desc);
1695
1696         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1697
1698         if (bank->toggle_edge_mode) {
1699                 polarity = readl_relaxed(bank->reg_base +
1700                                          GPIO_INT_POLARITY);
1701                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1702         }
1703
1704         while (pend) {
1705                 unsigned int virq;
1706
1707                 irq = __ffs(pend);
1708                 pend &= ~BIT(irq);
1709                 virq = irq_linear_revmap(bank->domain, irq);
1710
1711                 if (!virq) {
1712                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1713                         continue;
1714                 }
1715
1716                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1717
1718                 /*
1719                  * Triggering IRQ on both rising and falling edge
1720                  * needs manual intervention.
1721                  */
1722                 if (bank->toggle_edge_mode & BIT(irq)) {
1723                         if (data & BIT(irq))
1724                                 polarity &= ~BIT(irq);
1725                         else
1726                                 polarity |= BIT(irq);
1727
1728                         edge_changed = true;
1729                 }
1730
1731                 generic_handle_irq(virq);
1732
1733
1734                 DBG_PINCTRL("%s:irq=%d\n",__func__, irq);
1735         }
1736
1737         if (bank->toggle_edge_mode && edge_changed) {
1738                 /* Interrupt params should only be set with ints disabled */
1739                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1740                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1741                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1742                 writel(data, bank->reg_base + GPIO_INTEN);
1743         }
1744
1745         chained_irq_exit(chip, desc);
1746 }
1747
1748 static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1749 {
1750         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1751         struct rockchip_pinctrl *info = bank->drvdata;
1752         u32 mask = BIT(d->hwirq);
1753         u32 polarity;
1754         u32 level;
1755         u32 data;
1756         u32 mux;
1757         unsigned long flags;
1758
1759         DBG_PINCTRL("%s:type=%d,irq=%d,hwirq=%d\n",__func__,type, d->irq, (int)d->hwirq);
1760
1761         /* make sure the pin is configured as gpio input */
1762         mux = (bank->bank_num << 12) | (((d->hwirq / 8) + 0x0A) << 8) | ((d->hwirq % 8)<< 4) | RK_FUNC_GPIO;
1763         rockchip_set_mux(bank, d->hwirq, mux);
1764
1765         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1766         data &= ~mask;
1767         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1768
1769         if (type & IRQ_TYPE_EDGE_BOTH)
1770                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1771         else
1772                 __irq_set_handler_locked(d->irq, handle_level_irq);
1773
1774         spin_lock_irqsave(&bank->slock, flags);
1775
1776         level = readl_relaxed(bank->reg_base + GPIO_INTTYPE_LEVEL);
1777         polarity = readl_relaxed(bank->reg_base + GPIO_INT_POLARITY);
1778
1779         switch (type) {
1780         case IRQ_TYPE_EDGE_BOTH:
1781                 bank->toggle_edge_mode |= mask;
1782                 level |= mask;
1783
1784                 /*
1785                  * Determine gpio state. If 1 next interrupt should be falling
1786                  * otherwise rising.
1787                  */
1788                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1789                 if (data & mask)
1790                         polarity &= ~mask;
1791                 else
1792                         polarity |= mask;
1793                 break;
1794         case IRQ_TYPE_EDGE_RISING:
1795                 bank->toggle_edge_mode &= ~mask;
1796                 level |= mask;
1797                 polarity |= mask;
1798                 break;
1799         case IRQ_TYPE_EDGE_FALLING:
1800                 bank->toggle_edge_mode &= ~mask;
1801                 level |= mask;
1802                 polarity &= ~mask;
1803                 break;
1804         case IRQ_TYPE_LEVEL_HIGH:
1805                 bank->toggle_edge_mode &= ~mask;
1806                 level &= ~mask;
1807                 polarity |= mask;
1808                 break;
1809         case IRQ_TYPE_LEVEL_LOW:
1810                 bank->toggle_edge_mode &= ~mask;
1811                 level &= ~mask;
1812                 polarity &= ~mask;
1813                 break;
1814         default:
1815                 //spin_unlock_irqrestore(&bank->slock, flags);
1816                 return -EINVAL;
1817         }
1818
1819         writel_relaxed(level, bank->reg_base + GPIO_INTTYPE_LEVEL);
1820         writel_relaxed(polarity, bank->reg_base + GPIO_INT_POLARITY);
1821
1822         spin_unlock_irqrestore(&bank->slock, flags);
1823
1824         DBG_PINCTRL("%s:type=%d,irq=%d,hwirq=%d,ok\n",__func__,type, d->irq, (int)d->hwirq);
1825         return 0;
1826 }
1827 #if 0
1828 static int rockchip_interrupts_register(struct platform_device *pdev,
1829                                                 struct rockchip_pinctrl *info)
1830 {
1831         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1832         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1833         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1834         struct irq_chip_generic *gc;
1835         int ret;
1836         int i;
1837
1838         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1839                 if (!bank->valid) {
1840                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1841                                  bank->name);
1842                         continue;
1843                 }
1844
1845                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1846                                                 &irq_generic_chip_ops, NULL);
1847                 if (!bank->domain) {
1848                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1849                                  bank->name);
1850                         continue;
1851                 }
1852
1853                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1854                                          "rockchip_gpio_irq", handle_level_irq,
1855                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1856                 if (ret) {
1857                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1858                                 bank->name);
1859                         irq_domain_remove(bank->domain);
1860                         continue;
1861                 }
1862
1863                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1864                 gc->reg_base = bank->reg_base;
1865                 gc->private = bank;
1866                 gc->chip_types[0].regs.mask = GPIO_INTEN;
1867                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1868                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1869                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1870                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1871                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1872                 gc->chip_types[0].chip.irq_set_type = rockchip_gpio_irq_set_type;
1873
1874                 irq_set_handler_data(bank->irq, bank);
1875                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1876         }
1877
1878         return 0;
1879 }
1880 #else
1881
1882 static inline void rockchip_gpio_bit_op(void __iomem *reg_base, unsigned int offset, u32 bit, unsigned char flag)
1883 {
1884         u32 val = __raw_readl(reg_base + offset);
1885         if (flag)
1886                 val |= bit;
1887         else
1888                 val &= ~bit;
1889         __raw_writel(val, reg_base + offset);
1890 }
1891
1892 static inline unsigned gpio_to_bit(struct rockchip_pin_bank *bank, unsigned gpio)
1893 {
1894         while (gpio >= (bank->pin_base + bank->nr_pins))
1895                 bank++;
1896
1897         return gpio - bank->pin_base;
1898 }
1899
1900 static inline unsigned offset_to_bit(unsigned offset)
1901 {
1902         return 1u << offset;
1903 }
1904 #if 0
1905 static void GPIOSetPinLevel(void __iomem *reg_base, unsigned int bit, eGPIOPinLevel_t level)
1906 {
1907         rockchip_gpio_bit_op(reg_base, GPIO_SWPORT_DDR, bit, 1);
1908         rockchip_gpio_bit_op(reg_base, GPIO_SWPORT_DR, bit, level);
1909 }
1910
1911 static int GPIOGetPinLevel(void __iomem *reg_base, unsigned int bit)
1912 {
1913         return ((__raw_readl(reg_base + GPIO_EXT_PORT) & bit) != 0);
1914 }
1915
1916 static void GPIOSetPinDirection(void __iomem *reg_base, unsigned int bit, eGPIOPinDirection_t direction)
1917 {
1918         rockchip_gpio_bit_op(reg_base, GPIO_SWPORT_DDR, bit, direction);
1919         /* Enable debounce may halt cpu on wfi, disable it by default */
1920         //rockchip_gpio_bit_op(reg_base, GPIO_DEBOUNCE, bit, 1);
1921 }
1922 #endif
1923 static void GPIOEnableIntr(void __iomem *reg_base, unsigned int bit)
1924 {
1925         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 1);
1926 }
1927
1928 static void GPIODisableIntr(void __iomem *reg_base, unsigned int bit)
1929 {
1930         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 0);
1931 }
1932
1933 static void GPIOAckIntr(void __iomem *reg_base, unsigned int bit)
1934 {
1935         rockchip_gpio_bit_op(reg_base, GPIO_PORTS_EOI, bit, 1);
1936 }
1937 #if 0
1938 static void GPIOSetIntrType(void __iomem *reg_base, unsigned int bit, eGPIOIntType_t type)
1939 {
1940         switch (type) {
1941         case GPIOLevelLow:
1942                 rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 0);
1943                 rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 0);
1944                 break;
1945         case GPIOLevelHigh:
1946                 rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 0);
1947                 rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 1);
1948                 break;
1949         case GPIOEdgelFalling:
1950                 rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 1);
1951                 rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 0);
1952                 break;
1953         case GPIOEdgelRising:
1954                 rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 1);
1955                 rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 1);
1956                 break;
1957         }
1958 }
1959
1960 static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1961 {
1962         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1963         u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
1964         eGPIOIntType_t int_type;
1965         unsigned long flags;
1966
1967         switch (type) {
1968         case IRQ_TYPE_EDGE_RISING:
1969                 int_type = GPIOEdgelRising;
1970                 break;
1971         case IRQ_TYPE_EDGE_FALLING:
1972                 int_type = GPIOEdgelFalling;
1973                 break;
1974         case IRQ_TYPE_LEVEL_HIGH:
1975                 int_type = GPIOLevelHigh;
1976                 break;
1977         case IRQ_TYPE_LEVEL_LOW:
1978                 int_type = GPIOLevelLow;
1979                 break;
1980         default:
1981                 return -EINVAL;
1982         }
1983
1984         spin_lock_irqsave(&bank->slock, flags);
1985         //ÉèÖÃÎªÖÐ¶ÏÖ®Ç°£¬±ØÐëÏÈÉèÖÃÎªÊäÈë×´Ì¬
1986         GPIOSetPinDirection(bank->reg_base, bit, 0);
1987         GPIOSetIntrType(bank->reg_base, bit, int_type);
1988         spin_unlock_irqrestore(&bank->slock, flags);
1989
1990         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
1991                 __irq_set_handler_locked(d->irq, handle_level_irq);
1992         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
1993                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1994
1995         return 0;
1996 }
1997 #endif
1998 static int rockchip_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1999 {
2000         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2001         struct rockchip_pinctrl *info = bank->drvdata;
2002
2003         //u32 bit = gpio_to_bit(bank, d->irq);
2004         u32 bit = d->hwirq;
2005         unsigned long flags;
2006
2007         spin_lock_irqsave(&bank->slock, flags);
2008
2009         if (on)
2010                 bank->suspend_wakeup |= bit;
2011         else
2012                 bank->suspend_wakeup &= ~bit;
2013         spin_unlock_irqrestore(&bank->slock, flags);
2014
2015         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2016         return 0;
2017 }
2018
2019 static void rockchip_gpio_irq_unmask(struct irq_data *d)
2020 {
2021         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2022         struct rockchip_pinctrl *info = bank->drvdata;
2023         //u32 bit = gpio_to_bit(bank, d->irq);
2024         u32 bit = d->hwirq;
2025         unsigned long flags;
2026
2027         spin_lock_irqsave(&bank->slock, flags);
2028         GPIOEnableIntr(bank->reg_base, bit);
2029         spin_unlock_irqrestore(&bank->slock, flags);
2030
2031         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2032 }
2033
2034 static void rockchip_gpio_irq_mask(struct irq_data *d)
2035 {
2036         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2037         struct rockchip_pinctrl *info = bank->drvdata;
2038         //u32 bit = gpio_to_bit(bank, d->irq);
2039         u32 bit = d->hwirq;
2040         unsigned long flags;
2041
2042         spin_lock_irqsave(&bank->slock, flags);
2043         GPIODisableIntr(bank->reg_base, bit);
2044         spin_unlock_irqrestore(&bank->slock, flags);
2045
2046         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2047 }
2048
2049 static void rockchip_gpio_irq_ack(struct irq_data *d)
2050 {
2051         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2052         struct rockchip_pinctrl *info = bank->drvdata;
2053         //u32 bit = gpio_to_bit(bank, d->irq);
2054         u32 bit = d->hwirq;
2055
2056         GPIOAckIntr(bank->reg_base, bit);
2057
2058         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2059 }
2060
2061
2062 static struct irq_chip rockchip_gpio_irq_chip = {
2063         .name           = "GPIO",
2064         .irq_ack        = rockchip_gpio_irq_ack,
2065         .irq_disable    = rockchip_gpio_irq_mask,
2066         .irq_mask       = rockchip_gpio_irq_mask,
2067         .irq_unmask     = rockchip_gpio_irq_unmask,
2068         .irq_set_type   = rockchip_gpio_irq_set_type,
2069         .irq_set_wake   = rockchip_gpio_irq_set_wake,
2070 };
2071
2072
2073 static int rockchip_gpio_irq_map(struct irq_domain *d, unsigned int irq,
2074                                 irq_hw_number_t hwirq)
2075 {
2076         struct rockchip_pin_bank *bank = d->host_data;
2077         struct rockchip_pinctrl *info = bank->drvdata;
2078         struct irq_data *irq_data = irq_get_irq_data(irq);
2079
2080         if (!bank)
2081         {
2082                 printk("%s:bank=0x%p,irq=%d\n",__func__,bank, irq);
2083                 return -EINVAL;
2084         }
2085
2086         irq_set_chip_and_handler(irq, &rockchip_gpio_irq_chip, handle_level_irq);
2087         irq_set_chip_data(irq, bank);
2088         set_irq_flags(irq, IRQF_VALID);
2089
2090         irq_data->hwirq = hwirq;
2091         irq_data->irq = irq;
2092
2093         DBG_PINCTRL("%s:irq=%d\n",__func__,irq);
2094         return 0;
2095 }
2096
2097 const struct irq_domain_ops rockchip_gpio_irq_ops = {
2098         .map = rockchip_gpio_irq_map,
2099         .xlate = irq_domain_xlate_twocell,
2100 };
2101
2102
2103 static int rockchip_interrupts_register(struct platform_device *pdev,
2104                                                 struct rockchip_pinctrl *info)
2105 {
2106         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2107         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2108         //unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2109         int i;
2110
2111         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2112                 if (!bank->valid) {
2113                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2114                                  bank->name);
2115                         continue;
2116                 }
2117
2118                 __raw_writel(0, bank->reg_base + GPIO_INTEN);
2119
2120                 bank->drvdata = info;
2121                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2122                                 &rockchip_gpio_irq_ops, bank);
2123                 if (!bank->domain) {
2124                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2125                                  bank->name);
2126                         continue;
2127                 }
2128
2129
2130                 DBG_PINCTRL("%s:bank=%d\n",__func__,i);
2131
2132                 irq_set_handler_data(bank->irq, bank);
2133                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
2134         }
2135
2136
2137         return 0;
2138 }
2139
2140
2141 #endif
2142 static int rockchip_gpiolib_register(struct platform_device *pdev,
2143                                                 struct rockchip_pinctrl *info)
2144 {
2145         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2146         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2147         struct gpio_chip *gc;
2148         int ret;
2149         int i;
2150
2151         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2152                 if (!bank->valid) {
2153                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2154                                  bank->name);
2155                         continue;
2156                 }
2157
2158                 bank->gpio_chip = rockchip_gpiolib_chip;
2159
2160                 gc = &bank->gpio_chip;
2161                 gc->base = bank->pin_base;
2162                 gc->ngpio = bank->nr_pins;
2163                 gc->dev = &pdev->dev;
2164                 gc->of_node = bank->of_node;
2165                 gc->label = bank->name;
2166
2167                 ret = gpiochip_add(gc);
2168                 if (ret) {
2169                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2170                                                         gc->label, ret);
2171                         goto fail;
2172                 }
2173         }
2174
2175         rockchip_interrupts_register(pdev, info);
2176
2177         return 0;
2178
2179 fail:
2180         for (--i, --bank; i >= 0; --i, --bank) {
2181                 if (!bank->valid)
2182                         continue;
2183
2184                 if (gpiochip_remove(&bank->gpio_chip))
2185                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
2186                                                         bank->gpio_chip.label);
2187         }
2188         return ret;
2189 }
2190
2191 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2192                                                 struct rockchip_pinctrl *info)
2193 {
2194         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2195         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2196         int ret = 0;
2197         int i;
2198
2199         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
2200                 if (!bank->valid)
2201                         continue;
2202
2203                 ret = gpiochip_remove(&bank->gpio_chip);
2204         }
2205
2206         if (ret)
2207                 dev_err(&pdev->dev, "gpio chip remove failed\n");
2208
2209         return ret;
2210 }
2211
2212 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2213                                   struct device *dev)
2214 {
2215         struct resource res;
2216
2217         if (of_address_to_resource(bank->of_node, 0, &res)) {
2218                 dev_err(dev, "cannot find IO resource for bank\n");
2219                 return -ENOENT;
2220         }
2221
2222         bank->reg_base = devm_ioremap_resource(dev, &res);
2223         if (IS_ERR(bank->reg_base))
2224                 return PTR_ERR(bank->reg_base);
2225
2226         /*
2227          * special case, where parts of the pull setting-registers are
2228          * part of the PMU register space
2229          */
2230         if (of_device_is_compatible(bank->of_node,
2231                                     "rockchip,rk3188-gpio-bank0")) {
2232                 bank->bank_type = RK3188_BANK0;
2233
2234                 if (of_address_to_resource(bank->of_node, 1, &res)) {
2235                         dev_err(dev, "cannot find IO resource for bank\n");
2236                         return -ENOENT;
2237                 }
2238
2239                 bank->reg_pull = devm_ioremap_resource(dev, &res);
2240                 if (IS_ERR(bank->reg_pull))
2241                         return PTR_ERR(bank->reg_pull);
2242         } else {
2243                 bank->bank_type = COMMON_BANK;
2244         }
2245
2246         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2247
2248         bank->clk = of_clk_get(bank->of_node, 0);
2249         //if (IS_ERR(bank->clk))
2250                 //return PTR_ERR(bank->clk);
2251         return 0;
2252         //return clk_prepare_enable(bank->clk);
2253 }
2254
2255 static const struct of_device_id rockchip_pinctrl_dt_match[];
2256
2257 /* retrieve the soc specific data */
2258 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2259                                                 struct rockchip_pinctrl *d,
2260                                                 struct platform_device *pdev)
2261 {
2262         const struct of_device_id *match;
2263         struct device_node *node = pdev->dev.of_node;
2264         struct device_node *np;
2265         struct rockchip_pin_ctrl *ctrl;
2266         struct rockchip_pin_bank *bank;
2267         int i;
2268
2269         match = of_match_node(rockchip_pinctrl_dt_match, node);
2270         ctrl = (struct rockchip_pin_ctrl *)match->data;
2271
2272         for_each_child_of_node(node, np) {
2273                 if (!of_find_property(np, "gpio-controller", NULL))
2274                         continue;
2275
2276                 bank = ctrl->pin_banks;
2277                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2278                         if (!strcmp(bank->name, np->name)) {
2279                                 bank->of_node = np;
2280
2281                                 if (!rockchip_get_bank_data(bank, &pdev->dev))
2282                                         bank->valid = true;
2283                                 break;
2284                         }
2285                 }
2286         }
2287
2288         bank = ctrl->pin_banks;
2289         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2290                 spin_lock_init(&bank->slock);
2291                 bank->drvdata = d;
2292                 bank->pin_base = ctrl->nr_pins;
2293                 ctrl->nr_pins += bank->nr_pins;
2294         }
2295
2296         return ctrl;
2297 }
2298 #if 0
2299 static irqreturn_t pinctrl_interrupt_test(int irq, void *dev_id)
2300 {
2301         printk("%s:line=%d\n",__func__, __LINE__);
2302         return IRQ_HANDLED;
2303 }
2304 #endif
2305 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2306 {
2307         struct rockchip_pinctrl *info;
2308         struct device *dev = &pdev->dev;
2309         struct rockchip_pin_ctrl *ctrl;
2310         struct resource *res;
2311         int ret;
2312
2313         if (!dev->of_node) {
2314                 dev_err(dev, "device tree node not found\n");
2315                 return -ENODEV;
2316         }
2317
2318         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2319         if (!info)
2320                 return -ENOMEM;
2321
2322         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2323         if (!ctrl) {
2324                 dev_err(dev, "driver data not available\n");
2325                 return -EINVAL;
2326         }
2327         info->ctrl = ctrl;
2328         info->dev = dev;
2329
2330         atomic_set(&info->debug_flag, 1);
2331
2332         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2333         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
2334         if (IS_ERR(info->reg_base))
2335                 return PTR_ERR(info->reg_base);
2336
2337         /* The RK3188 has its pull registers in a separate place */
2338         if (ctrl->type == RK3188) {
2339                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2340                 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
2341                 if (IS_ERR(info->reg_base))
2342                         return PTR_ERR(info->reg_base);
2343         }
2344
2345         ret = rockchip_gpiolib_register(pdev, info);
2346         if (ret)
2347                 return ret;
2348
2349         ret = rockchip_pinctrl_register(pdev, info);
2350         if (ret) {
2351                 rockchip_gpiolib_unregister(pdev, info);
2352                 return ret;
2353         }
2354
2355         platform_set_drvdata(pdev, info);
2356 #if 0
2357         int i = 0;
2358         for(i=1; i<32*4; i++)
2359         {
2360                 if(i>23 && i<32+16)
2361                 continue;
2362                 gpio_request(i, NULL);
2363                 gpio_direction_input(i);
2364
2365                 ret = request_irq(gpio_to_irq(i), pinctrl_interrupt_test, IRQ_TYPE_EDGE_RISING, "test", info);
2366                 disable_irq(gpio_to_irq(i));
2367         }
2368 #endif
2369         printk("%s:init ok\n",__func__);
2370         return 0;
2371 }
2372
2373 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2374         PIN_BANK(0, 32, "gpio0"),
2375         PIN_BANK(1, 32, "gpio1"),
2376         PIN_BANK(2, 32, "gpio2"),
2377         PIN_BANK(3, 32, "gpio3"),
2378
2379         PIN_BANK(15, 32, "gpio15"),//virtual bank
2380 };
2381
2382 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2383                 .pin_banks              = rk2928_pin_banks,
2384                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2385                 .label                  = "RK2928-GPIO",
2386                 .type                   = RK2928,
2387                 .mux_offset             = 0xa8,
2388                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2389 };
2390
2391 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2392         PIN_BANK(0, 32, "gpio0"),
2393         PIN_BANK(1, 32, "gpio1"),
2394         PIN_BANK(2, 32, "gpio2"),
2395         PIN_BANK(3, 32, "gpio3"),
2396         PIN_BANK(4, 32, "gpio4"),
2397         PIN_BANK(6, 16, "gpio6"),
2398         PIN_BANK(15, 32, "gpio15"),//virtual bank
2399 };
2400
2401 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2402                 .pin_banks              = rk3066a_pin_banks,
2403                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2404                 .label                  = "RK3066a-GPIO",
2405                 .type                   = RK2928,
2406                 .mux_offset             = 0xa8,
2407                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2408 };
2409
2410 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2411         PIN_BANK(0, 32, "gpio0"),
2412         PIN_BANK(1, 32, "gpio1"),
2413         PIN_BANK(2, 32, "gpio2"),
2414         PIN_BANK(3, 32, "gpio3"),
2415
2416         PIN_BANK(15, 32, "gpio15"),//virtual bank
2417 };
2418
2419 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2420                 .pin_banks      = rk3066b_pin_banks,
2421                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2422                 .label          = "RK3066b-GPIO",
2423                 .type           = RK3066B,
2424                 .mux_offset     = 0x60,
2425 };
2426
2427 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2428         PIN_BANK(0, 32, "gpio0"),
2429         PIN_BANK(1, 32, "gpio1"),
2430         PIN_BANK(2, 32, "gpio2"),
2431         PIN_BANK(3, 32, "gpio3"),
2432
2433         PIN_BANK(15, 32, "gpio15"),//virtual bank
2434 };
2435
2436 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2437                 .pin_banks              = rk3188_pin_banks,
2438                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2439                 .label                  = "RK3188-GPIO",
2440                 .type                   = RK3188,
2441                 .mux_offset             = 0x60,
2442                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2443 };
2444
2445 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2446         { .compatible = "rockchip,rk2928-pinctrl",
2447                 .data = (void *)&rk2928_pin_ctrl },
2448         { .compatible = "rockchip,rk3066a-pinctrl",
2449                 .data = (void *)&rk3066a_pin_ctrl },
2450         { .compatible = "rockchip,rk3066b-pinctrl",
2451                 .data = (void *)&rk3066b_pin_ctrl },
2452         { .compatible = "rockchip,rk3188-pinctrl",
2453                 .data = (void *)&rk3188_pin_ctrl },
2454         {},
2455 };
2456 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2457
2458 static struct platform_driver rockchip_pinctrl_driver = {
2459         .probe          = rockchip_pinctrl_probe,
2460         .driver = {
2461                 .name   = "rockchip-pinctrl",
2462                 .owner  = THIS_MODULE,
2463                 .of_match_table = rockchip_pinctrl_dt_match,
2464         },
2465 };
2466
2467 static int __init rockchip_pinctrl_drv_register(void)
2468 {
2469         return platform_driver_register(&rockchip_pinctrl_driver);
2470 }
2471 postcore_initcall(rockchip_pinctrl_drv_register);
2472
2473 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2474 MODULE_DESCRIPTION("Rockchip pinctrl driver");
2475 MODULE_LICENSE("GPL v2");