drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <dt-bindings/pinctrl/rockchip.h>
  41
  42 #include "core.h"
  43 #include "pinconf.h"
  44
  45 /* GPIO control registers */
  46 #define GPIO_SWPORT_DR          0x00
  47 #define GPIO_SWPORT_DDR         0x04
  48 #define GPIO_INTEN              0x30
  49 #define GPIO_INTMASK            0x34
  50 #define GPIO_INTTYPE_LEVEL      0x38
  51 #define GPIO_INT_POLARITY       0x3c
  52 #define GPIO_INT_STATUS         0x40
  53 #define GPIO_INT_RAWSTATUS      0x44
  54 #define GPIO_DEBOUNCE           0x48
  55 #define GPIO_PORTS_EOI          0x4c
  56 #define GPIO_EXT_PORT           0x50
  57 #define GPIO_LS_SYNC            0x60
  58
  59 /**
  60  * @reg_base: register base of the gpio bank
  61  * @clk: clock of the gpio bank
  62  * @irq: interrupt of the gpio bank
  63  * @pin_base: first pin number
  64  * @nr_pins: number of pins in this bank
  65  * @name: name of the bank
  66  * @bank_num: number of the bank, to account for holes
  67  * @valid: are all necessary informations present
  68  * @of_node: dt node of this bank
  69  * @drvdata: common pinctrl basedata
  70  * @domain: irqdomain of the gpio bank
  71  * @gpio_chip: gpiolib chip
  72  * @grange: gpio range
  73  * @slock: spinlock for the gpio bank
  74  */
  75 struct rockchip_pin_bank {
  76         void __iomem                    *reg_base;
  77         struct clk                      *clk;
  78         int                             irq;
  79         u32                             pin_base;
  80         u8                              nr_pins;
  81         char                            *name;
  82         u8                              bank_num;
  83         bool                            valid;
  84         struct device_node              *of_node;
  85         struct rockchip_pinctrl         *drvdata;
  86         struct irq_domain               *domain;
  87         struct gpio_chip                gpio_chip;
  88         struct pinctrl_gpio_range       grange;
  89         spinlock_t                      slock;
  90
  91 };
  92
  93 #define PIN_BANK(id, pins, label)                       \
  94         {                                               \
  95                 .bank_num       = id,                   \
  96                 .nr_pins        = pins,                 \
  97                 .name           = label,                \
  98         }
  99
 100 /**
 101  * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but
 102  *             instead decide this automatically based on the pad-type.
 103  */
 104 struct rockchip_pin_ctrl {
 105         struct rockchip_pin_bank        *pin_banks;
 106         u32                             nr_banks;
 107         u32                             nr_pins;
 108         char                            *label;
 109         int                             mux_offset;
 110         int                             pull_offset;
 111         bool                            pull_auto;
 112         int                             pull_bank_stride;
 113 };
 114
 115 struct rockchip_pin_config {
 116         unsigned int            func;
 117         unsigned long           *configs;
 118         unsigned int            nconfigs;
 119 };
 120
 121 /**
 122  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 123  * @name: name of the pin group, used to lookup the group.
 124  * @pins: the pins included in this group.
 125  * @npins: number of pins included in this group.
 126  * @func: the mux function number to be programmed when selected.
 127  * @configs: the config values to be set for each pin
 128  * @nconfigs: number of configs for each pin
 129  */
 130 struct rockchip_pin_group {
 131         const char                      *name;
 132         unsigned int                    npins;
 133         unsigned int                    *pins;
 134         struct rockchip_pin_config      *data;
 135 };
 136
 137 /**
 138  * struct rockchip_pmx_func: represent a pin function.
 139  * @name: name of the pin function, used to lookup the function.
 140  * @groups: one or more names of pin groups that provide this function.
 141  * @num_groups: number of groups included in @groups.
 142  */
 143 struct rockchip_pmx_func {
 144         const char              *name;
 145         const char              **groups;
 146         u8                      ngroups;
 147 };
 148
 149 struct rockchip_pinctrl {
 150         void __iomem                    *reg_base;
 151         struct device                   *dev;
 152         struct rockchip_pin_ctrl        *ctrl;
 153         struct pinctrl_desc             pctl;
 154         struct pinctrl_dev              *pctl_dev;
 155         struct rockchip_pin_group       *groups;
 156         unsigned int                    ngroups;
 157         struct rockchip_pmx_func        *functions;
 158         unsigned int                    nfunctions;
 159 };
 160
 161 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 162 {
 163         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 164 }
 165
 166 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 167                                         const struct rockchip_pinctrl *info,
 168                                         const char *name)
 169 {
 170         int i;
 171
 172         for (i = 0; i < info->ngroups; i++) {
 173                 if (!strcmp(info->groups[i].name, name))
 174                         return &info->groups[i];
 175         }
 176
 177         return NULL;
 178 }
 179
 180 /*
 181  * given a pin number that is local to a pin controller, find out the pin bank
 182  * and the register base of the pin bank.
 183  */
 184 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 185                                                                 unsigned pin)
 186 {
 187         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 188
 189         while ((pin >= b->pin_base) &&
 190                         ((b->pin_base + b->nr_pins - 1) < pin))
 191                 b++;
 192
 193         return b;
 194 }
 195
 196 static struct rockchip_pin_bank *bank_num_to_bank(
 197                                         struct rockchip_pinctrl *info,
 198                                         unsigned num)
 199 {
 200         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 201         int i;
 202
 203         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 204                 if (b->bank_num == num)
 205                         return b;
 206         }
 207
 208         return ERR_PTR(-EINVAL);
 209 }
 210
 211 /*
 212  * Pinctrl_ops handling
 213  */
 214
 215 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 216 {
 217         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 218
 219         return info->ngroups;
 220 }
 221
 222 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 223                                                         unsigned selector)
 224 {
 225         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 226
 227         return info->groups[selector].name;
 228 }
 229
 230 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 231                                       unsigned selector, const unsigned **pins,
 232                                       unsigned *npins)
 233 {
 234         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 235
 236         if (selector >= info->ngroups)
 237                 return -EINVAL;
 238
 239         *pins = info->groups[selector].pins;
 240         *npins = info->groups[selector].npins;
 241
 242         return 0;
 243 }
 244
 245 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 246                                  struct device_node *np,
 247                                  struct pinctrl_map **map, unsigned *num_maps)
 248 {
 249         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 250         const struct rockchip_pin_group *grp;
 251         struct pinctrl_map *new_map;
 252         struct device_node *parent;
 253         int map_num = 1;
 254         int i;
 255
 256         /*
 257          * first find the group of this node and check if we need to create
 258          * config maps for pins
 259          */
 260         grp = pinctrl_name_to_group(info, np->name);
 261         if (!grp) {
 262                 dev_err(info->dev, "unable to find group for node %s\n",
 263                         np->name);
 264                 return -EINVAL;
 265         }
 266
 267         map_num += grp->npins;
 268         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 269                                                                 GFP_KERNEL);
 270         if (!new_map)
 271                 return -ENOMEM;
 272
 273         *map = new_map;
 274         *num_maps = map_num;
 275
 276         /* create mux map */
 277         parent = of_get_parent(np);
 278         if (!parent) {
 279                 devm_kfree(pctldev->dev, new_map);
 280                 return -EINVAL;
 281         }
 282         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 283         new_map[0].data.mux.function = parent->name;
 284         new_map[0].data.mux.group = np->name;
 285         of_node_put(parent);
 286
 287         /* create config map */
 288         new_map++;
 289         for (i = 0; i < grp->npins; i++) {
 290                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 291                 new_map[i].data.configs.group_or_pin =
 292                                 pin_get_name(pctldev, grp->pins[i]);
 293                 new_map[i].data.configs.configs = grp->data[i].configs;
 294                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 295         }
 296
 297         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 298                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 299
 300         return 0;
 301 }
 302
 303 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 304                                     struct pinctrl_map *map, unsigned num_maps)
 305 {
 306 }
 307
 308 static const struct pinctrl_ops rockchip_pctrl_ops = {
 309         .get_groups_count       = rockchip_get_groups_count,
 310         .get_group_name         = rockchip_get_group_name,
 311         .get_group_pins         = rockchip_get_group_pins,
 312         .dt_node_to_map         = rockchip_dt_node_to_map,
 313         .dt_free_map            = rockchip_dt_free_map,
 314 };
 315
 316 /*
 317  * Hardware access
 318  */
 319
 320 /*
 321  * Set a new mux function for a pin.
 322  *
 323  * The register is divided into the upper and lower 16 bit. When changing
 324  * a value, the previous register value is not read and changed. Instead
 325  * it seems the changed bits are marked in the upper 16 bit, while the
 326  * changed value gets set in the same offset in the lower 16 bit.
 327  * All pin settings seem to be 2 bit wide in both the upper and lower
 328  * parts.
 329  * @bank: pin bank to change
 330  * @pin: pin to change
 331  * @mux: new mux function to set
 332  */
 333 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 334 {
 335         struct rockchip_pinctrl *info = bank->drvdata;
 336         void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 337         unsigned long flags;
 338         u8 bit;
 339         u32 data;
 340
 341         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 342                                                 bank->bank_num, pin, mux);
 343
 344         /* get basic quadrupel of mux registers and the correct reg inside */
 345         reg += bank->bank_num * 0x10;
 346         reg += (pin / 8) * 4;
 347         bit = (pin % 8) * 2;
 348
 349         spin_lock_irqsave(&bank->slock, flags);
 350
 351         data = (3 << (bit + 16));
 352         data |= (mux & 3) << bit;
 353         writel(data, reg);
 354
 355         spin_unlock_irqrestore(&bank->slock, flags);
 356 }
 357
 358 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 359 {
 360         struct rockchip_pinctrl *info = bank->drvdata;
 361         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 362         void __iomem *reg;
 363         u8 bit;
 364
 365         /* rk3066b does support any pulls */
 366         if (!ctrl->pull_offset)
 367                 return PIN_CONFIG_BIAS_DISABLE;
 368
 369         reg = info->reg_base + ctrl->pull_offset;
 370
 371         if (ctrl->pull_auto) {
 372                 reg += bank->bank_num * ctrl->pull_bank_stride;
 373                 reg += (pin_num / 16) * 4;
 374                 bit = pin_num % 16;
 375
 376                 return !(readl_relaxed(reg) & BIT(bit))
 377                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 378                                 : PIN_CONFIG_BIAS_DISABLE;
 379         } else {
 380                 dev_err(info->dev, "pull support for rk31xx not implemented\n");
 381                 return -EIO;
 382         }
 383 }
 384
 385 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 386                                         int pin_num, int pull)
 387 {
 388         struct rockchip_pinctrl *info = bank->drvdata;
 389         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 390         void __iomem *reg;
 391         unsigned long flags;
 392         u8 bit;
 393         u32 data;
 394
 395         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 396                  bank->bank_num, pin_num, pull);
 397
 398         /* rk3066b does support any pulls */
 399         if (!ctrl->pull_offset)
 400                 return pull ? -EINVAL : 0;
 401
 402         reg = info->reg_base + ctrl->pull_offset;
 403
 404         if (ctrl->pull_auto) {
 405                 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
 406                                         pull != PIN_CONFIG_BIAS_DISABLE) {
 407                         dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
 408                         return -EINVAL;
 409                 }
 410
 411                 reg += bank->bank_num * ctrl->pull_bank_stride;
 412                 reg += (pin_num / 16) * 4;
 413                 bit = pin_num % 16;
 414
 415                 spin_lock_irqsave(&bank->slock, flags);
 416
 417                 data = BIT(bit + 16);
 418                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 419                         data |= BIT(bit);
 420                 writel(data, reg);
 421
 422                 spin_unlock_irqrestore(&bank->slock, flags);
 423         } else {
 424                 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) {
 425                         dev_err(info->dev, "pull direction (up/down) needs to be specified\n");
 426                         return -EINVAL;
 427                 }
 428
 429                 dev_err(info->dev, "pull support for rk31xx not implemented\n");
 430                 return -EIO;
 431         }
 432
 433         return 0;
 434 }
 435
 436 /*
 437  * Pinmux_ops handling
 438  */
 439
 440 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 441 {
 442         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 443
 444         return info->nfunctions;
 445 }
 446
 447 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 448                                           unsigned selector)
 449 {
 450         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 451
 452         return info->functions[selector].name;
 453 }
 454
 455 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 456                                 unsigned selector, const char * const **groups,
 457                                 unsigned * const num_groups)
 458 {
 459         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 460
 461         *groups = info->functions[selector].groups;
 462         *num_groups = info->functions[selector].ngroups;
 463
 464         return 0;
 465 }
 466
 467 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 468                                                             unsigned group)
 469 {
 470         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 471         const unsigned int *pins = info->groups[group].pins;
 472         const struct rockchip_pin_config *data = info->groups[group].data;
 473         struct rockchip_pin_bank *bank;
 474         int cnt;
 475
 476         dev_dbg(info->dev, "enable function %s group %s\n",
 477                 info->functions[selector].name, info->groups[group].name);
 478
 479         /*
 480          * for each pin in the pin group selected, program the correspoding pin
 481          * pin function number in the config register.
 482          */
 483         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 484                 bank = pin_to_bank(info, pins[cnt]);
 485                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 486                                  data[cnt].func);
 487         }
 488
 489         return 0;
 490 }
 491
 492 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 493                                         unsigned selector, unsigned group)
 494 {
 495         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 496         const unsigned int *pins = info->groups[group].pins;
 497         struct rockchip_pin_bank *bank;
 498         int cnt;
 499
 500         dev_dbg(info->dev, "disable function %s group %s\n",
 501                 info->functions[selector].name, info->groups[group].name);
 502
 503         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 504                 bank = pin_to_bank(info, pins[cnt]);
 505                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 506         }
 507 }
 508
 509 /*
 510  * The calls to gpio_direction_output() and gpio_direction_input()
 511  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 512  * function called from the gpiolib interface).
 513  */
 514 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 515                                               struct pinctrl_gpio_range *range,
 516                                               unsigned offset, bool input)
 517 {
 518         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 519         struct rockchip_pin_bank *bank;
 520         struct gpio_chip *chip;
 521         int pin;
 522         u32 data;
 523
 524         chip = range->gc;
 525         bank = gc_to_pin_bank(chip);
 526         pin = offset - chip->base;
 527
 528         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 529                  offset, range->name, pin, input ? "input" : "output");
 530
 531         rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 532
 533         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 534         /* set bit to 1 for output, 0 for input */
 535         if (!input)
 536                 data |= BIT(pin);
 537         else
 538                 data &= ~BIT(pin);
 539         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 540
 541         return 0;
 542 }
 543
 544 static const struct pinmux_ops rockchip_pmx_ops = {
 545         .get_functions_count    = rockchip_pmx_get_funcs_count,
 546         .get_function_name      = rockchip_pmx_get_func_name,
 547         .get_function_groups    = rockchip_pmx_get_groups,
 548         .enable                 = rockchip_pmx_enable,
 549         .disable                = rockchip_pmx_disable,
 550         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 551 };
 552
 553 /*
 554  * Pinconf_ops handling
 555  */
 556
 557 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 558                                         enum pin_config_param pull)
 559 {
 560         /* rk3066b does support any pulls */
 561         if (!ctrl->pull_offset)
 562                 return pull ? false : true;
 563
 564         if (ctrl->pull_auto) {
 565                 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
 566                                         pull != PIN_CONFIG_BIAS_DISABLE)
 567                         return false;
 568         } else {
 569                 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
 570                         return false;
 571         }
 572
 573         return true;
 574 }
 575
 576 /* set the pin config settings for a specified pin */
 577 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 578                                                         unsigned long config)
 579 {
 580         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 581         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 582         enum pin_config_param param = pinconf_to_config_param(config);
 583         u16 arg = pinconf_to_config_argument(config);
 584
 585         switch (param) {
 586         case PIN_CONFIG_BIAS_DISABLE:
 587                 return rockchip_set_pull(bank, pin - bank->pin_base, param);
 588                 break;
 589         case PIN_CONFIG_BIAS_PULL_UP:
 590         case PIN_CONFIG_BIAS_PULL_DOWN:
 591         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 592                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 593                         return -ENOTSUPP;
 594
 595                 if (!arg)
 596                         return -EINVAL;
 597
 598                 return rockchip_set_pull(bank, pin - bank->pin_base, param);
 599                 break;
 600         default:
 601                 return -ENOTSUPP;
 602                 break;
 603         }
 604
 605         return 0;
 606 }
 607
 608 /* get the pin config settings for a specified pin */
 609 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 610                                                         unsigned long *config)
 611 {
 612         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 613         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 614         enum pin_config_param param = pinconf_to_config_param(*config);
 615
 616         switch (param) {
 617         case PIN_CONFIG_BIAS_DISABLE:
 618                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 619                         return -EINVAL;
 620
 621                 *config = 0;
 622                 break;
 623         case PIN_CONFIG_BIAS_PULL_UP:
 624         case PIN_CONFIG_BIAS_PULL_DOWN:
 625         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 626                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 627                         return -ENOTSUPP;
 628
 629                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 630                         return -EINVAL;
 631
 632                 *config = 1;
 633                 break;
 634         default:
 635                 return -ENOTSUPP;
 636                 break;
 637         }
 638
 639         return 0;
 640 }
 641
 642 static const struct pinconf_ops rockchip_pinconf_ops = {
 643         .pin_config_get                 = rockchip_pinconf_get,
 644         .pin_config_set                 = rockchip_pinconf_set,
 645 };
 646
 647 static const char *gpio_compat = "rockchip,gpio-bank";
 648
 649 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
 650                                                 struct device_node *np)
 651 {
 652         struct device_node *child;
 653
 654         for_each_child_of_node(np, child) {
 655                 if (of_device_is_compatible(child, gpio_compat))
 656                         continue;
 657
 658                 info->nfunctions++;
 659                 info->ngroups += of_get_child_count(child);
 660         }
 661 }
 662
 663 static int rockchip_pinctrl_parse_groups(struct device_node *np,
 664                                               struct rockchip_pin_group *grp,
 665                                               struct rockchip_pinctrl *info,
 666                                               u32 index)
 667 {
 668         struct rockchip_pin_bank *bank;
 669         int size;
 670         const __be32 *list;
 671         int num;
 672         int i, j;
 673         int ret;
 674
 675         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 676
 677         /* Initialise group */
 678         grp->name = np->name;
 679
 680         /*
 681          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
 682          * do sanity check and calculate pins number
 683          */
 684         list = of_get_property(np, "rockchip,pins", &size);
 685         /* we do not check return since it's safe node passed down */
 686         size /= sizeof(*list);
 687         if (!size || size % 4) {
 688                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
 689                 return -EINVAL;
 690         }
 691
 692         grp->npins = size / 4;
 693
 694         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 695                                                 GFP_KERNEL);
 696         grp->data = devm_kzalloc(info->dev, grp->npins *
 697                                           sizeof(struct rockchip_pin_config),
 698                                         GFP_KERNEL);
 699         if (!grp->pins || !grp->data)
 700                 return -ENOMEM;
 701
 702         for (i = 0, j = 0; i < size; i += 4, j++) {
 703                 const __be32 *phandle;
 704                 struct device_node *np_config;
 705
 706                 num = be32_to_cpu(*list++);
 707                 bank = bank_num_to_bank(info, num);
 708                 if (IS_ERR(bank))
 709                         return PTR_ERR(bank);
 710
 711                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
 712                 grp->data[j].func = be32_to_cpu(*list++);
 713
 714                 phandle = list++;
 715                 if (!phandle)
 716                         return -EINVAL;
 717
 718                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
 719                 ret = pinconf_generic_parse_dt_config(np_config,
 720                                 &grp->data[j].configs, &grp->data[j].nconfigs);
 721                 if (ret)
 722                         return ret;
 723         }
 724
 725         return 0;
 726 }
 727
 728 static int rockchip_pinctrl_parse_functions(struct device_node *np,
 729                                                 struct rockchip_pinctrl *info,
 730                                                 u32 index)
 731 {
 732         struct device_node *child;
 733         struct rockchip_pmx_func *func;
 734         struct rockchip_pin_group *grp;
 735         int ret;
 736         static u32 grp_index;
 737         u32 i = 0;
 738
 739         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 740
 741         func = &info->functions[index];
 742
 743         /* Initialise function */
 744         func->name = np->name;
 745         func->ngroups = of_get_child_count(np);
 746         if (func->ngroups <= 0)
 747                 return 0;
 748
 749         func->groups = devm_kzalloc(info->dev,
 750                         func->ngroups * sizeof(char *), GFP_KERNEL);
 751         if (!func->groups)
 752                 return -ENOMEM;
 753
 754         for_each_child_of_node(np, child) {
 755                 func->groups[i] = child->name;
 756                 grp = &info->groups[grp_index++];
 757                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
 758                 if (ret)
 759                         return ret;
 760         }
 761
 762         return 0;
 763 }
 764
 765 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
 766                                               struct rockchip_pinctrl *info)
 767 {
 768         struct device *dev = &pdev->dev;
 769         struct device_node *np = dev->of_node;
 770         struct device_node *child;
 771         int ret;
 772         int i;
 773
 774         rockchip_pinctrl_child_count(info, np);
 775
 776         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
 777         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
 778
 779         info->functions = devm_kzalloc(dev, info->nfunctions *
 780                                               sizeof(struct rockchip_pmx_func),
 781                                               GFP_KERNEL);
 782         if (!info->functions) {
 783                 dev_err(dev, "failed to allocate memory for function list\n");
 784                 return -EINVAL;
 785         }
 786
 787         info->groups = devm_kzalloc(dev, info->ngroups *
 788                                             sizeof(struct rockchip_pin_group),
 789                                             GFP_KERNEL);
 790         if (!info->groups) {
 791                 dev_err(dev, "failed allocate memory for ping group list\n");
 792                 return -EINVAL;
 793         }
 794
 795         i = 0;
 796
 797         for_each_child_of_node(np, child) {
 798                 if (of_device_is_compatible(child, gpio_compat))
 799                         continue;
 800                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
 801                 if (ret) {
 802                         dev_err(&pdev->dev, "failed to parse function\n");
 803                         return ret;
 804                 }
 805         }
 806
 807         return 0;
 808 }
 809
 810 static int rockchip_pinctrl_register(struct platform_device *pdev,
 811                                         struct rockchip_pinctrl *info)
 812 {
 813         struct pinctrl_desc *ctrldesc = &info->pctl;
 814         struct pinctrl_pin_desc *pindesc, *pdesc;
 815         struct rockchip_pin_bank *pin_bank;
 816         int pin, bank, ret;
 817         int k;
 818
 819         ctrldesc->name = "rockchip-pinctrl";
 820         ctrldesc->owner = THIS_MODULE;
 821         ctrldesc->pctlops = &rockchip_pctrl_ops;
 822         ctrldesc->pmxops = &rockchip_pmx_ops;
 823         ctrldesc->confops = &rockchip_pinconf_ops;
 824
 825         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
 826                         info->ctrl->nr_pins, GFP_KERNEL);
 827         if (!pindesc) {
 828                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
 829                 return -ENOMEM;
 830         }
 831         ctrldesc->pins = pindesc;
 832         ctrldesc->npins = info->ctrl->nr_pins;
 833
 834         pdesc = pindesc;
 835         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
 836                 pin_bank = &info->ctrl->pin_banks[bank];
 837                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
 838                         pdesc->number = k;
 839                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
 840                                                 pin_bank->name, pin);
 841                         pdesc++;
 842                 }
 843         }
 844
 845         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
 846         if (!info->pctl_dev) {
 847                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
 848                 return -EINVAL;
 849         }
 850
 851         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
 852                 pin_bank = &info->ctrl->pin_banks[bank];
 853                 pin_bank->grange.name = pin_bank->name;
 854                 pin_bank->grange.id = bank;
 855                 pin_bank->grange.pin_base = pin_bank->pin_base;
 856                 pin_bank->grange.base = pin_bank->gpio_chip.base;
 857                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
 858                 pin_bank->grange.gc = &pin_bank->gpio_chip;
 859                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
 860         }
 861
 862         ret = rockchip_pinctrl_parse_dt(pdev, info);
 863         if (ret) {
 864                 pinctrl_unregister(info->pctl_dev);
 865                 return ret;
 866         }
 867
 868         return 0;
 869 }
 870
 871 /*
 872  * GPIO handling
 873  */
 874
 875 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 876 {
 877         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 878         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
 879         unsigned long flags;
 880         u32 data;
 881
 882         spin_lock_irqsave(&bank->slock, flags);
 883
 884         data = readl(reg);
 885         data &= ~BIT(offset);
 886         if (value)
 887                 data |= BIT(offset);
 888         writel(data, reg);
 889
 890         spin_unlock_irqrestore(&bank->slock, flags);
 891 }
 892
 893 /*
 894  * Returns the level of the pin for input direction and setting of the DR
 895  * register for output gpios.
 896  */
 897 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
 898 {
 899         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 900         u32 data;
 901
 902         data = readl(bank->reg_base + GPIO_EXT_PORT);
 903         data >>= offset;
 904         data &= 1;
 905         return data;
 906 }
 907
 908 /*
 909  * gpiolib gpio_direction_input callback function. The setting of the pin
 910  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
 911  * interface.
 912  */
 913 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
 914 {
 915         return pinctrl_gpio_direction_input(gc->base + offset);
 916 }
 917
 918 /*
 919  * gpiolib gpio_direction_output callback function. The setting of the pin
 920  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
 921  * interface.
 922  */
 923 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
 924                                           unsigned offset, int value)
 925 {
 926         rockchip_gpio_set(gc, offset, value);
 927         return pinctrl_gpio_direction_output(gc->base + offset);
 928 }
 929
 930 /*
 931  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
 932  * and a virtual IRQ, if not already present.
 933  */
 934 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 935 {
 936         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 937         unsigned int virq;
 938
 939         if (!bank->domain)
 940                 return -ENXIO;
 941
 942         virq = irq_create_mapping(bank->domain, offset);
 943
 944         return (virq) ? : -ENXIO;
 945 }
 946
 947 static const struct gpio_chip rockchip_gpiolib_chip = {
 948         .set = rockchip_gpio_set,
 949         .get = rockchip_gpio_get,
 950         .direction_input = rockchip_gpio_direction_input,
 951         .direction_output = rockchip_gpio_direction_output,
 952         .to_irq = rockchip_gpio_to_irq,
 953         .owner = THIS_MODULE,
 954 };
 955
 956 /*
 957  * Interrupt handling
 958  */
 959
 960 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
 961 {
 962         struct irq_chip *chip = irq_get_chip(irq);
 963         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
 964         u32 pend;
 965
 966         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
 967
 968         chained_irq_enter(chip, desc);
 969
 970         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
 971
 972         while (pend) {
 973                 unsigned int virq;
 974
 975                 irq = __ffs(pend);
 976                 pend &= ~BIT(irq);
 977                 virq = irq_linear_revmap(bank->domain, irq);
 978
 979                 if (!virq) {
 980                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
 981                         continue;
 982                 }
 983
 984                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
 985
 986                 generic_handle_irq(virq);
 987         }
 988
 989         chained_irq_exit(chip, desc);
 990 }
 991
 992 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
 993 {
 994         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 995         struct rockchip_pin_bank *bank = gc->private;
 996         u32 mask = BIT(d->hwirq);
 997         u32 polarity;
 998         u32 level;
 999         u32 data;
1000
1001         if (type & IRQ_TYPE_EDGE_BOTH)
1002                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1003         else
1004                 __irq_set_handler_locked(d->irq, handle_level_irq);
1005
1006         irq_gc_lock(gc);
1007
1008         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1009         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1010
1011         switch (type) {
1012         case IRQ_TYPE_EDGE_RISING:
1013                 level |= mask;
1014                 polarity |= mask;
1015                 break;
1016         case IRQ_TYPE_EDGE_FALLING:
1017                 level |= mask;
1018                 polarity &= ~mask;
1019                 break;
1020         case IRQ_TYPE_LEVEL_HIGH:
1021                 level &= ~mask;
1022                 polarity |= mask;
1023                 break;
1024         case IRQ_TYPE_LEVEL_LOW:
1025                 level &= ~mask;
1026                 polarity &= ~mask;
1027                 break;
1028         default:
1029                 irq_gc_unlock(gc);
1030                 return -EINVAL;
1031         }
1032
1033         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1034         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1035
1036         irq_gc_unlock(gc);
1037
1038         /* make sure the pin is configured as gpio input */
1039         rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1040         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1041         data &= ~mask;
1042         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1043
1044         return 0;
1045 }
1046
1047 static int rockchip_interrupts_register(struct platform_device *pdev,
1048                                                 struct rockchip_pinctrl *info)
1049 {
1050         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1051         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1052         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1053         struct irq_chip_generic *gc;
1054         int ret;
1055         int i;
1056
1057         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1058                 if (!bank->valid) {
1059                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1060                                  bank->name);
1061                         continue;
1062                 }
1063
1064                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1065                                                 &irq_generic_chip_ops, NULL);
1066                 if (!bank->domain) {
1067                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1068                                  bank->name);
1069                         continue;
1070                 }
1071
1072                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1073                                          "rockchip_gpio_irq", handle_level_irq,
1074                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1075                 if (ret) {
1076                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1077                                 bank->name);
1078                         irq_domain_remove(bank->domain);
1079                         continue;
1080                 }
1081
1082                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1083                 gc->reg_base = bank->reg_base;
1084                 gc->private = bank;
1085                 gc->chip_types[0].regs.mask = GPIO_INTEN;
1086                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1087                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1088                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1089                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1090                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1091                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1092
1093                 irq_set_handler_data(bank->irq, bank);
1094                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1095         }
1096
1097         return 0;
1098 }
1099
1100 static int rockchip_gpiolib_register(struct platform_device *pdev,
1101                                                 struct rockchip_pinctrl *info)
1102 {
1103         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1104         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1105         struct gpio_chip *gc;
1106         int ret;
1107         int i;
1108
1109         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1110                 if (!bank->valid) {
1111                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1112                                  bank->name);
1113                         continue;
1114                 }
1115
1116                 bank->gpio_chip = rockchip_gpiolib_chip;
1117
1118                 gc = &bank->gpio_chip;
1119                 gc->base = bank->pin_base;
1120                 gc->ngpio = bank->nr_pins;
1121                 gc->dev = &pdev->dev;
1122                 gc->of_node = bank->of_node;
1123                 gc->label = bank->name;
1124
1125                 ret = gpiochip_add(gc);
1126                 if (ret) {
1127                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1128                                                         gc->label, ret);
1129                         goto fail;
1130                 }
1131         }
1132
1133         rockchip_interrupts_register(pdev, info);
1134
1135         return 0;
1136
1137 fail:
1138         for (--i, --bank; i >= 0; --i, --bank) {
1139                 if (!bank->valid)
1140                         continue;
1141
1142                 if (gpiochip_remove(&bank->gpio_chip))
1143                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1144                                                         bank->gpio_chip.label);
1145         }
1146         return ret;
1147 }
1148
1149 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1150                                                 struct rockchip_pinctrl *info)
1151 {
1152         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1153         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1154         int ret = 0;
1155         int i;
1156
1157         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1158                 if (!bank->valid)
1159                         continue;
1160
1161                 ret = gpiochip_remove(&bank->gpio_chip);
1162         }
1163
1164         if (ret)
1165                 dev_err(&pdev->dev, "gpio chip remove failed\n");
1166
1167         return ret;
1168 }
1169
1170 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1171                                   struct device *dev)
1172 {
1173         struct resource res;
1174
1175         if (of_address_to_resource(bank->of_node, 0, &res)) {
1176                 dev_err(dev, "cannot find IO resource for bank\n");
1177                 return -ENOENT;
1178         }
1179
1180         bank->reg_base = devm_ioremap_resource(dev, &res);
1181         if (IS_ERR(bank->reg_base))
1182                 return PTR_ERR(bank->reg_base);
1183
1184         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1185
1186         bank->clk = of_clk_get(bank->of_node, 0);
1187         if (IS_ERR(bank->clk))
1188                 return PTR_ERR(bank->clk);
1189
1190         return clk_prepare_enable(bank->clk);
1191 }
1192
1193 static const struct of_device_id rockchip_pinctrl_dt_match[];
1194
1195 /* retrieve the soc specific data */
1196 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1197                                                 struct rockchip_pinctrl *d,
1198                                                 struct platform_device *pdev)
1199 {
1200         const struct of_device_id *match;
1201         struct device_node *node = pdev->dev.of_node;
1202         struct device_node *np;
1203         struct rockchip_pin_ctrl *ctrl;
1204         struct rockchip_pin_bank *bank;
1205         int i;
1206
1207         match = of_match_node(rockchip_pinctrl_dt_match, node);
1208         ctrl = (struct rockchip_pin_ctrl *)match->data;
1209
1210         for_each_child_of_node(node, np) {
1211                 if (!of_find_property(np, "gpio-controller", NULL))
1212                         continue;
1213
1214                 bank = ctrl->pin_banks;
1215                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1216                         if (!strcmp(bank->name, np->name)) {
1217                                 bank->of_node = np;
1218
1219                                 if (!rockchip_get_bank_data(bank, &pdev->dev))
1220                                         bank->valid = true;
1221
1222                                 break;
1223                         }
1224                 }
1225         }
1226
1227         bank = ctrl->pin_banks;
1228         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1229                 spin_lock_init(&bank->slock);
1230                 bank->drvdata = d;
1231                 bank->pin_base = ctrl->nr_pins;
1232                 ctrl->nr_pins += bank->nr_pins;
1233         }
1234
1235         return ctrl;
1236 }
1237
1238 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1239 {
1240         struct rockchip_pinctrl *info;
1241         struct device *dev = &pdev->dev;
1242         struct rockchip_pin_ctrl *ctrl;
1243         struct resource *res;
1244         int ret;
1245
1246         if (!dev->of_node) {
1247                 dev_err(dev, "device tree node not found\n");
1248                 return -ENODEV;
1249         }
1250
1251         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1252         if (!info)
1253                 return -ENOMEM;
1254
1255         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1256         if (!ctrl) {
1257                 dev_err(dev, "driver data not available\n");
1258                 return -EINVAL;
1259         }
1260         info->ctrl = ctrl;
1261         info->dev = dev;
1262
1263         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1264         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1265         if (IS_ERR(info->reg_base))
1266                 return PTR_ERR(info->reg_base);
1267
1268         ret = rockchip_gpiolib_register(pdev, info);
1269         if (ret)
1270                 return ret;
1271
1272         ret = rockchip_pinctrl_register(pdev, info);
1273         if (ret) {
1274                 rockchip_gpiolib_unregister(pdev, info);
1275                 return ret;
1276         }
1277
1278         platform_set_drvdata(pdev, info);
1279
1280         return 0;
1281 }
1282
1283 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1284         PIN_BANK(0, 32, "gpio0"),
1285         PIN_BANK(1, 32, "gpio1"),
1286         PIN_BANK(2, 32, "gpio2"),
1287         PIN_BANK(3, 32, "gpio3"),
1288 };
1289
1290 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1291                 .pin_banks              = rk2928_pin_banks,
1292                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1293                 .label                  = "RK2928-GPIO",
1294                 .mux_offset             = 0xa8,
1295                 .pull_offset            = 0x118,
1296                 .pull_auto              = 1,
1297                 .pull_bank_stride       = 8,
1298 };
1299
1300 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1301         PIN_BANK(0, 32, "gpio0"),
1302         PIN_BANK(1, 32, "gpio1"),
1303         PIN_BANK(2, 32, "gpio2"),
1304         PIN_BANK(3, 32, "gpio3"),
1305         PIN_BANK(4, 32, "gpio4"),
1306         PIN_BANK(6, 16, "gpio6"),
1307 };
1308
1309 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1310                 .pin_banks              = rk3066a_pin_banks,
1311                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1312                 .label                  = "RK3066a-GPIO",
1313                 .mux_offset             = 0xa8,
1314                 .pull_offset            = 0x118,
1315                 .pull_auto              = 1,
1316                 .pull_bank_stride       = 8,
1317 };
1318
1319 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1320         PIN_BANK(0, 32, "gpio0"),
1321         PIN_BANK(1, 32, "gpio1"),
1322         PIN_BANK(2, 32, "gpio2"),
1323         PIN_BANK(3, 32, "gpio3"),
1324 };
1325
1326 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1327                 .pin_banks      = rk3066b_pin_banks,
1328                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
1329                 .label          = "RK3066b-GPIO",
1330                 .mux_offset     = 0x60,
1331                 .pull_offset    = -EINVAL,
1332 };
1333
1334 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1335         PIN_BANK(0, 32, "gpio0"),
1336         PIN_BANK(1, 32, "gpio1"),
1337         PIN_BANK(2, 32, "gpio2"),
1338         PIN_BANK(3, 32, "gpio3"),
1339 };
1340
1341 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1342                 .pin_banks              = rk3188_pin_banks,
1343                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
1344                 .label                  = "RK3188-GPIO",
1345                 .mux_offset             = 0x68,
1346                 .pull_offset            = 0x164,
1347                 .pull_bank_stride       = 16,
1348 };
1349
1350 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1351         { .compatible = "rockchip,rk2928-pinctrl",
1352                 .data = (void *)&rk2928_pin_ctrl },
1353         { .compatible = "rockchip,rk3066a-pinctrl",
1354                 .data = (void *)&rk3066a_pin_ctrl },
1355         { .compatible = "rockchip,rk3066b-pinctrl",
1356                 .data = (void *)&rk3066b_pin_ctrl },
1357         { .compatible = "rockchip,rk3188-pinctrl",
1358                 .data = (void *)&rk3188_pin_ctrl },
1359         {},
1360 };
1361 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1362
1363 static struct platform_driver rockchip_pinctrl_driver = {
1364         .probe          = rockchip_pinctrl_probe,
1365         .driver = {
1366                 .name   = "rockchip-pinctrl",
1367                 .owner  = THIS_MODULE,
1368                 .of_match_table = rockchip_pinctrl_dt_match,
1369         },
1370 };
1371
1372 static int __init rockchip_pinctrl_drv_register(void)
1373 {
1374         return platform_driver_register(&rockchip_pinctrl_driver);
1375 }
1376 postcore_initcall(rockchip_pinctrl_drv_register);
1377
1378 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1379 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1380 MODULE_LICENSE("GPL v2");