2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk-provider.h>
40 #include <dt-bindings/pinctrl/rockchip.h>
45 /* GPIO control registers */
46 #define GPIO_SWPORT_DR 0x00
47 #define GPIO_SWPORT_DDR 0x04
48 #define GPIO_INTEN 0x30
49 #define GPIO_INTMASK 0x34
50 #define GPIO_INTTYPE_LEVEL 0x38
51 #define GPIO_INT_POLARITY 0x3c
52 #define GPIO_INT_STATUS 0x40
53 #define GPIO_INT_RAWSTATUS 0x44
54 #define GPIO_DEBOUNCE 0x48
55 #define GPIO_PORTS_EOI 0x4c
56 #define GPIO_EXT_PORT 0x50
57 #define GPIO_LS_SYNC 0x60
60 * @reg_base: register base of the gpio bank
61 * @clk: clock of the gpio bank
62 * @irq: interrupt of the gpio bank
63 * @pin_base: first pin number
64 * @nr_pins: number of pins in this bank
65 * @name: name of the bank
66 * @bank_num: number of the bank, to account for holes
67 * @valid: are all necessary informations present
68 * @of_node: dt node of this bank
69 * @drvdata: common pinctrl basedata
70 * @domain: irqdomain of the gpio bank
71 * @gpio_chip: gpiolib chip
73 * @slock: spinlock for the gpio bank
75 struct rockchip_pin_bank {
76 void __iomem *reg_base;
84 struct device_node *of_node;
85 struct rockchip_pinctrl *drvdata;
86 struct irq_domain *domain;
87 struct gpio_chip gpio_chip;
88 struct pinctrl_gpio_range grange;
93 #define PIN_BANK(id, pins, label) \
101 * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but
102 * instead decide this automatically based on the pad-type.
104 struct rockchip_pin_ctrl {
105 struct rockchip_pin_bank *pin_banks;
112 int pull_bank_stride;
115 struct rockchip_pin_config {
117 unsigned long *configs;
118 unsigned int nconfigs;
122 * struct rockchip_pin_group: represent group of pins of a pinmux function.
123 * @name: name of the pin group, used to lookup the group.
124 * @pins: the pins included in this group.
125 * @npins: number of pins included in this group.
126 * @func: the mux function number to be programmed when selected.
127 * @configs: the config values to be set for each pin
128 * @nconfigs: number of configs for each pin
130 struct rockchip_pin_group {
134 struct rockchip_pin_config *data;
138 * struct rockchip_pmx_func: represent a pin function.
139 * @name: name of the pin function, used to lookup the function.
140 * @groups: one or more names of pin groups that provide this function.
141 * @num_groups: number of groups included in @groups.
143 struct rockchip_pmx_func {
149 struct rockchip_pinctrl {
150 void __iomem *reg_base;
152 struct rockchip_pin_ctrl *ctrl;
153 struct pinctrl_desc pctl;
154 struct pinctrl_dev *pctl_dev;
155 struct rockchip_pin_group *groups;
156 unsigned int ngroups;
157 struct rockchip_pmx_func *functions;
158 unsigned int nfunctions;
161 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
163 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
166 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
167 const struct rockchip_pinctrl *info,
170 const struct rockchip_pin_group *grp = NULL;
173 for (i = 0; i < info->ngroups; i++) {
174 if (strcmp(info->groups[i].name, name))
177 grp = &info->groups[i];
185 * given a pin number that is local to a pin controller, find out the pin bank
186 * and the register base of the pin bank.
188 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
191 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
193 while ((pin >= b->pin_base) &&
194 ((b->pin_base + b->nr_pins - 1) < pin))
200 static struct rockchip_pin_bank *bank_num_to_bank(
201 struct rockchip_pinctrl *info,
204 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
207 for (i = 0; i < info->ctrl->nr_banks; i++) {
208 if (b->bank_num == num)
214 if (b->bank_num != num)
215 return ERR_PTR(-EINVAL);
221 * Pinctrl_ops handling
224 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
226 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
228 return info->ngroups;
231 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
234 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
236 return info->groups[selector].name;
239 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
240 unsigned selector, const unsigned **pins,
243 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
245 if (selector >= info->ngroups)
248 *pins = info->groups[selector].pins;
249 *npins = info->groups[selector].npins;
254 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
255 struct device_node *np,
256 struct pinctrl_map **map, unsigned *num_maps)
258 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
259 const struct rockchip_pin_group *grp;
260 struct pinctrl_map *new_map;
261 struct device_node *parent;
266 * first find the group of this node and check if we need to create
267 * config maps for pins
269 grp = pinctrl_name_to_group(info, np->name);
271 dev_err(info->dev, "unable to find group for node %s\n",
276 map_num += grp->npins;
277 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
286 parent = of_get_parent(np);
288 devm_kfree(pctldev->dev, new_map);
291 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
292 new_map[0].data.mux.function = parent->name;
293 new_map[0].data.mux.group = np->name;
296 /* create config map */
298 for (i = 0; i < grp->npins; i++) {
299 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
300 new_map[i].data.configs.group_or_pin =
301 pin_get_name(pctldev, grp->pins[i]);
302 new_map[i].data.configs.configs = grp->data[i].configs;
303 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
306 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
307 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
312 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
313 struct pinctrl_map *map, unsigned num_maps)
317 static const struct pinctrl_ops rockchip_pctrl_ops = {
318 .get_groups_count = rockchip_get_groups_count,
319 .get_group_name = rockchip_get_group_name,
320 .get_group_pins = rockchip_get_group_pins,
321 .dt_node_to_map = rockchip_dt_node_to_map,
322 .dt_free_map = rockchip_dt_free_map,
330 * Set a new mux function for a pin.
332 * The register is divided into the upper and lower 16 bit. When changing
333 * a value, the previous register value is not read and changed. Instead
334 * it seems the changed bits are marked in the upper 16 bit, while the
335 * changed value gets set in the same offset in the lower 16 bit.
336 * All pin settings seem to be 2 bit wide in both the upper and lower
338 * @bank: pin bank to change
339 * @pin: pin to change
340 * @mux: new mux function to set
342 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
344 struct rockchip_pinctrl *info = bank->drvdata;
345 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
350 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
351 bank->bank_num, pin, mux);
353 /* get basic quadrupel of mux registers and the correct reg inside */
354 reg += bank->bank_num * 0x10;
355 reg += (pin / 8) * 4;
358 spin_lock_irqsave(&bank->slock, flags);
360 data = (3 << (bit + 16));
361 data |= (mux & 3) << bit;
364 spin_unlock_irqrestore(&bank->slock, flags);
367 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
369 struct rockchip_pinctrl *info = bank->drvdata;
370 struct rockchip_pin_ctrl *ctrl = info->ctrl;
374 /* rk3066b does support any pulls */
375 if (!ctrl->pull_offset)
376 return PIN_CONFIG_BIAS_DISABLE;
378 reg = info->reg_base + ctrl->pull_offset;
380 if (ctrl->pull_auto) {
381 reg += bank->bank_num * ctrl->pull_bank_stride;
382 reg += (pin_num / 16) * 4;
385 return !(readl_relaxed(reg) & BIT(bit))
386 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
387 : PIN_CONFIG_BIAS_DISABLE;
389 dev_err(info->dev, "pull support for rk31xx not implemented\n");
394 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
395 int pin_num, int pull)
397 struct rockchip_pinctrl *info = bank->drvdata;
398 struct rockchip_pin_ctrl *ctrl = info->ctrl;
404 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
405 bank->bank_num, pin_num, pull);
407 /* rk3066b does support any pulls */
408 if (!ctrl->pull_offset)
409 return pull ? -EINVAL : 0;
411 reg = info->reg_base + ctrl->pull_offset;
413 if (ctrl->pull_auto) {
414 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
415 pull != PIN_CONFIG_BIAS_DISABLE) {
416 dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
420 reg += bank->bank_num * ctrl->pull_bank_stride;
421 reg += (pin_num / 16) * 4;
424 spin_lock_irqsave(&bank->slock, flags);
426 data = BIT(bit + 16);
427 if (pull == PIN_CONFIG_BIAS_DISABLE)
431 spin_unlock_irqrestore(&bank->slock, flags);
433 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) {
434 dev_err(info->dev, "pull direction (up/down) needs to be specified\n");
438 dev_err(info->dev, "pull support for rk31xx not implemented\n");
446 * Pinmux_ops handling
449 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
451 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
453 return info->nfunctions;
456 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
459 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
461 return info->functions[selector].name;
464 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
465 unsigned selector, const char * const **groups,
466 unsigned * const num_groups)
468 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
470 *groups = info->functions[selector].groups;
471 *num_groups = info->functions[selector].ngroups;
476 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
479 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
480 const unsigned int *pins = info->groups[group].pins;
481 const struct rockchip_pin_config *data = info->groups[group].data;
482 struct rockchip_pin_bank *bank;
485 dev_dbg(info->dev, "enable function %s group %s\n",
486 info->functions[selector].name, info->groups[group].name);
489 * for each pin in the pin group selected, program the correspoding pin
490 * pin function number in the config register.
492 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
493 bank = pin_to_bank(info, pins[cnt]);
494 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
501 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
502 unsigned selector, unsigned group)
504 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
505 const unsigned int *pins = info->groups[group].pins;
506 struct rockchip_pin_bank *bank;
509 dev_dbg(info->dev, "disable function %s group %s\n",
510 info->functions[selector].name, info->groups[group].name);
512 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
513 bank = pin_to_bank(info, pins[cnt]);
514 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
519 * The calls to gpio_direction_output() and gpio_direction_input()
520 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
521 * function called from the gpiolib interface).
523 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
524 struct pinctrl_gpio_range *range,
525 unsigned offset, bool input)
527 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
528 struct rockchip_pin_bank *bank;
529 struct gpio_chip *chip;
534 bank = gc_to_pin_bank(chip);
535 pin = offset - chip->base;
537 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
538 offset, range->name, pin, input ? "input" : "output");
540 rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
542 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
543 /* set bit to 1 for output, 0 for input */
548 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
553 static const struct pinmux_ops rockchip_pmx_ops = {
554 .get_functions_count = rockchip_pmx_get_funcs_count,
555 .get_function_name = rockchip_pmx_get_func_name,
556 .get_function_groups = rockchip_pmx_get_groups,
557 .enable = rockchip_pmx_enable,
558 .disable = rockchip_pmx_disable,
559 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
563 * Pinconf_ops handling
566 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
567 enum pin_config_param pull)
569 /* rk3066b does support any pulls */
570 if (!ctrl->pull_offset)
571 return pull ? false : true;
573 if (ctrl->pull_auto) {
574 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
575 pull != PIN_CONFIG_BIAS_DISABLE)
578 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
585 /* set the pin config settings for a specified pin */
586 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
587 unsigned long config)
589 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
590 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
591 enum pin_config_param param = pinconf_to_config_param(config);
592 u16 arg = pinconf_to_config_argument(config);
595 case PIN_CONFIG_BIAS_DISABLE:
596 return rockchip_set_pull(bank, pin - bank->pin_base, param);
598 case PIN_CONFIG_BIAS_PULL_UP:
599 case PIN_CONFIG_BIAS_PULL_DOWN:
600 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
601 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
607 return rockchip_set_pull(bank, pin - bank->pin_base, param);
617 /* get the pin config settings for a specified pin */
618 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
619 unsigned long *config)
621 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
622 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
623 enum pin_config_param param = pinconf_to_config_param(*config);
626 case PIN_CONFIG_BIAS_DISABLE:
627 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
632 case PIN_CONFIG_BIAS_PULL_UP:
633 case PIN_CONFIG_BIAS_PULL_DOWN:
634 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
635 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
638 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
651 static const struct pinconf_ops rockchip_pinconf_ops = {
652 .pin_config_get = rockchip_pinconf_get,
653 .pin_config_set = rockchip_pinconf_set,
656 static const char *gpio_compat = "rockchip,gpio-bank";
658 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
659 struct device_node *np)
661 struct device_node *child;
663 for_each_child_of_node(np, child) {
664 if (of_device_is_compatible(child, gpio_compat))
668 info->ngroups += of_get_child_count(child);
672 static int rockchip_pinctrl_parse_groups(struct device_node *np,
673 struct rockchip_pin_group *grp,
674 struct rockchip_pinctrl *info,
677 struct rockchip_pin_bank *bank;
684 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
686 /* Initialise group */
687 grp->name = np->name;
690 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
691 * do sanity check and calculate pins number
693 list = of_get_property(np, "rockchip,pins", &size);
694 /* we do not check return since it's safe node passed down */
695 size /= sizeof(*list);
696 if (!size || size % 4) {
697 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
701 grp->npins = size / 4;
703 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
705 grp->data = devm_kzalloc(info->dev, grp->npins *
706 sizeof(struct rockchip_pin_config),
708 if (!grp->pins || !grp->data)
711 for (i = 0, j = 0; i < size; i += 4, j++) {
712 const __be32 *phandle;
713 struct device_node *np_config;
715 num = be32_to_cpu(*list++);
716 bank = bank_num_to_bank(info, num);
718 return PTR_ERR(bank);
720 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
721 grp->data[j].func = be32_to_cpu(*list++);
727 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
728 ret = pinconf_generic_parse_dt_config(np_config,
729 &grp->data[j].configs, &grp->data[j].nconfigs);
737 static int rockchip_pinctrl_parse_functions(struct device_node *np,
738 struct rockchip_pinctrl *info,
741 struct device_node *child;
742 struct rockchip_pmx_func *func;
743 struct rockchip_pin_group *grp;
745 static u32 grp_index;
748 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
750 func = &info->functions[index];
752 /* Initialise function */
753 func->name = np->name;
754 func->ngroups = of_get_child_count(np);
755 if (func->ngroups <= 0)
758 func->groups = devm_kzalloc(info->dev,
759 func->ngroups * sizeof(char *), GFP_KERNEL);
763 for_each_child_of_node(np, child) {
764 func->groups[i] = child->name;
765 grp = &info->groups[grp_index++];
766 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
774 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
775 struct rockchip_pinctrl *info)
777 struct device *dev = &pdev->dev;
778 struct device_node *np = dev->of_node;
779 struct device_node *child;
783 rockchip_pinctrl_child_count(info, np);
785 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
786 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
788 info->functions = devm_kzalloc(dev, info->nfunctions *
789 sizeof(struct rockchip_pmx_func),
791 if (!info->functions) {
792 dev_err(dev, "failed to allocate memory for function list\n");
796 info->groups = devm_kzalloc(dev, info->ngroups *
797 sizeof(struct rockchip_pin_group),
800 dev_err(dev, "failed allocate memory for ping group list\n");
806 for_each_child_of_node(np, child) {
807 if (of_device_is_compatible(child, gpio_compat))
809 ret = rockchip_pinctrl_parse_functions(child, info, i++);
811 dev_err(&pdev->dev, "failed to parse function\n");
819 static int rockchip_pinctrl_register(struct platform_device *pdev,
820 struct rockchip_pinctrl *info)
822 struct pinctrl_desc *ctrldesc = &info->pctl;
823 struct pinctrl_pin_desc *pindesc, *pdesc;
824 struct rockchip_pin_bank *pin_bank;
828 ctrldesc->name = "rockchip-pinctrl";
829 ctrldesc->owner = THIS_MODULE;
830 ctrldesc->pctlops = &rockchip_pctrl_ops;
831 ctrldesc->pmxops = &rockchip_pmx_ops;
832 ctrldesc->confops = &rockchip_pinconf_ops;
834 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
835 info->ctrl->nr_pins, GFP_KERNEL);
837 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
840 ctrldesc->pins = pindesc;
841 ctrldesc->npins = info->ctrl->nr_pins;
844 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
845 pin_bank = &info->ctrl->pin_banks[bank];
846 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
848 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
849 pin_bank->name, pin);
854 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
855 if (!info->pctl_dev) {
856 dev_err(&pdev->dev, "could not register pinctrl driver\n");
860 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
861 pin_bank = &info->ctrl->pin_banks[bank];
862 pin_bank->grange.name = pin_bank->name;
863 pin_bank->grange.id = bank;
864 pin_bank->grange.pin_base = pin_bank->pin_base;
865 pin_bank->grange.base = pin_bank->gpio_chip.base;
866 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
867 pin_bank->grange.gc = &pin_bank->gpio_chip;
868 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
871 ret = rockchip_pinctrl_parse_dt(pdev, info);
873 pinctrl_unregister(info->pctl_dev);
884 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
886 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
887 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
891 spin_lock_irqsave(&bank->slock, flags);
894 data &= ~BIT(offset);
899 spin_unlock_irqrestore(&bank->slock, flags);
903 * Returns the level of the pin for input direction and setting of the DR
904 * register for output gpios.
906 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
908 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
911 data = readl(bank->reg_base + GPIO_EXT_PORT);
918 * gpiolib gpio_direction_input callback function. The setting of the pin
919 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
922 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
924 return pinctrl_gpio_direction_input(gc->base + offset);
928 * gpiolib gpio_direction_output callback function. The setting of the pin
929 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
932 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
933 unsigned offset, int value)
935 rockchip_gpio_set(gc, offset, value);
936 return pinctrl_gpio_direction_output(gc->base + offset);
940 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
941 * and a virtual IRQ, if not already present.
943 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
945 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
951 virq = irq_create_mapping(bank->domain, offset);
953 return (virq) ? : -ENXIO;
956 static const struct gpio_chip rockchip_gpiolib_chip = {
957 .set = rockchip_gpio_set,
958 .get = rockchip_gpio_get,
959 .direction_input = rockchip_gpio_direction_input,
960 .direction_output = rockchip_gpio_direction_output,
961 .to_irq = rockchip_gpio_to_irq,
962 .owner = THIS_MODULE,
969 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
971 struct irq_chip *chip = irq_get_chip(irq);
972 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
975 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
977 chained_irq_enter(chip, desc);
979 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
986 virq = irq_linear_revmap(bank->domain, irq);
989 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
993 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
995 generic_handle_irq(virq);
998 chained_irq_exit(chip, desc);
1001 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1003 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1004 struct rockchip_pin_bank *bank = gc->private;
1005 u32 mask = BIT(d->hwirq);
1010 if (type & IRQ_TYPE_EDGE_BOTH)
1011 __irq_set_handler_locked(d->irq, handle_edge_irq);
1013 __irq_set_handler_locked(d->irq, handle_level_irq);
1017 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1018 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1021 case IRQ_TYPE_EDGE_RISING:
1025 case IRQ_TYPE_EDGE_FALLING:
1029 case IRQ_TYPE_LEVEL_HIGH:
1033 case IRQ_TYPE_LEVEL_LOW:
1042 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1043 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1047 /* make sure the pin is configured as gpio input */
1048 rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1049 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1051 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1056 static int rockchip_interrupts_register(struct platform_device *pdev,
1057 struct rockchip_pinctrl *info)
1059 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1060 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1061 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1062 struct irq_chip_generic *gc;
1066 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1068 dev_warn(&pdev->dev, "bank %s is not valid\n",
1073 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1074 &irq_generic_chip_ops, NULL);
1075 if (!bank->domain) {
1076 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1081 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1082 "rockchip_gpio_irq", handle_level_irq,
1083 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1085 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1087 irq_domain_remove(bank->domain);
1091 gc = irq_get_domain_generic_chip(bank->domain, 0);
1092 gc->reg_base = bank->reg_base;
1094 gc->chip_types[0].regs.mask = GPIO_INTEN;
1095 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1096 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1097 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1098 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1099 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1100 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1102 irq_set_handler_data(bank->irq, bank);
1103 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1109 static int rockchip_gpiolib_register(struct platform_device *pdev,
1110 struct rockchip_pinctrl *info)
1112 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1113 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1114 struct gpio_chip *gc;
1118 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1120 dev_warn(&pdev->dev, "bank %s is not valid\n",
1125 bank->gpio_chip = rockchip_gpiolib_chip;
1127 gc = &bank->gpio_chip;
1128 gc->base = bank->pin_base;
1129 gc->ngpio = bank->nr_pins;
1130 gc->dev = &pdev->dev;
1131 gc->of_node = bank->of_node;
1132 gc->label = bank->name;
1134 ret = gpiochip_add(gc);
1136 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1142 rockchip_interrupts_register(pdev, info);
1147 for (--i, --bank; i >= 0; --i, --bank) {
1151 if (gpiochip_remove(&bank->gpio_chip))
1152 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1153 bank->gpio_chip.label);
1158 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1159 struct rockchip_pinctrl *info)
1161 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1162 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1166 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1170 ret = gpiochip_remove(&bank->gpio_chip);
1174 dev_err(&pdev->dev, "gpio chip remove failed\n");
1179 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1182 struct resource res;
1184 if (of_address_to_resource(bank->of_node, 0, &res)) {
1185 dev_err(dev, "cannot find IO resource for bank\n");
1189 bank->reg_base = devm_ioremap_resource(dev, &res);
1190 if (IS_ERR(bank->reg_base))
1191 return PTR_ERR(bank->reg_base);
1193 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1195 bank->clk = of_clk_get(bank->of_node, 0);
1196 if (IS_ERR(bank->clk))
1197 return PTR_ERR(bank->clk);
1199 return clk_prepare_enable(bank->clk);
1202 static const struct of_device_id rockchip_pinctrl_dt_match[];
1204 /* retrieve the soc specific data */
1205 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1206 struct rockchip_pinctrl *d,
1207 struct platform_device *pdev)
1209 const struct of_device_id *match;
1210 struct device_node *node = pdev->dev.of_node;
1211 struct device_node *np;
1212 struct rockchip_pin_ctrl *ctrl;
1213 struct rockchip_pin_bank *bank;
1216 match = of_match_node(rockchip_pinctrl_dt_match, node);
1217 ctrl = (struct rockchip_pin_ctrl *)match->data;
1219 for_each_child_of_node(node, np) {
1220 if (!of_find_property(np, "gpio-controller", NULL))
1223 bank = ctrl->pin_banks;
1224 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1225 if (!strcmp(bank->name, np->name)) {
1228 if (!rockchip_get_bank_data(bank, &pdev->dev))
1236 bank = ctrl->pin_banks;
1237 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1238 spin_lock_init(&bank->slock);
1240 bank->pin_base = ctrl->nr_pins;
1241 ctrl->nr_pins += bank->nr_pins;
1247 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1249 struct rockchip_pinctrl *info;
1250 struct device *dev = &pdev->dev;
1251 struct rockchip_pin_ctrl *ctrl;
1252 struct resource *res;
1255 if (!dev->of_node) {
1256 dev_err(dev, "device tree node not found\n");
1260 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1264 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1266 dev_err(dev, "driver data not available\n");
1272 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1274 dev_err(dev, "cannot find IO resource\n");
1278 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1279 if (IS_ERR(info->reg_base))
1280 return PTR_ERR(info->reg_base);
1282 ret = rockchip_gpiolib_register(pdev, info);
1286 ret = rockchip_pinctrl_register(pdev, info);
1288 rockchip_gpiolib_unregister(pdev, info);
1292 platform_set_drvdata(pdev, info);
1297 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1298 PIN_BANK(0, 32, "gpio0"),
1299 PIN_BANK(1, 32, "gpio1"),
1300 PIN_BANK(2, 32, "gpio2"),
1301 PIN_BANK(3, 32, "gpio3"),
1304 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1305 .pin_banks = rk2928_pin_banks,
1306 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1307 .label = "RK2928-GPIO",
1309 .pull_offset = 0x118,
1311 .pull_bank_stride = 8,
1314 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1315 PIN_BANK(0, 32, "gpio0"),
1316 PIN_BANK(1, 32, "gpio1"),
1317 PIN_BANK(2, 32, "gpio2"),
1318 PIN_BANK(3, 32, "gpio3"),
1319 PIN_BANK(4, 32, "gpio4"),
1320 PIN_BANK(6, 16, "gpio6"),
1323 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1324 .pin_banks = rk3066a_pin_banks,
1325 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1326 .label = "RK3066a-GPIO",
1328 .pull_offset = 0x118,
1330 .pull_bank_stride = 8,
1333 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1334 PIN_BANK(0, 32, "gpio0"),
1335 PIN_BANK(1, 32, "gpio1"),
1336 PIN_BANK(2, 32, "gpio2"),
1337 PIN_BANK(3, 32, "gpio3"),
1340 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1341 .pin_banks = rk3066b_pin_banks,
1342 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1343 .label = "RK3066b-GPIO",
1345 .pull_offset = -EINVAL,
1348 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1349 PIN_BANK(0, 32, "gpio0"),
1350 PIN_BANK(1, 32, "gpio1"),
1351 PIN_BANK(2, 32, "gpio2"),
1352 PIN_BANK(3, 32, "gpio3"),
1355 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1356 .pin_banks = rk3188_pin_banks,
1357 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1358 .label = "RK3188-GPIO",
1360 .pull_offset = 0x164,
1361 .pull_bank_stride = 16,
1364 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1365 { .compatible = "rockchip,rk2928-pinctrl",
1366 .data = (void *)&rk2928_pin_ctrl },
1367 { .compatible = "rockchip,rk3066a-pinctrl",
1368 .data = (void *)&rk3066a_pin_ctrl },
1369 { .compatible = "rockchip,rk3066b-pinctrl",
1370 .data = (void *)&rk3066b_pin_ctrl },
1371 { .compatible = "rockchip,rk3188-pinctrl",
1372 .data = (void *)&rk3188_pin_ctrl },
1375 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1377 static struct platform_driver rockchip_pinctrl_driver = {
1378 .probe = rockchip_pinctrl_probe,
1380 .name = "rockchip-pinctrl",
1381 .owner = THIS_MODULE,
1382 .of_match_table = of_match_ptr(rockchip_pinctrl_dt_match),
1386 static int __init rockchip_pinctrl_drv_register(void)
1388 return platform_driver_register(&rockchip_pinctrl_driver);
1390 postcore_initcall(rockchip_pinctrl_drv_register);
1392 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1393 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1394 MODULE_LICENSE("GPL v2");