2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <dt-bindings/pinctrl/rockchip.h>
45 /* GPIO control registers */
46 #define GPIO_SWPORT_DR 0x00
47 #define GPIO_SWPORT_DDR 0x04
48 #define GPIO_INTEN 0x30
49 #define GPIO_INTMASK 0x34
50 #define GPIO_INTTYPE_LEVEL 0x38
51 #define GPIO_INT_POLARITY 0x3c
52 #define GPIO_INT_STATUS 0x40
53 #define GPIO_INT_RAWSTATUS 0x44
54 #define GPIO_DEBOUNCE 0x48
55 #define GPIO_PORTS_EOI 0x4c
56 #define GPIO_EXT_PORT 0x50
57 #define GPIO_LS_SYNC 0x60
60 * @reg_base: register base of the gpio bank
61 * @clk: clock of the gpio bank
62 * @irq: interrupt of the gpio bank
63 * @pin_base: first pin number
64 * @nr_pins: number of pins in this bank
65 * @name: name of the bank
66 * @bank_num: number of the bank, to account for holes
67 * @valid: are all necessary informations present
68 * @of_node: dt node of this bank
69 * @drvdata: common pinctrl basedata
70 * @domain: irqdomain of the gpio bank
71 * @gpio_chip: gpiolib chip
73 * @slock: spinlock for the gpio bank
75 struct rockchip_pin_bank {
76 void __iomem *reg_base;
84 struct device_node *of_node;
85 struct rockchip_pinctrl *drvdata;
86 struct irq_domain *domain;
87 struct gpio_chip gpio_chip;
88 struct pinctrl_gpio_range grange;
93 #define PIN_BANK(id, pins, label) \
101 * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but
102 * instead decide this automatically based on the pad-type.
104 struct rockchip_pin_ctrl {
105 struct rockchip_pin_bank *pin_banks;
112 int pull_bank_stride;
115 struct rockchip_pin_config {
117 unsigned long *configs;
118 unsigned int nconfigs;
122 * struct rockchip_pin_group: represent group of pins of a pinmux function.
123 * @name: name of the pin group, used to lookup the group.
124 * @pins: the pins included in this group.
125 * @npins: number of pins included in this group.
126 * @func: the mux function number to be programmed when selected.
127 * @configs: the config values to be set for each pin
128 * @nconfigs: number of configs for each pin
130 struct rockchip_pin_group {
134 struct rockchip_pin_config *data;
138 * struct rockchip_pmx_func: represent a pin function.
139 * @name: name of the pin function, used to lookup the function.
140 * @groups: one or more names of pin groups that provide this function.
141 * @num_groups: number of groups included in @groups.
143 struct rockchip_pmx_func {
149 struct rockchip_pinctrl {
150 void __iomem *reg_base;
152 struct rockchip_pin_ctrl *ctrl;
153 struct pinctrl_desc pctl;
154 struct pinctrl_dev *pctl_dev;
155 struct rockchip_pin_group *groups;
156 unsigned int ngroups;
157 struct rockchip_pmx_func *functions;
158 unsigned int nfunctions;
161 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
163 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
166 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
167 const struct rockchip_pinctrl *info,
172 for (i = 0; i < info->ngroups; i++) {
173 if (!strcmp(info->groups[i].name, name))
174 return &info->groups[i];
181 * given a pin number that is local to a pin controller, find out the pin bank
182 * and the register base of the pin bank.
184 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
187 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
189 while (pin >= (b->pin_base + b->nr_pins))
195 static struct rockchip_pin_bank *bank_num_to_bank(
196 struct rockchip_pinctrl *info,
199 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
202 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
203 if (b->bank_num == num)
207 return ERR_PTR(-EINVAL);
211 * Pinctrl_ops handling
214 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
216 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
218 return info->ngroups;
221 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
224 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
226 return info->groups[selector].name;
229 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
230 unsigned selector, const unsigned **pins,
233 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
235 if (selector >= info->ngroups)
238 *pins = info->groups[selector].pins;
239 *npins = info->groups[selector].npins;
244 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
245 struct device_node *np,
246 struct pinctrl_map **map, unsigned *num_maps)
248 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
249 const struct rockchip_pin_group *grp;
250 struct pinctrl_map *new_map;
251 struct device_node *parent;
256 * first find the group of this node and check if we need to create
257 * config maps for pins
259 grp = pinctrl_name_to_group(info, np->name);
261 dev_err(info->dev, "unable to find group for node %s\n",
266 map_num += grp->npins;
267 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
276 parent = of_get_parent(np);
278 devm_kfree(pctldev->dev, new_map);
281 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
282 new_map[0].data.mux.function = parent->name;
283 new_map[0].data.mux.group = np->name;
286 /* create config map */
288 for (i = 0; i < grp->npins; i++) {
289 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
290 new_map[i].data.configs.group_or_pin =
291 pin_get_name(pctldev, grp->pins[i]);
292 new_map[i].data.configs.configs = grp->data[i].configs;
293 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
296 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
297 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
302 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
303 struct pinctrl_map *map, unsigned num_maps)
307 static const struct pinctrl_ops rockchip_pctrl_ops = {
308 .get_groups_count = rockchip_get_groups_count,
309 .get_group_name = rockchip_get_group_name,
310 .get_group_pins = rockchip_get_group_pins,
311 .dt_node_to_map = rockchip_dt_node_to_map,
312 .dt_free_map = rockchip_dt_free_map,
320 * Set a new mux function for a pin.
322 * The register is divided into the upper and lower 16 bit. When changing
323 * a value, the previous register value is not read and changed. Instead
324 * it seems the changed bits are marked in the upper 16 bit, while the
325 * changed value gets set in the same offset in the lower 16 bit.
326 * All pin settings seem to be 2 bit wide in both the upper and lower
328 * @bank: pin bank to change
329 * @pin: pin to change
330 * @mux: new mux function to set
332 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
334 struct rockchip_pinctrl *info = bank->drvdata;
335 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
340 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
341 bank->bank_num, pin, mux);
343 /* get basic quadrupel of mux registers and the correct reg inside */
344 reg += bank->bank_num * 0x10;
345 reg += (pin / 8) * 4;
348 spin_lock_irqsave(&bank->slock, flags);
350 data = (3 << (bit + 16));
351 data |= (mux & 3) << bit;
354 spin_unlock_irqrestore(&bank->slock, flags);
357 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
359 struct rockchip_pinctrl *info = bank->drvdata;
360 struct rockchip_pin_ctrl *ctrl = info->ctrl;
364 /* rk3066b does support any pulls */
365 if (!ctrl->pull_offset)
366 return PIN_CONFIG_BIAS_DISABLE;
368 reg = info->reg_base + ctrl->pull_offset;
370 if (ctrl->pull_auto) {
371 reg += bank->bank_num * ctrl->pull_bank_stride;
372 reg += (pin_num / 16) * 4;
375 return !(readl_relaxed(reg) & BIT(bit))
376 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
377 : PIN_CONFIG_BIAS_DISABLE;
379 dev_err(info->dev, "pull support for rk31xx not implemented\n");
384 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
385 int pin_num, int pull)
387 struct rockchip_pinctrl *info = bank->drvdata;
388 struct rockchip_pin_ctrl *ctrl = info->ctrl;
394 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
395 bank->bank_num, pin_num, pull);
397 /* rk3066b does support any pulls */
398 if (!ctrl->pull_offset)
399 return pull ? -EINVAL : 0;
401 reg = info->reg_base + ctrl->pull_offset;
403 if (ctrl->pull_auto) {
404 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
405 pull != PIN_CONFIG_BIAS_DISABLE) {
406 dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
410 reg += bank->bank_num * ctrl->pull_bank_stride;
411 reg += (pin_num / 16) * 4;
414 spin_lock_irqsave(&bank->slock, flags);
416 data = BIT(bit + 16);
417 if (pull == PIN_CONFIG_BIAS_DISABLE)
421 spin_unlock_irqrestore(&bank->slock, flags);
423 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) {
424 dev_err(info->dev, "pull direction (up/down) needs to be specified\n");
428 dev_err(info->dev, "pull support for rk31xx not implemented\n");
436 * Pinmux_ops handling
439 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
441 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
443 return info->nfunctions;
446 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
449 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
451 return info->functions[selector].name;
454 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
455 unsigned selector, const char * const **groups,
456 unsigned * const num_groups)
458 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
460 *groups = info->functions[selector].groups;
461 *num_groups = info->functions[selector].ngroups;
466 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
469 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
470 const unsigned int *pins = info->groups[group].pins;
471 const struct rockchip_pin_config *data = info->groups[group].data;
472 struct rockchip_pin_bank *bank;
475 dev_dbg(info->dev, "enable function %s group %s\n",
476 info->functions[selector].name, info->groups[group].name);
479 * for each pin in the pin group selected, program the correspoding pin
480 * pin function number in the config register.
482 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
483 bank = pin_to_bank(info, pins[cnt]);
484 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
491 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
492 unsigned selector, unsigned group)
494 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
495 const unsigned int *pins = info->groups[group].pins;
496 struct rockchip_pin_bank *bank;
499 dev_dbg(info->dev, "disable function %s group %s\n",
500 info->functions[selector].name, info->groups[group].name);
502 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
503 bank = pin_to_bank(info, pins[cnt]);
504 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
509 * The calls to gpio_direction_output() and gpio_direction_input()
510 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
511 * function called from the gpiolib interface).
513 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
514 struct pinctrl_gpio_range *range,
515 unsigned offset, bool input)
517 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
518 struct rockchip_pin_bank *bank;
519 struct gpio_chip *chip;
524 bank = gc_to_pin_bank(chip);
525 pin = offset - chip->base;
527 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
528 offset, range->name, pin, input ? "input" : "output");
530 rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
532 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
533 /* set bit to 1 for output, 0 for input */
538 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
543 static const struct pinmux_ops rockchip_pmx_ops = {
544 .get_functions_count = rockchip_pmx_get_funcs_count,
545 .get_function_name = rockchip_pmx_get_func_name,
546 .get_function_groups = rockchip_pmx_get_groups,
547 .enable = rockchip_pmx_enable,
548 .disable = rockchip_pmx_disable,
549 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
553 * Pinconf_ops handling
556 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
557 enum pin_config_param pull)
559 /* rk3066b does support any pulls */
560 if (!ctrl->pull_offset)
561 return pull ? false : true;
563 if (ctrl->pull_auto) {
564 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
565 pull != PIN_CONFIG_BIAS_DISABLE)
568 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
575 /* set the pin config settings for a specified pin */
576 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
577 unsigned long config)
579 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
580 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
581 enum pin_config_param param = pinconf_to_config_param(config);
582 u16 arg = pinconf_to_config_argument(config);
585 case PIN_CONFIG_BIAS_DISABLE:
586 return rockchip_set_pull(bank, pin - bank->pin_base, param);
588 case PIN_CONFIG_BIAS_PULL_UP:
589 case PIN_CONFIG_BIAS_PULL_DOWN:
590 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
591 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
597 return rockchip_set_pull(bank, pin - bank->pin_base, param);
607 /* get the pin config settings for a specified pin */
608 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
609 unsigned long *config)
611 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
612 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
613 enum pin_config_param param = pinconf_to_config_param(*config);
616 case PIN_CONFIG_BIAS_DISABLE:
617 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
622 case PIN_CONFIG_BIAS_PULL_UP:
623 case PIN_CONFIG_BIAS_PULL_DOWN:
624 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
625 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
628 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
641 static const struct pinconf_ops rockchip_pinconf_ops = {
642 .pin_config_get = rockchip_pinconf_get,
643 .pin_config_set = rockchip_pinconf_set,
646 static const char *gpio_compat = "rockchip,gpio-bank";
648 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
649 struct device_node *np)
651 struct device_node *child;
653 for_each_child_of_node(np, child) {
654 if (of_device_is_compatible(child, gpio_compat))
658 info->ngroups += of_get_child_count(child);
662 static int rockchip_pinctrl_parse_groups(struct device_node *np,
663 struct rockchip_pin_group *grp,
664 struct rockchip_pinctrl *info,
667 struct rockchip_pin_bank *bank;
674 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
676 /* Initialise group */
677 grp->name = np->name;
680 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
681 * do sanity check and calculate pins number
683 list = of_get_property(np, "rockchip,pins", &size);
684 /* we do not check return since it's safe node passed down */
685 size /= sizeof(*list);
686 if (!size || size % 4) {
687 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
691 grp->npins = size / 4;
693 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
695 grp->data = devm_kzalloc(info->dev, grp->npins *
696 sizeof(struct rockchip_pin_config),
698 if (!grp->pins || !grp->data)
701 for (i = 0, j = 0; i < size; i += 4, j++) {
702 const __be32 *phandle;
703 struct device_node *np_config;
705 num = be32_to_cpu(*list++);
706 bank = bank_num_to_bank(info, num);
708 return PTR_ERR(bank);
710 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
711 grp->data[j].func = be32_to_cpu(*list++);
717 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
718 ret = pinconf_generic_parse_dt_config(np_config,
719 &grp->data[j].configs, &grp->data[j].nconfigs);
727 static int rockchip_pinctrl_parse_functions(struct device_node *np,
728 struct rockchip_pinctrl *info,
731 struct device_node *child;
732 struct rockchip_pmx_func *func;
733 struct rockchip_pin_group *grp;
735 static u32 grp_index;
738 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
740 func = &info->functions[index];
742 /* Initialise function */
743 func->name = np->name;
744 func->ngroups = of_get_child_count(np);
745 if (func->ngroups <= 0)
748 func->groups = devm_kzalloc(info->dev,
749 func->ngroups * sizeof(char *), GFP_KERNEL);
753 for_each_child_of_node(np, child) {
754 func->groups[i] = child->name;
755 grp = &info->groups[grp_index++];
756 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
764 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
765 struct rockchip_pinctrl *info)
767 struct device *dev = &pdev->dev;
768 struct device_node *np = dev->of_node;
769 struct device_node *child;
773 rockchip_pinctrl_child_count(info, np);
775 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
776 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
778 info->functions = devm_kzalloc(dev, info->nfunctions *
779 sizeof(struct rockchip_pmx_func),
781 if (!info->functions) {
782 dev_err(dev, "failed to allocate memory for function list\n");
786 info->groups = devm_kzalloc(dev, info->ngroups *
787 sizeof(struct rockchip_pin_group),
790 dev_err(dev, "failed allocate memory for ping group list\n");
796 for_each_child_of_node(np, child) {
797 if (of_device_is_compatible(child, gpio_compat))
799 ret = rockchip_pinctrl_parse_functions(child, info, i++);
801 dev_err(&pdev->dev, "failed to parse function\n");
809 static int rockchip_pinctrl_register(struct platform_device *pdev,
810 struct rockchip_pinctrl *info)
812 struct pinctrl_desc *ctrldesc = &info->pctl;
813 struct pinctrl_pin_desc *pindesc, *pdesc;
814 struct rockchip_pin_bank *pin_bank;
818 ctrldesc->name = "rockchip-pinctrl";
819 ctrldesc->owner = THIS_MODULE;
820 ctrldesc->pctlops = &rockchip_pctrl_ops;
821 ctrldesc->pmxops = &rockchip_pmx_ops;
822 ctrldesc->confops = &rockchip_pinconf_ops;
824 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
825 info->ctrl->nr_pins, GFP_KERNEL);
827 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
830 ctrldesc->pins = pindesc;
831 ctrldesc->npins = info->ctrl->nr_pins;
834 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
835 pin_bank = &info->ctrl->pin_banks[bank];
836 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
838 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
839 pin_bank->name, pin);
844 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
845 if (!info->pctl_dev) {
846 dev_err(&pdev->dev, "could not register pinctrl driver\n");
850 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
851 pin_bank = &info->ctrl->pin_banks[bank];
852 pin_bank->grange.name = pin_bank->name;
853 pin_bank->grange.id = bank;
854 pin_bank->grange.pin_base = pin_bank->pin_base;
855 pin_bank->grange.base = pin_bank->gpio_chip.base;
856 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
857 pin_bank->grange.gc = &pin_bank->gpio_chip;
858 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
861 ret = rockchip_pinctrl_parse_dt(pdev, info);
863 pinctrl_unregister(info->pctl_dev);
874 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
876 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
877 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
881 spin_lock_irqsave(&bank->slock, flags);
884 data &= ~BIT(offset);
889 spin_unlock_irqrestore(&bank->slock, flags);
893 * Returns the level of the pin for input direction and setting of the DR
894 * register for output gpios.
896 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
898 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
901 data = readl(bank->reg_base + GPIO_EXT_PORT);
908 * gpiolib gpio_direction_input callback function. The setting of the pin
909 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
912 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
914 return pinctrl_gpio_direction_input(gc->base + offset);
918 * gpiolib gpio_direction_output callback function. The setting of the pin
919 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
922 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
923 unsigned offset, int value)
925 rockchip_gpio_set(gc, offset, value);
926 return pinctrl_gpio_direction_output(gc->base + offset);
930 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
931 * and a virtual IRQ, if not already present.
933 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
935 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
941 virq = irq_create_mapping(bank->domain, offset);
943 return (virq) ? : -ENXIO;
946 static const struct gpio_chip rockchip_gpiolib_chip = {
947 .set = rockchip_gpio_set,
948 .get = rockchip_gpio_get,
949 .direction_input = rockchip_gpio_direction_input,
950 .direction_output = rockchip_gpio_direction_output,
951 .to_irq = rockchip_gpio_to_irq,
952 .owner = THIS_MODULE,
959 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
961 struct irq_chip *chip = irq_get_chip(irq);
962 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
965 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
967 chained_irq_enter(chip, desc);
969 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
976 virq = irq_linear_revmap(bank->domain, irq);
979 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
983 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
985 generic_handle_irq(virq);
988 chained_irq_exit(chip, desc);
991 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
993 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
994 struct rockchip_pin_bank *bank = gc->private;
995 u32 mask = BIT(d->hwirq);
1000 if (type & IRQ_TYPE_EDGE_BOTH)
1001 __irq_set_handler_locked(d->irq, handle_edge_irq);
1003 __irq_set_handler_locked(d->irq, handle_level_irq);
1007 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1008 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1011 case IRQ_TYPE_EDGE_RISING:
1015 case IRQ_TYPE_EDGE_FALLING:
1019 case IRQ_TYPE_LEVEL_HIGH:
1023 case IRQ_TYPE_LEVEL_LOW:
1032 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1033 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1037 /* make sure the pin is configured as gpio input */
1038 rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1039 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1041 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1046 static int rockchip_interrupts_register(struct platform_device *pdev,
1047 struct rockchip_pinctrl *info)
1049 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1050 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1051 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1052 struct irq_chip_generic *gc;
1056 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1058 dev_warn(&pdev->dev, "bank %s is not valid\n",
1063 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1064 &irq_generic_chip_ops, NULL);
1065 if (!bank->domain) {
1066 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1071 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1072 "rockchip_gpio_irq", handle_level_irq,
1073 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1075 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1077 irq_domain_remove(bank->domain);
1081 gc = irq_get_domain_generic_chip(bank->domain, 0);
1082 gc->reg_base = bank->reg_base;
1084 gc->chip_types[0].regs.mask = GPIO_INTEN;
1085 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1086 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1087 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1088 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1089 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1090 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1092 irq_set_handler_data(bank->irq, bank);
1093 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1099 static int rockchip_gpiolib_register(struct platform_device *pdev,
1100 struct rockchip_pinctrl *info)
1102 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1103 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1104 struct gpio_chip *gc;
1108 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1110 dev_warn(&pdev->dev, "bank %s is not valid\n",
1115 bank->gpio_chip = rockchip_gpiolib_chip;
1117 gc = &bank->gpio_chip;
1118 gc->base = bank->pin_base;
1119 gc->ngpio = bank->nr_pins;
1120 gc->dev = &pdev->dev;
1121 gc->of_node = bank->of_node;
1122 gc->label = bank->name;
1124 ret = gpiochip_add(gc);
1126 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1132 rockchip_interrupts_register(pdev, info);
1137 for (--i, --bank; i >= 0; --i, --bank) {
1141 if (gpiochip_remove(&bank->gpio_chip))
1142 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1143 bank->gpio_chip.label);
1148 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1149 struct rockchip_pinctrl *info)
1151 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1152 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1156 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1160 ret = gpiochip_remove(&bank->gpio_chip);
1164 dev_err(&pdev->dev, "gpio chip remove failed\n");
1169 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1172 struct resource res;
1174 if (of_address_to_resource(bank->of_node, 0, &res)) {
1175 dev_err(dev, "cannot find IO resource for bank\n");
1179 bank->reg_base = devm_ioremap_resource(dev, &res);
1180 if (IS_ERR(bank->reg_base))
1181 return PTR_ERR(bank->reg_base);
1183 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1185 bank->clk = of_clk_get(bank->of_node, 0);
1186 if (IS_ERR(bank->clk))
1187 return PTR_ERR(bank->clk);
1189 return clk_prepare_enable(bank->clk);
1192 static const struct of_device_id rockchip_pinctrl_dt_match[];
1194 /* retrieve the soc specific data */
1195 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1196 struct rockchip_pinctrl *d,
1197 struct platform_device *pdev)
1199 const struct of_device_id *match;
1200 struct device_node *node = pdev->dev.of_node;
1201 struct device_node *np;
1202 struct rockchip_pin_ctrl *ctrl;
1203 struct rockchip_pin_bank *bank;
1206 match = of_match_node(rockchip_pinctrl_dt_match, node);
1207 ctrl = (struct rockchip_pin_ctrl *)match->data;
1209 for_each_child_of_node(node, np) {
1210 if (!of_find_property(np, "gpio-controller", NULL))
1213 bank = ctrl->pin_banks;
1214 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1215 if (!strcmp(bank->name, np->name)) {
1218 if (!rockchip_get_bank_data(bank, &pdev->dev))
1226 bank = ctrl->pin_banks;
1227 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1228 spin_lock_init(&bank->slock);
1230 bank->pin_base = ctrl->nr_pins;
1231 ctrl->nr_pins += bank->nr_pins;
1237 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1239 struct rockchip_pinctrl *info;
1240 struct device *dev = &pdev->dev;
1241 struct rockchip_pin_ctrl *ctrl;
1242 struct resource *res;
1245 if (!dev->of_node) {
1246 dev_err(dev, "device tree node not found\n");
1250 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1254 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1256 dev_err(dev, "driver data not available\n");
1262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1263 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1264 if (IS_ERR(info->reg_base))
1265 return PTR_ERR(info->reg_base);
1267 ret = rockchip_gpiolib_register(pdev, info);
1271 ret = rockchip_pinctrl_register(pdev, info);
1273 rockchip_gpiolib_unregister(pdev, info);
1277 platform_set_drvdata(pdev, info);
1282 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1283 PIN_BANK(0, 32, "gpio0"),
1284 PIN_BANK(1, 32, "gpio1"),
1285 PIN_BANK(2, 32, "gpio2"),
1286 PIN_BANK(3, 32, "gpio3"),
1289 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1290 .pin_banks = rk2928_pin_banks,
1291 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1292 .label = "RK2928-GPIO",
1294 .pull_offset = 0x118,
1296 .pull_bank_stride = 8,
1299 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1300 PIN_BANK(0, 32, "gpio0"),
1301 PIN_BANK(1, 32, "gpio1"),
1302 PIN_BANK(2, 32, "gpio2"),
1303 PIN_BANK(3, 32, "gpio3"),
1304 PIN_BANK(4, 32, "gpio4"),
1305 PIN_BANK(6, 16, "gpio6"),
1308 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1309 .pin_banks = rk3066a_pin_banks,
1310 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1311 .label = "RK3066a-GPIO",
1313 .pull_offset = 0x118,
1315 .pull_bank_stride = 8,
1318 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1319 PIN_BANK(0, 32, "gpio0"),
1320 PIN_BANK(1, 32, "gpio1"),
1321 PIN_BANK(2, 32, "gpio2"),
1322 PIN_BANK(3, 32, "gpio3"),
1325 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1326 .pin_banks = rk3066b_pin_banks,
1327 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1328 .label = "RK3066b-GPIO",
1330 .pull_offset = -EINVAL,
1333 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1334 PIN_BANK(0, 32, "gpio0"),
1335 PIN_BANK(1, 32, "gpio1"),
1336 PIN_BANK(2, 32, "gpio2"),
1337 PIN_BANK(3, 32, "gpio3"),
1340 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1341 .pin_banks = rk3188_pin_banks,
1342 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1343 .label = "RK3188-GPIO",
1345 .pull_offset = 0x164,
1346 .pull_bank_stride = 16,
1349 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1350 { .compatible = "rockchip,rk2928-pinctrl",
1351 .data = (void *)&rk2928_pin_ctrl },
1352 { .compatible = "rockchip,rk3066a-pinctrl",
1353 .data = (void *)&rk3066a_pin_ctrl },
1354 { .compatible = "rockchip,rk3066b-pinctrl",
1355 .data = (void *)&rk3066b_pin_ctrl },
1356 { .compatible = "rockchip,rk3188-pinctrl",
1357 .data = (void *)&rk3188_pin_ctrl },
1360 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1362 static struct platform_driver rockchip_pinctrl_driver = {
1363 .probe = rockchip_pinctrl_probe,
1365 .name = "rockchip-pinctrl",
1366 .owner = THIS_MODULE,
1367 .of_match_table = rockchip_pinctrl_dt_match,
1371 static int __init rockchip_pinctrl_drv_register(void)
1373 return platform_driver_register(&rockchip_pinctrl_driver);
1375 postcore_initcall(rockchip_pinctrl_drv_register);
1377 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1378 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1379 MODULE_LICENSE("GPL v2");