2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
61 enum rockchip_pinctrl_type {
69 * Encode variants of iomux registers into a type variable
71 #define IOMUX_GPIO_ONLY BIT(0)
72 #define IOMUX_WIDTH_4BIT BIT(1)
73 #define IOMUX_SOURCE_PMU BIT(2)
74 #define IOMUX_UNROUTED BIT(3)
77 * @type: iomux variant using IOMUX_* constants
78 * @offset: if initialized to -1 it will be autocalculated, by specifying
79 * an initial offset value the relevant source offset can be reset
80 * to a new value for autocalculating the following iomux registers.
82 struct rockchip_iomux {
88 * @reg_base: register base of the gpio bank
89 * @reg_pull: optional separate register for additional pull settings
90 * @clk: clock of the gpio bank
91 * @irq: interrupt of the gpio bank
92 * @pin_base: first pin number
93 * @nr_pins: number of pins in this bank
94 * @name: name of the bank
95 * @bank_num: number of the bank, to account for holes
96 * @iomux: array describing the 4 iomux sources of the bank
97 * @valid: are all necessary informations present
98 * @of_node: dt node of this bank
99 * @drvdata: common pinctrl basedata
100 * @domain: irqdomain of the gpio bank
101 * @gpio_chip: gpiolib chip
102 * @grange: gpio range
103 * @slock: spinlock for the gpio bank
105 struct rockchip_pin_bank {
106 void __iomem *reg_base;
107 struct regmap *regmap_pull;
114 struct rockchip_iomux iomux[4];
116 struct device_node *of_node;
117 struct rockchip_pinctrl *drvdata;
118 struct irq_domain *domain;
119 struct gpio_chip gpio_chip;
120 struct pinctrl_gpio_range grange;
122 u32 toggle_edge_mode;
125 #define PIN_BANK(id, pins, label) \
138 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
144 { .type = iom0, .offset = -1 }, \
145 { .type = iom1, .offset = -1 }, \
146 { .type = iom2, .offset = -1 }, \
147 { .type = iom3, .offset = -1 }, \
153 struct rockchip_pin_ctrl {
154 struct rockchip_pin_bank *pin_banks;
158 enum rockchip_pinctrl_type type;
161 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
162 int pin_num, struct regmap **regmap,
166 struct rockchip_pin_config {
168 unsigned long *configs;
169 unsigned int nconfigs;
173 * struct rockchip_pin_group: represent group of pins of a pinmux function.
174 * @name: name of the pin group, used to lookup the group.
175 * @pins: the pins included in this group.
176 * @npins: number of pins included in this group.
177 * @func: the mux function number to be programmed when selected.
178 * @configs: the config values to be set for each pin
179 * @nconfigs: number of configs for each pin
181 struct rockchip_pin_group {
185 struct rockchip_pin_config *data;
189 * struct rockchip_pmx_func: represent a pin function.
190 * @name: name of the pin function, used to lookup the function.
191 * @groups: one or more names of pin groups that provide this function.
192 * @num_groups: number of groups included in @groups.
194 struct rockchip_pmx_func {
200 struct rockchip_pinctrl {
201 struct regmap *regmap_base;
203 struct regmap *regmap_pull;
204 struct regmap *regmap_pmu;
206 struct rockchip_pin_ctrl *ctrl;
207 struct pinctrl_desc pctl;
208 struct pinctrl_dev *pctl_dev;
209 struct rockchip_pin_group *groups;
210 unsigned int ngroups;
211 struct rockchip_pmx_func *functions;
212 unsigned int nfunctions;
215 static struct regmap_config rockchip_regmap_config = {
221 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
223 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
226 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
227 const struct rockchip_pinctrl *info,
232 for (i = 0; i < info->ngroups; i++) {
233 if (!strcmp(info->groups[i].name, name))
234 return &info->groups[i];
241 * given a pin number that is local to a pin controller, find out the pin bank
242 * and the register base of the pin bank.
244 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
247 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
249 while (pin >= (b->pin_base + b->nr_pins))
255 static struct rockchip_pin_bank *bank_num_to_bank(
256 struct rockchip_pinctrl *info,
259 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
262 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
263 if (b->bank_num == num)
267 return ERR_PTR(-EINVAL);
271 * Pinctrl_ops handling
274 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
276 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
278 return info->ngroups;
281 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
284 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
286 return info->groups[selector].name;
289 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
290 unsigned selector, const unsigned **pins,
293 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
295 if (selector >= info->ngroups)
298 *pins = info->groups[selector].pins;
299 *npins = info->groups[selector].npins;
304 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
305 struct device_node *np,
306 struct pinctrl_map **map, unsigned *num_maps)
308 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
309 const struct rockchip_pin_group *grp;
310 struct pinctrl_map *new_map;
311 struct device_node *parent;
316 * first find the group of this node and check if we need to create
317 * config maps for pins
319 grp = pinctrl_name_to_group(info, np->name);
321 dev_err(info->dev, "unable to find group for node %s\n",
326 map_num += grp->npins;
327 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
336 parent = of_get_parent(np);
338 devm_kfree(pctldev->dev, new_map);
341 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
342 new_map[0].data.mux.function = parent->name;
343 new_map[0].data.mux.group = np->name;
346 /* create config map */
348 for (i = 0; i < grp->npins; i++) {
349 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
350 new_map[i].data.configs.group_or_pin =
351 pin_get_name(pctldev, grp->pins[i]);
352 new_map[i].data.configs.configs = grp->data[i].configs;
353 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
356 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
357 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
362 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
363 struct pinctrl_map *map, unsigned num_maps)
367 static const struct pinctrl_ops rockchip_pctrl_ops = {
368 .get_groups_count = rockchip_get_groups_count,
369 .get_group_name = rockchip_get_group_name,
370 .get_group_pins = rockchip_get_group_pins,
371 .dt_node_to_map = rockchip_dt_node_to_map,
372 .dt_free_map = rockchip_dt_free_map,
379 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
381 struct rockchip_pinctrl *info = bank->drvdata;
382 int iomux_num = (pin / 8);
383 struct regmap *regmap;
391 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
392 dev_err(info->dev, "pin %d is unrouted\n", pin);
396 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
399 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
400 ? info->regmap_pmu : info->regmap_base;
402 /* get basic quadrupel of mux registers and the correct reg inside */
403 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
404 reg = bank->iomux[iomux_num].offset;
405 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
413 ret = regmap_read(regmap, reg, &val);
417 return ((val >> bit) & mask);
421 * Set a new mux function for a pin.
423 * The register is divided into the upper and lower 16 bit. When changing
424 * a value, the previous register value is not read and changed. Instead
425 * it seems the changed bits are marked in the upper 16 bit, while the
426 * changed value gets set in the same offset in the lower 16 bit.
427 * All pin settings seem to be 2 bit wide in both the upper and lower
429 * @bank: pin bank to change
430 * @pin: pin to change
431 * @mux: new mux function to set
433 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
435 struct rockchip_pinctrl *info = bank->drvdata;
436 int iomux_num = (pin / 8);
437 struct regmap *regmap;
446 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
447 dev_err(info->dev, "pin %d is unrouted\n", pin);
451 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
452 if (mux != RK_FUNC_GPIO) {
454 "pin %d only supports a gpio mux\n", pin);
461 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
462 bank->bank_num, pin, mux);
464 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
465 ? info->regmap_pmu : info->regmap_base;
467 /* get basic quadrupel of mux registers and the correct reg inside */
468 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
469 reg = bank->iomux[iomux_num].offset;
470 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
478 spin_lock_irqsave(&bank->slock, flags);
480 data = (mask << (bit + 16));
481 data |= (mux & mask) << bit;
482 ret = regmap_write(regmap, reg, data);
484 spin_unlock_irqrestore(&bank->slock, flags);
489 #define RK2928_PULL_OFFSET 0x118
490 #define RK2928_PULL_PINS_PER_REG 16
491 #define RK2928_PULL_BANK_STRIDE 8
493 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
494 int pin_num, struct regmap **regmap,
497 struct rockchip_pinctrl *info = bank->drvdata;
499 *regmap = info->regmap_base;
500 *reg = RK2928_PULL_OFFSET;
501 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
502 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
504 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
507 #define RK3188_PULL_OFFSET 0x164
508 #define RK3188_PULL_BITS_PER_PIN 2
509 #define RK3188_PULL_PINS_PER_REG 8
510 #define RK3188_PULL_BANK_STRIDE 16
511 #define RK3188_PULL_PMU_OFFSET 0x64
513 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
514 int pin_num, struct regmap **regmap,
517 struct rockchip_pinctrl *info = bank->drvdata;
519 /* The first 12 pins of the first bank are located elsewhere */
520 if (bank->bank_num == 0 && pin_num < 12) {
521 *regmap = info->regmap_pmu ? info->regmap_pmu
523 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
524 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
525 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
526 *bit *= RK3188_PULL_BITS_PER_PIN;
528 *regmap = info->regmap_pull ? info->regmap_pull
530 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
532 /* correct the offset, as it is the 2nd pull register */
534 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
535 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
538 * The bits in these registers have an inverse ordering
539 * with the lowest pin being in bits 15:14 and the highest
542 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
543 *bit *= RK3188_PULL_BITS_PER_PIN;
547 #define RK3288_PULL_OFFSET 0x140
548 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
549 int pin_num, struct regmap **regmap,
552 struct rockchip_pinctrl *info = bank->drvdata;
554 /* The first 24 pins of the first bank are located in PMU */
555 if (bank->bank_num == 0) {
556 *regmap = info->regmap_pmu;
557 *reg = RK3188_PULL_PMU_OFFSET;
559 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
560 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
561 *bit *= RK3188_PULL_BITS_PER_PIN;
563 *regmap = info->regmap_base;
564 *reg = RK3288_PULL_OFFSET;
566 /* correct the offset, as we're starting with the 2nd bank */
568 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
569 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
571 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
572 *bit *= RK3188_PULL_BITS_PER_PIN;
576 #define RK3288_DRV_PMU_OFFSET 0x70
577 #define RK3288_DRV_GRF_OFFSET 0x1c0
578 #define RK3288_DRV_BITS_PER_PIN 2
579 #define RK3288_DRV_PINS_PER_REG 8
580 #define RK3288_DRV_BANK_STRIDE 16
581 static int rk3288_drv_list[] = { 2, 4, 8, 12 };
583 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
584 int pin_num, struct regmap **regmap,
587 struct rockchip_pinctrl *info = bank->drvdata;
589 /* The first 24 pins of the first bank are located in PMU */
590 if (bank->bank_num == 0) {
591 *regmap = info->regmap_pmu;
592 *reg = RK3288_DRV_PMU_OFFSET;
594 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
595 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
596 *bit *= RK3288_DRV_BITS_PER_PIN;
598 *regmap = info->regmap_base;
599 *reg = RK3288_DRV_GRF_OFFSET;
601 /* correct the offset, as we're starting with the 2nd bank */
603 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
604 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
606 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
607 *bit *= RK3288_DRV_BITS_PER_PIN;
611 static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
613 struct regmap *regmap;
618 rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
620 ret = regmap_read(regmap, reg, &data);
625 data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
627 return rk3288_drv_list[data];
630 static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
633 struct rockchip_pinctrl *info = bank->drvdata;
634 struct regmap *regmap;
640 rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
643 for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
644 if (rk3288_drv_list[i] == strength) {
651 dev_err(info->dev, "unsupported driver strength %d\n",
656 spin_lock_irqsave(&bank->slock, flags);
658 /* enable the write to the equivalent lower bits */
659 data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
660 data |= (ret << bit);
662 ret = regmap_write(regmap, reg, data);
663 spin_unlock_irqrestore(&bank->slock, flags);
668 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
670 struct rockchip_pinctrl *info = bank->drvdata;
671 struct rockchip_pin_ctrl *ctrl = info->ctrl;
672 struct regmap *regmap;
677 /* rk3066b does support any pulls */
678 if (ctrl->type == RK3066B)
679 return PIN_CONFIG_BIAS_DISABLE;
681 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
683 ret = regmap_read(regmap, reg, &data);
687 switch (ctrl->type) {
689 return !(data & BIT(bit))
690 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
691 : PIN_CONFIG_BIAS_DISABLE;
695 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
699 return PIN_CONFIG_BIAS_DISABLE;
701 return PIN_CONFIG_BIAS_PULL_UP;
703 return PIN_CONFIG_BIAS_PULL_DOWN;
705 return PIN_CONFIG_BIAS_BUS_HOLD;
708 dev_err(info->dev, "unknown pull setting\n");
711 dev_err(info->dev, "unsupported pinctrl type\n");
716 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
717 int pin_num, int pull)
719 struct rockchip_pinctrl *info = bank->drvdata;
720 struct rockchip_pin_ctrl *ctrl = info->ctrl;
721 struct regmap *regmap;
727 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
728 bank->bank_num, pin_num, pull);
730 /* rk3066b does support any pulls */
731 if (ctrl->type == RK3066B)
732 return pull ? -EINVAL : 0;
734 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
736 switch (ctrl->type) {
738 spin_lock_irqsave(&bank->slock, flags);
740 data = BIT(bit + 16);
741 if (pull == PIN_CONFIG_BIAS_DISABLE)
743 ret = regmap_write(regmap, reg, data);
745 spin_unlock_irqrestore(&bank->slock, flags);
749 spin_lock_irqsave(&bank->slock, flags);
751 /* enable the write to the equivalent lower bits */
752 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
755 case PIN_CONFIG_BIAS_DISABLE:
757 case PIN_CONFIG_BIAS_PULL_UP:
760 case PIN_CONFIG_BIAS_PULL_DOWN:
763 case PIN_CONFIG_BIAS_BUS_HOLD:
767 spin_unlock_irqrestore(&bank->slock, flags);
768 dev_err(info->dev, "unsupported pull setting %d\n",
773 ret = regmap_write(regmap, reg, data);
775 spin_unlock_irqrestore(&bank->slock, flags);
778 dev_err(info->dev, "unsupported pinctrl type\n");
786 * Pinmux_ops handling
789 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
791 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
793 return info->nfunctions;
796 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
799 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
801 return info->functions[selector].name;
804 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
805 unsigned selector, const char * const **groups,
806 unsigned * const num_groups)
808 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
810 *groups = info->functions[selector].groups;
811 *num_groups = info->functions[selector].ngroups;
816 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
819 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
820 const unsigned int *pins = info->groups[group].pins;
821 const struct rockchip_pin_config *data = info->groups[group].data;
822 struct rockchip_pin_bank *bank;
825 dev_dbg(info->dev, "enable function %s group %s\n",
826 info->functions[selector].name, info->groups[group].name);
829 * for each pin in the pin group selected, program the correspoding pin
830 * pin function number in the config register.
832 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
833 bank = pin_to_bank(info, pins[cnt]);
834 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
841 /* revert the already done pin settings */
842 for (cnt--; cnt >= 0; cnt--)
843 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
852 * The calls to gpio_direction_output() and gpio_direction_input()
853 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
854 * function called from the gpiolib interface).
856 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
857 struct pinctrl_gpio_range *range,
858 unsigned offset, bool input)
860 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
861 struct rockchip_pin_bank *bank;
862 struct gpio_chip *chip;
867 bank = gc_to_pin_bank(chip);
868 pin = offset - chip->base;
870 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
871 offset, range->name, pin, input ? "input" : "output");
873 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
877 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
878 /* set bit to 1 for output, 0 for input */
883 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
888 static const struct pinmux_ops rockchip_pmx_ops = {
889 .get_functions_count = rockchip_pmx_get_funcs_count,
890 .get_function_name = rockchip_pmx_get_func_name,
891 .get_function_groups = rockchip_pmx_get_groups,
892 .enable = rockchip_pmx_enable,
893 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
897 * Pinconf_ops handling
900 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
901 enum pin_config_param pull)
903 switch (ctrl->type) {
905 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
906 pull == PIN_CONFIG_BIAS_DISABLE);
908 return pull ? false : true;
911 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
917 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
918 unsigned offset, int value);
919 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
921 /* set the pin config settings for a specified pin */
922 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
923 unsigned long *configs, unsigned num_configs)
925 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
926 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
927 enum pin_config_param param;
932 for (i = 0; i < num_configs; i++) {
933 param = pinconf_to_config_param(configs[i]);
934 arg = pinconf_to_config_argument(configs[i]);
937 case PIN_CONFIG_BIAS_DISABLE:
938 rc = rockchip_set_pull(bank, pin - bank->pin_base,
943 case PIN_CONFIG_BIAS_PULL_UP:
944 case PIN_CONFIG_BIAS_PULL_DOWN:
945 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
946 case PIN_CONFIG_BIAS_BUS_HOLD:
947 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
953 rc = rockchip_set_pull(bank, pin - bank->pin_base,
958 case PIN_CONFIG_OUTPUT:
959 rc = rockchip_gpio_direction_output(&bank->gpio_chip,
960 pin - bank->pin_base,
965 case PIN_CONFIG_DRIVE_STRENGTH:
966 /* rk3288 is the first with per-pin drive-strength */
967 if (info->ctrl->type != RK3288)
970 rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
978 } /* for each config */
983 /* get the pin config settings for a specified pin */
984 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
985 unsigned long *config)
987 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
988 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
989 enum pin_config_param param = pinconf_to_config_param(*config);
994 case PIN_CONFIG_BIAS_DISABLE:
995 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1000 case PIN_CONFIG_BIAS_PULL_UP:
1001 case PIN_CONFIG_BIAS_PULL_DOWN:
1002 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1003 case PIN_CONFIG_BIAS_BUS_HOLD:
1004 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1007 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1012 case PIN_CONFIG_OUTPUT:
1013 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1014 if (rc != RK_FUNC_GPIO)
1017 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1023 case PIN_CONFIG_DRIVE_STRENGTH:
1024 /* rk3288 is the first with per-pin drive-strength */
1025 if (info->ctrl->type != RK3288)
1028 rc = rk3288_get_drive(bank, pin - bank->pin_base);
1039 *config = pinconf_to_config_packed(param, arg);
1044 static const struct pinconf_ops rockchip_pinconf_ops = {
1045 .pin_config_get = rockchip_pinconf_get,
1046 .pin_config_set = rockchip_pinconf_set,
1050 static const struct of_device_id rockchip_bank_match[] = {
1051 { .compatible = "rockchip,gpio-bank" },
1052 { .compatible = "rockchip,rk3188-gpio-bank0" },
1056 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1057 struct device_node *np)
1059 struct device_node *child;
1061 for_each_child_of_node(np, child) {
1062 if (of_match_node(rockchip_bank_match, child))
1066 info->ngroups += of_get_child_count(child);
1070 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1071 struct rockchip_pin_group *grp,
1072 struct rockchip_pinctrl *info,
1075 struct rockchip_pin_bank *bank;
1082 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1084 /* Initialise group */
1085 grp->name = np->name;
1088 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1089 * do sanity check and calculate pins number
1091 list = of_get_property(np, "rockchip,pins", &size);
1092 /* we do not check return since it's safe node passed down */
1093 size /= sizeof(*list);
1094 if (!size || size % 4) {
1095 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1099 grp->npins = size / 4;
1101 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1103 grp->data = devm_kzalloc(info->dev, grp->npins *
1104 sizeof(struct rockchip_pin_config),
1106 if (!grp->pins || !grp->data)
1109 for (i = 0, j = 0; i < size; i += 4, j++) {
1110 const __be32 *phandle;
1111 struct device_node *np_config;
1113 num = be32_to_cpu(*list++);
1114 bank = bank_num_to_bank(info, num);
1116 return PTR_ERR(bank);
1118 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1119 grp->data[j].func = be32_to_cpu(*list++);
1125 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1126 ret = pinconf_generic_parse_dt_config(np_config,
1127 &grp->data[j].configs, &grp->data[j].nconfigs);
1135 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1136 struct rockchip_pinctrl *info,
1139 struct device_node *child;
1140 struct rockchip_pmx_func *func;
1141 struct rockchip_pin_group *grp;
1143 static u32 grp_index;
1146 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1148 func = &info->functions[index];
1150 /* Initialise function */
1151 func->name = np->name;
1152 func->ngroups = of_get_child_count(np);
1153 if (func->ngroups <= 0)
1156 func->groups = devm_kzalloc(info->dev,
1157 func->ngroups * sizeof(char *), GFP_KERNEL);
1161 for_each_child_of_node(np, child) {
1162 func->groups[i] = child->name;
1163 grp = &info->groups[grp_index++];
1164 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1172 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1173 struct rockchip_pinctrl *info)
1175 struct device *dev = &pdev->dev;
1176 struct device_node *np = dev->of_node;
1177 struct device_node *child;
1181 rockchip_pinctrl_child_count(info, np);
1183 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1184 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1186 info->functions = devm_kzalloc(dev, info->nfunctions *
1187 sizeof(struct rockchip_pmx_func),
1189 if (!info->functions) {
1190 dev_err(dev, "failed to allocate memory for function list\n");
1194 info->groups = devm_kzalloc(dev, info->ngroups *
1195 sizeof(struct rockchip_pin_group),
1197 if (!info->groups) {
1198 dev_err(dev, "failed allocate memory for ping group list\n");
1204 for_each_child_of_node(np, child) {
1205 if (of_match_node(rockchip_bank_match, child))
1208 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1210 dev_err(&pdev->dev, "failed to parse function\n");
1218 static int rockchip_pinctrl_register(struct platform_device *pdev,
1219 struct rockchip_pinctrl *info)
1221 struct pinctrl_desc *ctrldesc = &info->pctl;
1222 struct pinctrl_pin_desc *pindesc, *pdesc;
1223 struct rockchip_pin_bank *pin_bank;
1227 ctrldesc->name = "rockchip-pinctrl";
1228 ctrldesc->owner = THIS_MODULE;
1229 ctrldesc->pctlops = &rockchip_pctrl_ops;
1230 ctrldesc->pmxops = &rockchip_pmx_ops;
1231 ctrldesc->confops = &rockchip_pinconf_ops;
1233 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1234 info->ctrl->nr_pins, GFP_KERNEL);
1236 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1239 ctrldesc->pins = pindesc;
1240 ctrldesc->npins = info->ctrl->nr_pins;
1243 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1244 pin_bank = &info->ctrl->pin_banks[bank];
1245 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1247 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1248 pin_bank->name, pin);
1253 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1254 if (!info->pctl_dev) {
1255 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1259 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1260 pin_bank = &info->ctrl->pin_banks[bank];
1261 pin_bank->grange.name = pin_bank->name;
1262 pin_bank->grange.id = bank;
1263 pin_bank->grange.pin_base = pin_bank->pin_base;
1264 pin_bank->grange.base = pin_bank->gpio_chip.base;
1265 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1266 pin_bank->grange.gc = &pin_bank->gpio_chip;
1267 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1270 ret = rockchip_pinctrl_parse_dt(pdev, info);
1272 pinctrl_unregister(info->pctl_dev);
1283 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1285 return pinctrl_request_gpio(chip->base + offset);
1288 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1290 pinctrl_free_gpio(chip->base + offset);
1293 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1295 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1296 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1297 unsigned long flags;
1300 spin_lock_irqsave(&bank->slock, flags);
1303 data &= ~BIT(offset);
1305 data |= BIT(offset);
1308 spin_unlock_irqrestore(&bank->slock, flags);
1312 * Returns the level of the pin for input direction and setting of the DR
1313 * register for output gpios.
1315 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1317 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1320 data = readl(bank->reg_base + GPIO_EXT_PORT);
1327 * gpiolib gpio_direction_input callback function. The setting of the pin
1328 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1331 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1333 return pinctrl_gpio_direction_input(gc->base + offset);
1337 * gpiolib gpio_direction_output callback function. The setting of the pin
1338 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1341 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1342 unsigned offset, int value)
1344 rockchip_gpio_set(gc, offset, value);
1345 return pinctrl_gpio_direction_output(gc->base + offset);
1349 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1350 * and a virtual IRQ, if not already present.
1352 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1354 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1360 virq = irq_create_mapping(bank->domain, offset);
1362 return (virq) ? : -ENXIO;
1365 static const struct gpio_chip rockchip_gpiolib_chip = {
1366 .request = rockchip_gpio_request,
1367 .free = rockchip_gpio_free,
1368 .set = rockchip_gpio_set,
1369 .get = rockchip_gpio_get,
1370 .direction_input = rockchip_gpio_direction_input,
1371 .direction_output = rockchip_gpio_direction_output,
1372 .to_irq = rockchip_gpio_to_irq,
1373 .owner = THIS_MODULE,
1377 * Interrupt handling
1380 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1382 struct irq_chip *chip = irq_get_chip(irq);
1383 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1384 u32 polarity = 0, data = 0;
1386 bool edge_changed = false;
1388 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1390 chained_irq_enter(chip, desc);
1392 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1394 if (bank->toggle_edge_mode) {
1395 polarity = readl_relaxed(bank->reg_base +
1397 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1405 virq = irq_linear_revmap(bank->domain, irq);
1408 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1412 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1415 * Triggering IRQ on both rising and falling edge
1416 * needs manual intervention.
1418 if (bank->toggle_edge_mode & BIT(irq)) {
1419 if (data & BIT(irq))
1420 polarity &= ~BIT(irq);
1422 polarity |= BIT(irq);
1424 edge_changed = true;
1427 generic_handle_irq(virq);
1430 if (bank->toggle_edge_mode && edge_changed) {
1431 /* Interrupt params should only be set with ints disabled */
1432 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1433 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1434 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1435 writel(data, bank->reg_base + GPIO_INTEN);
1438 chained_irq_exit(chip, desc);
1441 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1443 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1444 struct rockchip_pin_bank *bank = gc->private;
1445 u32 mask = BIT(d->hwirq);
1451 /* make sure the pin is configured as gpio input */
1452 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1456 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1458 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1460 if (type & IRQ_TYPE_EDGE_BOTH)
1461 __irq_set_handler_locked(d->irq, handle_edge_irq);
1463 __irq_set_handler_locked(d->irq, handle_level_irq);
1467 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1468 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1471 case IRQ_TYPE_EDGE_BOTH:
1472 bank->toggle_edge_mode |= mask;
1476 * Determine gpio state. If 1 next interrupt should be falling
1479 data = readl(bank->reg_base + GPIO_EXT_PORT);
1485 case IRQ_TYPE_EDGE_RISING:
1486 bank->toggle_edge_mode &= ~mask;
1490 case IRQ_TYPE_EDGE_FALLING:
1491 bank->toggle_edge_mode &= ~mask;
1495 case IRQ_TYPE_LEVEL_HIGH:
1496 bank->toggle_edge_mode &= ~mask;
1500 case IRQ_TYPE_LEVEL_LOW:
1501 bank->toggle_edge_mode &= ~mask;
1510 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1511 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1518 static int rockchip_interrupts_register(struct platform_device *pdev,
1519 struct rockchip_pinctrl *info)
1521 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1522 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1523 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1524 struct irq_chip_generic *gc;
1528 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1530 dev_warn(&pdev->dev, "bank %s is not valid\n",
1535 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1536 &irq_generic_chip_ops, NULL);
1537 if (!bank->domain) {
1538 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1543 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1544 "rockchip_gpio_irq", handle_level_irq,
1545 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1547 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1549 irq_domain_remove(bank->domain);
1553 gc = irq_get_domain_generic_chip(bank->domain, 0);
1554 gc->reg_base = bank->reg_base;
1556 gc->chip_types[0].regs.mask = GPIO_INTEN;
1557 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1558 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1559 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1560 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1561 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1562 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1564 irq_set_handler_data(bank->irq, bank);
1565 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1571 static int rockchip_gpiolib_register(struct platform_device *pdev,
1572 struct rockchip_pinctrl *info)
1574 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1575 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1576 struct gpio_chip *gc;
1580 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1582 dev_warn(&pdev->dev, "bank %s is not valid\n",
1587 bank->gpio_chip = rockchip_gpiolib_chip;
1589 gc = &bank->gpio_chip;
1590 gc->base = bank->pin_base;
1591 gc->ngpio = bank->nr_pins;
1592 gc->dev = &pdev->dev;
1593 gc->of_node = bank->of_node;
1594 gc->label = bank->name;
1596 ret = gpiochip_add(gc);
1598 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1604 rockchip_interrupts_register(pdev, info);
1609 for (--i, --bank; i >= 0; --i, --bank) {
1612 gpiochip_remove(&bank->gpio_chip);
1617 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1618 struct rockchip_pinctrl *info)
1620 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1621 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1624 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1627 gpiochip_remove(&bank->gpio_chip);
1633 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1634 struct rockchip_pinctrl *info)
1636 struct resource res;
1639 if (of_address_to_resource(bank->of_node, 0, &res)) {
1640 dev_err(info->dev, "cannot find IO resource for bank\n");
1644 bank->reg_base = devm_ioremap_resource(info->dev, &res);
1645 if (IS_ERR(bank->reg_base))
1646 return PTR_ERR(bank->reg_base);
1649 * special case, where parts of the pull setting-registers are
1650 * part of the PMU register space
1652 if (of_device_is_compatible(bank->of_node,
1653 "rockchip,rk3188-gpio-bank0")) {
1654 struct device_node *node;
1656 node = of_parse_phandle(bank->of_node->parent,
1659 if (of_address_to_resource(bank->of_node, 1, &res)) {
1660 dev_err(info->dev, "cannot find IO resource for bank\n");
1664 base = devm_ioremap_resource(info->dev, &res);
1666 return PTR_ERR(base);
1667 rockchip_regmap_config.max_register =
1668 resource_size(&res) - 4;
1669 rockchip_regmap_config.name =
1670 "rockchip,rk3188-gpio-bank0-pull";
1671 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1673 &rockchip_regmap_config);
1677 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1679 bank->clk = of_clk_get(bank->of_node, 0);
1680 if (IS_ERR(bank->clk))
1681 return PTR_ERR(bank->clk);
1683 return clk_prepare_enable(bank->clk);
1686 static const struct of_device_id rockchip_pinctrl_dt_match[];
1688 /* retrieve the soc specific data */
1689 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1690 struct rockchip_pinctrl *d,
1691 struct platform_device *pdev)
1693 const struct of_device_id *match;
1694 struct device_node *node = pdev->dev.of_node;
1695 struct device_node *np;
1696 struct rockchip_pin_ctrl *ctrl;
1697 struct rockchip_pin_bank *bank;
1698 int grf_offs, pmu_offs, i, j;
1700 match = of_match_node(rockchip_pinctrl_dt_match, node);
1701 ctrl = (struct rockchip_pin_ctrl *)match->data;
1703 for_each_child_of_node(node, np) {
1704 if (!of_find_property(np, "gpio-controller", NULL))
1707 bank = ctrl->pin_banks;
1708 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1709 if (!strcmp(bank->name, np->name)) {
1712 if (!rockchip_get_bank_data(bank, d))
1720 grf_offs = ctrl->grf_mux_offset;
1721 pmu_offs = ctrl->pmu_mux_offset;
1722 bank = ctrl->pin_banks;
1723 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1726 spin_lock_init(&bank->slock);
1728 bank->pin_base = ctrl->nr_pins;
1729 ctrl->nr_pins += bank->nr_pins;
1731 /* calculate iomux offsets */
1732 for (j = 0; j < 4; j++) {
1733 struct rockchip_iomux *iom = &bank->iomux[j];
1736 if (bank_pins >= bank->nr_pins)
1739 /* preset offset value, set new start value */
1740 if (iom->offset >= 0) {
1741 if (iom->type & IOMUX_SOURCE_PMU)
1742 pmu_offs = iom->offset;
1744 grf_offs = iom->offset;
1745 } else { /* set current offset */
1746 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1747 pmu_offs : grf_offs;
1750 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1754 * Increase offset according to iomux width.
1755 * 4bit iomux'es are spread over two registers.
1757 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1758 if (iom->type & IOMUX_SOURCE_PMU)
1770 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1772 struct rockchip_pinctrl *info;
1773 struct device *dev = &pdev->dev;
1774 struct rockchip_pin_ctrl *ctrl;
1775 struct device_node *np = pdev->dev.of_node, *node;
1776 struct resource *res;
1780 if (!dev->of_node) {
1781 dev_err(dev, "device tree node not found\n");
1785 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1791 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1793 dev_err(dev, "driver data not available\n");
1798 node = of_parse_phandle(np, "rockchip,grf", 0);
1800 info->regmap_base = syscon_node_to_regmap(node);
1801 if (IS_ERR(info->regmap_base))
1802 return PTR_ERR(info->regmap_base);
1804 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1805 base = devm_ioremap_resource(&pdev->dev, res);
1807 return PTR_ERR(base);
1809 rockchip_regmap_config.max_register = resource_size(res) - 4;
1810 rockchip_regmap_config.name = "rockchip,pinctrl";
1811 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
1812 &rockchip_regmap_config);
1814 /* to check for the old dt-bindings */
1815 info->reg_size = resource_size(res);
1817 /* Honor the old binding, with pull registers as 2nd resource */
1818 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1819 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1820 base = devm_ioremap_resource(&pdev->dev, res);
1822 return PTR_ERR(base);
1824 rockchip_regmap_config.max_register =
1825 resource_size(res) - 4;
1826 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
1827 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
1829 &rockchip_regmap_config);
1833 /* try to find the optional reference to the pmu syscon */
1834 node = of_parse_phandle(np, "rockchip,pmu", 0);
1836 info->regmap_pmu = syscon_node_to_regmap(node);
1837 if (IS_ERR(info->regmap_pmu))
1838 return PTR_ERR(info->regmap_pmu);
1841 ret = rockchip_gpiolib_register(pdev, info);
1845 ret = rockchip_pinctrl_register(pdev, info);
1847 rockchip_gpiolib_unregister(pdev, info);
1851 platform_set_drvdata(pdev, info);
1856 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1857 PIN_BANK(0, 32, "gpio0"),
1858 PIN_BANK(1, 32, "gpio1"),
1859 PIN_BANK(2, 32, "gpio2"),
1860 PIN_BANK(3, 32, "gpio3"),
1863 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1864 .pin_banks = rk2928_pin_banks,
1865 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1866 .label = "RK2928-GPIO",
1868 .grf_mux_offset = 0xa8,
1869 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1872 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1873 PIN_BANK(0, 32, "gpio0"),
1874 PIN_BANK(1, 32, "gpio1"),
1875 PIN_BANK(2, 32, "gpio2"),
1876 PIN_BANK(3, 32, "gpio3"),
1877 PIN_BANK(4, 32, "gpio4"),
1878 PIN_BANK(6, 16, "gpio6"),
1881 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1882 .pin_banks = rk3066a_pin_banks,
1883 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1884 .label = "RK3066a-GPIO",
1886 .grf_mux_offset = 0xa8,
1887 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1890 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1891 PIN_BANK(0, 32, "gpio0"),
1892 PIN_BANK(1, 32, "gpio1"),
1893 PIN_BANK(2, 32, "gpio2"),
1894 PIN_BANK(3, 32, "gpio3"),
1897 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1898 .pin_banks = rk3066b_pin_banks,
1899 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1900 .label = "RK3066b-GPIO",
1902 .grf_mux_offset = 0x60,
1905 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1906 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
1907 PIN_BANK(1, 32, "gpio1"),
1908 PIN_BANK(2, 32, "gpio2"),
1909 PIN_BANK(3, 32, "gpio3"),
1912 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1913 .pin_banks = rk3188_pin_banks,
1914 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1915 .label = "RK3188-GPIO",
1917 .grf_mux_offset = 0x60,
1918 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
1921 static struct rockchip_pin_bank rk3288_pin_banks[] = {
1922 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
1927 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
1932 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
1933 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
1934 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
1939 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
1944 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
1945 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
1950 PIN_BANK(8, 16, "gpio8"),
1953 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
1954 .pin_banks = rk3288_pin_banks,
1955 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
1956 .label = "RK3288-GPIO",
1958 .grf_mux_offset = 0x0,
1959 .pmu_mux_offset = 0x84,
1960 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
1963 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1964 { .compatible = "rockchip,rk2928-pinctrl",
1965 .data = (void *)&rk2928_pin_ctrl },
1966 { .compatible = "rockchip,rk3066a-pinctrl",
1967 .data = (void *)&rk3066a_pin_ctrl },
1968 { .compatible = "rockchip,rk3066b-pinctrl",
1969 .data = (void *)&rk3066b_pin_ctrl },
1970 { .compatible = "rockchip,rk3188-pinctrl",
1971 .data = (void *)&rk3188_pin_ctrl },
1972 { .compatible = "rockchip,rk3288-pinctrl",
1973 .data = (void *)&rk3288_pin_ctrl },
1976 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1978 static struct platform_driver rockchip_pinctrl_driver = {
1979 .probe = rockchip_pinctrl_probe,
1981 .name = "rockchip-pinctrl",
1982 .owner = THIS_MODULE,
1983 .of_match_table = rockchip_pinctrl_dt_match,
1987 static int __init rockchip_pinctrl_drv_register(void)
1989 return platform_driver_register(&rockchip_pinctrl_driver);
1991 postcore_initcall(rockchip_pinctrl_drv_register);
1993 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1994 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1995 MODULE_LICENSE("GPL v2");