2 * S3C24XX specific support for Samsung pinctrl/gpiolib driver.
4 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This file contains the SamsungS3C24XX specific information required by the
12 * Samsung pinctrl/gpiolib driver. It also includes the implementation of
13 * external gpio and wakeup interrupt support.
16 #include <linux/module.h>
17 #include <linux/device.h>
18 #include <linux/interrupt.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irq.h>
21 #include <linux/of_irq.h>
23 #include <linux/slab.h>
24 #include <linux/err.h>
26 #include <asm/mach/irq.h>
28 #include "pinctrl-samsung.h"
31 #define NUM_EINT_IRQ 6
32 #define EINT_MAX_PER_GROUP 8
34 #define EINTPEND_REG 0xa8
35 #define EINTMASK_REG 0xa4
37 #define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP))
38 #define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88)
39 #define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4)
41 #define EINT_LEVEL_LOW 0
42 #define EINT_LEVEL_HIGH 1
43 #define EINT_EDGE_FALLING 2
44 #define EINT_EDGE_RISING 4
45 #define EINT_EDGE_BOTH 6
48 static struct samsung_pin_bank_type bank_type_1bit = {
49 .fld_width = { 1, 1, },
50 .reg_offset = { 0x00, 0x04, },
53 static struct samsung_pin_bank_type bank_type_2bit = {
54 .fld_width = { 2, 1, 2, },
55 .reg_offset = { 0x00, 0x04, 0x08, },
58 #define PIN_BANK_A(pins, reg, id) \
60 .type = &bank_type_1bit, \
63 .eint_type = EINT_TYPE_NONE, \
67 #define PIN_BANK_2BIT(pins, reg, id) \
69 .type = &bank_type_2bit, \
72 .eint_type = EINT_TYPE_NONE, \
76 #define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\
78 .type = &bank_type_2bit, \
81 .eint_type = EINT_TYPE_WKUP, \
84 .eint_offset = eoffs, \
89 * struct s3c24xx_eint_data: EINT common data
90 * @drvdata: pin controller driver data
91 * @domains: IRQ domains of particular EINT interrupts
92 * @parents: mapped parent irqs in the main interrupt controller
94 struct s3c24xx_eint_data {
95 struct samsung_pinctrl_drv_data *drvdata;
96 struct irq_domain *domains[NUM_EINT];
97 int parents[NUM_EINT_IRQ];
101 * struct s3c24xx_eint_domain_data: per irq-domain data
102 * @bank: pin bank related to the domain
103 * @eint_data: common data
104 * eint0_3_parent_only: live eints 0-3 only in the main intc
106 struct s3c24xx_eint_domain_data {
107 struct samsung_pin_bank *bank;
108 struct s3c24xx_eint_data *eint_data;
109 bool eint0_3_parent_only;
112 static int s3c24xx_eint_get_trigger(unsigned int type)
115 case IRQ_TYPE_EDGE_RISING:
116 return EINT_EDGE_RISING;
118 case IRQ_TYPE_EDGE_FALLING:
119 return EINT_EDGE_FALLING;
121 case IRQ_TYPE_EDGE_BOTH:
122 return EINT_EDGE_BOTH;
124 case IRQ_TYPE_LEVEL_HIGH:
125 return EINT_LEVEL_HIGH;
127 case IRQ_TYPE_LEVEL_LOW:
128 return EINT_LEVEL_LOW;
135 static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type)
137 /* Edge- and level-triggered interrupts need different handlers */
138 if (type & IRQ_TYPE_EDGE_BOTH)
139 __irq_set_handler_locked(irq, handle_edge_irq);
141 __irq_set_handler_locked(irq, handle_level_irq);
144 static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
145 struct samsung_pin_bank *bank, int pin)
147 struct samsung_pin_bank_type *bank_type = bank->type;
154 /* Make sure that pin is configured as interrupt */
155 reg = d->virt_base + bank->pctl_offset;
156 shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
157 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
159 spin_lock_irqsave(&bank->slock, flags);
162 val &= ~(mask << shift);
163 val |= bank->eint_func << shift;
166 spin_unlock_irqrestore(&bank->slock, flags);
169 static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
171 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
172 struct samsung_pinctrl_drv_data *d = bank->drvdata;
173 int index = bank->eint_offset + data->hwirq;
179 trigger = s3c24xx_eint_get_trigger(type);
181 dev_err(d->dev, "unsupported external interrupt type\n");
185 s3c24xx_eint_set_handler(data->irq, type);
187 /* Set up interrupt trigger */
188 reg = d->virt_base + EINT_REG(index);
189 shift = EINT_OFFS(index);
192 val &= ~(EINT_MASK << shift);
193 val |= trigger << shift;
196 s3c24xx_eint_set_function(d, bank, data->hwirq);
201 /* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */
203 static void s3c2410_eint0_3_ack(struct irq_data *data)
205 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
206 struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
207 struct s3c24xx_eint_data *eint_data = ddata->eint_data;
208 int parent_irq = eint_data->parents[data->hwirq];
209 struct irq_chip *parent_chip = irq_get_chip(parent_irq);
211 parent_chip->irq_ack(irq_get_irq_data(parent_irq));
214 static void s3c2410_eint0_3_mask(struct irq_data *data)
216 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
217 struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
218 struct s3c24xx_eint_data *eint_data = ddata->eint_data;
219 int parent_irq = eint_data->parents[data->hwirq];
220 struct irq_chip *parent_chip = irq_get_chip(parent_irq);
222 parent_chip->irq_mask(irq_get_irq_data(parent_irq));
225 static void s3c2410_eint0_3_unmask(struct irq_data *data)
227 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
228 struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
229 struct s3c24xx_eint_data *eint_data = ddata->eint_data;
230 int parent_irq = eint_data->parents[data->hwirq];
231 struct irq_chip *parent_chip = irq_get_chip(parent_irq);
233 parent_chip->irq_unmask(irq_get_irq_data(parent_irq));
236 static struct irq_chip s3c2410_eint0_3_chip = {
237 .name = "s3c2410-eint0_3",
238 .irq_ack = s3c2410_eint0_3_ack,
239 .irq_mask = s3c2410_eint0_3_mask,
240 .irq_unmask = s3c2410_eint0_3_unmask,
241 .irq_set_type = s3c24xx_eint_type,
244 static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
246 struct irq_data *data = irq_desc_get_irq_data(desc);
247 struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq);
250 /* the first 4 eints have a simple 1 to 1 mapping */
251 virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
252 /* Something must be really wrong if an unmapped EINT is unmasked */
255 generic_handle_irq(virq);
258 /* Handling of EINTs 0-3 on S3C2412 and S3C2413 */
260 static void s3c2412_eint0_3_ack(struct irq_data *data)
262 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
263 struct samsung_pinctrl_drv_data *d = bank->drvdata;
265 unsigned long bitval = 1UL << data->hwirq;
266 writel(bitval, d->virt_base + EINTPEND_REG);
269 static void s3c2412_eint0_3_mask(struct irq_data *data)
271 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
272 struct samsung_pinctrl_drv_data *d = bank->drvdata;
275 mask = readl(d->virt_base + EINTMASK_REG);
276 mask |= (1UL << data->hwirq);
277 writel(mask, d->virt_base + EINTMASK_REG);
280 static void s3c2412_eint0_3_unmask(struct irq_data *data)
282 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
283 struct samsung_pinctrl_drv_data *d = bank->drvdata;
286 mask = readl(d->virt_base + EINTMASK_REG);
287 mask &= ~(1UL << data->hwirq);
288 writel(mask, d->virt_base + EINTMASK_REG);
291 static struct irq_chip s3c2412_eint0_3_chip = {
292 .name = "s3c2412-eint0_3",
293 .irq_ack = s3c2412_eint0_3_ack,
294 .irq_mask = s3c2412_eint0_3_mask,
295 .irq_unmask = s3c2412_eint0_3_unmask,
296 .irq_set_type = s3c24xx_eint_type,
299 static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
301 struct irq_chip *chip = irq_get_chip(irq);
302 struct irq_data *data = irq_desc_get_irq_data(desc);
303 struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq);
306 chained_irq_enter(chip, desc);
308 /* the first 4 eints have a simple 1 to 1 mapping */
309 virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
310 /* Something must be really wrong if an unmapped EINT is unmasked */
313 generic_handle_irq(virq);
315 chained_irq_exit(chip, desc);
318 /* Handling of all other eints */
320 static void s3c24xx_eint_ack(struct irq_data *data)
322 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
323 struct samsung_pinctrl_drv_data *d = bank->drvdata;
324 unsigned char index = bank->eint_offset + data->hwirq;
326 writel(1UL << index, d->virt_base + EINTPEND_REG);
329 static void s3c24xx_eint_mask(struct irq_data *data)
331 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
332 struct samsung_pinctrl_drv_data *d = bank->drvdata;
333 unsigned char index = bank->eint_offset + data->hwirq;
336 mask = readl(d->virt_base + EINTMASK_REG);
337 mask |= (1UL << index);
338 writel(mask, d->virt_base + EINTMASK_REG);
341 static void s3c24xx_eint_unmask(struct irq_data *data)
343 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
344 struct samsung_pinctrl_drv_data *d = bank->drvdata;
345 unsigned char index = bank->eint_offset + data->hwirq;
348 mask = readl(d->virt_base + EINTMASK_REG);
349 mask &= ~(1UL << index);
350 writel(mask, d->virt_base + EINTMASK_REG);
353 static struct irq_chip s3c24xx_eint_chip = {
355 .irq_ack = s3c24xx_eint_ack,
356 .irq_mask = s3c24xx_eint_mask,
357 .irq_unmask = s3c24xx_eint_unmask,
358 .irq_set_type = s3c24xx_eint_type,
361 static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc,
362 u32 offset, u32 range)
364 struct irq_chip *chip = irq_get_chip(irq);
365 struct s3c24xx_eint_data *data = irq_get_handler_data(irq);
366 struct samsung_pinctrl_drv_data *d = data->drvdata;
367 unsigned int pend, mask;
369 chained_irq_enter(chip, desc);
371 pend = readl(d->virt_base + EINTPEND_REG);
372 mask = readl(d->virt_base + EINTMASK_REG);
382 virq = irq_linear_revmap(data->domains[irq], irq - offset);
383 /* Something is really wrong if an unmapped EINT is unmasked */
386 generic_handle_irq(virq);
389 chained_irq_exit(chip, desc);
392 static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc)
394 s3c24xx_demux_eint(irq, desc, 0, 0xf0);
397 static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc)
399 s3c24xx_demux_eint(irq, desc, 8, 0xffff00);
402 static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = {
403 s3c2410_demux_eint0_3,
404 s3c2410_demux_eint0_3,
405 s3c2410_demux_eint0_3,
406 s3c2410_demux_eint0_3,
407 s3c24xx_demux_eint4_7,
408 s3c24xx_demux_eint8_23,
411 static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = {
412 s3c2412_demux_eint0_3,
413 s3c2412_demux_eint0_3,
414 s3c2412_demux_eint0_3,
415 s3c2412_demux_eint0_3,
416 s3c24xx_demux_eint4_7,
417 s3c24xx_demux_eint8_23,
420 static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq,
423 struct s3c24xx_eint_domain_data *ddata = h->host_data;
424 struct samsung_pin_bank *bank = ddata->bank;
426 if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
430 if (ddata->eint0_3_parent_only)
431 irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip,
434 irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip,
437 irq_set_chip_and_handler(virq, &s3c24xx_eint_chip,
440 irq_set_chip_data(virq, bank);
441 set_irq_flags(virq, IRQF_VALID);
445 static const struct irq_domain_ops s3c24xx_gpf_irq_ops = {
446 .map = s3c24xx_gpf_irq_map,
447 .xlate = irq_domain_xlate_twocell,
450 static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq,
453 struct s3c24xx_eint_domain_data *ddata = h->host_data;
454 struct samsung_pin_bank *bank = ddata->bank;
456 if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
459 irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq);
460 irq_set_chip_data(virq, bank);
461 set_irq_flags(virq, IRQF_VALID);
465 static const struct irq_domain_ops s3c24xx_gpg_irq_ops = {
466 .map = s3c24xx_gpg_irq_map,
467 .xlate = irq_domain_xlate_twocell,
470 static const struct of_device_id s3c24xx_eint_irq_ids[] = {
471 { .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 },
472 { .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 },
476 static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
478 struct device *dev = d->dev;
479 const struct of_device_id *match;
480 struct device_node *eint_np = NULL;
481 struct device_node *np;
482 struct samsung_pin_bank *bank;
483 struct s3c24xx_eint_data *eint_data;
484 const struct irq_domain_ops *ops;
486 bool eint0_3_parent_only;
487 irq_flow_handler_t *handlers;
489 for_each_child_of_node(dev->of_node, np) {
490 match = of_match_node(s3c24xx_eint_irq_ids, np);
493 eint0_3_parent_only = (bool)match->data;
500 eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL);
504 eint_data->drvdata = d;
506 handlers = eint0_3_parent_only ? s3c2410_eint_handlers
507 : s3c2412_eint_handlers;
508 for (i = 0; i < NUM_EINT_IRQ; ++i) {
511 irq = irq_of_parse_and_map(eint_np, i);
513 dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
517 eint_data->parents[i] = irq;
518 irq_set_chained_handler(irq, handlers[i]);
519 irq_set_handler_data(irq, eint_data);
522 bank = d->ctrl->pin_banks;
523 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
524 struct s3c24xx_eint_domain_data *ddata;
529 if (bank->eint_type != EINT_TYPE_WKUP)
532 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
537 ddata->eint_data = eint_data;
538 ddata->eint0_3_parent_only = eint0_3_parent_only;
540 ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops
541 : &s3c24xx_gpg_irq_ops;
543 bank->irq_domain = irq_domain_add_linear(bank->of_node,
544 bank->nr_pins, ops, ddata);
545 if (!bank->irq_domain) {
546 dev_err(dev, "wkup irq domain add failed\n");
550 irq = bank->eint_offset;
551 mask = bank->eint_mask;
552 for (pin = 0; mask; ++pin, mask >>= 1) {
557 eint_data->domains[irq] = bank->irq_domain;
565 static struct samsung_pin_bank s3c2412_pin_banks[] = {
566 PIN_BANK_A(23, 0x000, "gpa"),
567 PIN_BANK_2BIT(11, 0x010, "gpb"),
568 PIN_BANK_2BIT(16, 0x020, "gpc"),
569 PIN_BANK_2BIT(16, 0x030, "gpd"),
570 PIN_BANK_2BIT(16, 0x040, "gpe"),
571 PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
572 PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
573 PIN_BANK_2BIT(11, 0x070, "gph"),
574 PIN_BANK_2BIT(13, 0x080, "gpj"),
577 struct samsung_pin_ctrl s3c2412_pin_ctrl[] = {
579 .pin_banks = s3c2412_pin_banks,
580 .nr_banks = ARRAY_SIZE(s3c2412_pin_banks),
581 .eint_wkup_init = s3c24xx_eint_init,
582 .label = "S3C2412-GPIO",
586 static struct samsung_pin_bank s3c2416_pin_banks[] = {
587 PIN_BANK_A(27, 0x000, "gpa"),
588 PIN_BANK_2BIT(11, 0x010, "gpb"),
589 PIN_BANK_2BIT(16, 0x020, "gpc"),
590 PIN_BANK_2BIT(16, 0x030, "gpd"),
591 PIN_BANK_2BIT(16, 0x040, "gpe"),
592 PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
593 PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00),
594 PIN_BANK_2BIT(15, 0x070, "gph"),
595 PIN_BANK_2BIT(16, 0x0e0, "gpk"),
596 PIN_BANK_2BIT(14, 0x0f0, "gpl"),
597 PIN_BANK_2BIT(2, 0x100, "gpm"),
600 struct samsung_pin_ctrl s3c2416_pin_ctrl[] = {
602 .pin_banks = s3c2416_pin_banks,
603 .nr_banks = ARRAY_SIZE(s3c2416_pin_banks),
604 .eint_wkup_init = s3c24xx_eint_init,
605 .label = "S3C2416-GPIO",
609 static struct samsung_pin_bank s3c2440_pin_banks[] = {
610 PIN_BANK_A(25, 0x000, "gpa"),
611 PIN_BANK_2BIT(11, 0x010, "gpb"),
612 PIN_BANK_2BIT(16, 0x020, "gpc"),
613 PIN_BANK_2BIT(16, 0x030, "gpd"),
614 PIN_BANK_2BIT(16, 0x040, "gpe"),
615 PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
616 PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
617 PIN_BANK_2BIT(11, 0x070, "gph"),
618 PIN_BANK_2BIT(13, 0x0d0, "gpj"),
621 struct samsung_pin_ctrl s3c2440_pin_ctrl[] = {
623 .pin_banks = s3c2440_pin_banks,
624 .nr_banks = ARRAY_SIZE(s3c2440_pin_banks),
625 .eint_wkup_init = s3c24xx_eint_init,
626 .label = "S3C2440-GPIO",
630 static struct samsung_pin_bank s3c2450_pin_banks[] = {
631 PIN_BANK_A(28, 0x000, "gpa"),
632 PIN_BANK_2BIT(11, 0x010, "gpb"),
633 PIN_BANK_2BIT(16, 0x020, "gpc"),
634 PIN_BANK_2BIT(16, 0x030, "gpd"),
635 PIN_BANK_2BIT(16, 0x040, "gpe"),
636 PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
637 PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
638 PIN_BANK_2BIT(15, 0x070, "gph"),
639 PIN_BANK_2BIT(16, 0x0d0, "gpj"),
640 PIN_BANK_2BIT(16, 0x0e0, "gpk"),
641 PIN_BANK_2BIT(15, 0x0f0, "gpl"),
642 PIN_BANK_2BIT(2, 0x100, "gpm"),
645 struct samsung_pin_ctrl s3c2450_pin_ctrl[] = {
647 .pin_banks = s3c2450_pin_banks,
648 .nr_banks = ARRAY_SIZE(s3c2450_pin_banks),
649 .eint_wkup_init = s3c24xx_eint_init,
650 .label = "S3C2450-GPIO",