2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
5 * Copyright (C) 2012 Texas Instruments, Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/interrupt.h>
20 #include <linux/irqchip/chained_irq.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
36 #define DRIVER_NAME "pinctrl-single"
37 #define PCS_MUX_PINS_NAME "pinctrl-single,pins"
38 #define PCS_MUX_BITS_NAME "pinctrl-single,bits"
39 #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3)
40 #define PCS_OFF_DISABLED ~0U
43 * struct pcs_pingroup - pingroups for a function
44 * @np: pingroup device node pointer
45 * @name: pingroup name
46 * @gpins: array of the pins in the group
47 * @ngpins: number of pins in the group
51 struct device_node *np;
55 struct list_head node;
59 * struct pcs_func_vals - mux function register offset and value pair
60 * @reg: register virtual address
61 * @val: register value
63 struct pcs_func_vals {
70 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * and value, enable, disable, mask
72 * @param: config parameter
73 * @val: user input bits in the pinconf register
74 * @enable: enable bits in the pinconf register
75 * @disable: disable bits in the pinconf register
76 * @mask: mask bits in the register value
78 struct pcs_conf_vals {
79 enum pin_config_param param;
87 * struct pcs_conf_type - pinconf property name, pinconf param pair
88 * @name: property name in DTS file
89 * @param: config parameter
91 struct pcs_conf_type {
93 enum pin_config_param param;
97 * struct pcs_function - pinctrl function
98 * @name: pinctrl function name
99 * @vals: register and vals array
100 * @nvals: number of entries in vals array
101 * @pgnames: array of pingroup names the function uses
102 * @npgnames: number of pingroup names the function uses
105 struct pcs_function {
107 struct pcs_func_vals *vals;
109 const char **pgnames;
111 struct pcs_conf_vals *conf;
113 struct list_head node;
117 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
118 * @offset: offset base of pins
119 * @npins: number pins with the same mux value of gpio function
120 * @gpiofunc: mux value of gpio function
123 struct pcs_gpiofunc_range {
127 struct list_head node;
131 * struct pcs_data - wrapper for data needed by pinctrl framework
133 * @cur: index to current element
135 * REVISIT: We should be able to drop this eventually by adding
136 * support for registering pins individually in the pinctrl
137 * framework for those drivers that don't need a static array.
140 struct pinctrl_pin_desc *pa;
145 * struct pcs_name - register name for a pin
146 * @name: name of the pinctrl register
148 * REVISIT: We may want to make names optional in the pinctrl
149 * framework as some drivers may not care about pin names to
150 * avoid kernel bloat. The pin names can be deciphered by user
151 * space tools using debugfs based on the register address and
152 * SoC packaging information.
155 char name[PCS_REG_NAME_LEN];
159 * struct pcs_soc_data - SoC specific settings
160 * @flags: initial SoC specific PCS_FEAT_xxx values
161 * @irq: optional interrupt for the controller
162 * @irq_enable_mask: optional SoC specific interrupt enable mask
163 * @irq_status_mask: optional SoC specific interrupt status mask
164 * @rearm: optional SoC specific wake-up rearm function
166 struct pcs_soc_data {
169 unsigned irq_enable_mask;
170 unsigned irq_status_mask;
175 * struct pcs_device - pinctrl device instance
177 * @base: virtual address of the controller
178 * @size: size of the ioremapped area
180 * @pctl: pin controller device
181 * @flags: mask of PCS_FEAT_xxx values
182 * @lock: spinlock for register access
183 * @mutex: mutex protecting the lists
184 * @width: bits per mux register
185 * @fmask: function register mask
186 * @fshift: function register shift
187 * @foff: value to turn mux off
188 * @fmax: max number of functions in fmask
189 * @bits_per_pin:number of bits per pin
190 * @names: array of register names for pins
191 * @pins: physical pins on the SoC
192 * @pgtree: pingroup index radix tree
193 * @ftree: function index radix tree
194 * @pingroups: list of pingroups
195 * @functions: list of functions
196 * @gpiofuncs: list of gpio functions
197 * @irqs: list of interrupt registers
198 * @chip: chip container for this instance
199 * @domain: IRQ domain for this instance
200 * @ngroups: number of pingroups
201 * @nfuncs: number of functions
202 * @desc: pin controller descriptor
203 * @read: register read function to use
204 * @write: register write function to use
207 struct resource *res;
211 struct pinctrl_dev *pctl;
213 #define PCS_QUIRK_SHARED_IRQ (1 << 2)
214 #define PCS_FEAT_IRQ (1 << 1)
215 #define PCS_FEAT_PINCONF (1 << 0)
216 struct pcs_soc_data socdata;
225 unsigned bits_per_pin;
226 struct pcs_name *names;
227 struct pcs_data pins;
228 struct radix_tree_root pgtree;
229 struct radix_tree_root ftree;
230 struct list_head pingroups;
231 struct list_head functions;
232 struct list_head gpiofuncs;
233 struct list_head irqs;
234 struct irq_chip chip;
235 struct irq_domain *domain;
238 struct pinctrl_desc desc;
239 unsigned (*read)(void __iomem *reg);
240 void (*write)(unsigned val, void __iomem *reg);
243 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
244 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
245 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
247 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
248 unsigned long *config);
249 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
250 unsigned long *configs, unsigned num_configs);
252 static enum pin_config_param pcs_bias[] = {
253 PIN_CONFIG_BIAS_PULL_DOWN,
254 PIN_CONFIG_BIAS_PULL_UP,
258 * REVISIT: Reads and writes could eventually use regmap or something
259 * generic. But at least on omaps, some mux registers are performance
260 * critical as they may need to be remuxed every time before and after
261 * idle. Adding tests for register access width for every read and
262 * write like regmap is doing is not desired, and caching the registers
263 * does not help in this case.
266 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
271 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
276 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
281 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
286 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
291 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
296 static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
298 struct pcs_device *pcs;
300 pcs = pinctrl_dev_get_drvdata(pctldev);
305 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
308 struct pcs_device *pcs;
309 struct pcs_pingroup *group;
311 pcs = pinctrl_dev_get_drvdata(pctldev);
312 group = radix_tree_lookup(&pcs->pgtree, gselector);
314 dev_err(pcs->dev, "%s could not find pingroup%i\n",
315 __func__, gselector);
322 static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
324 const unsigned **pins,
327 struct pcs_device *pcs;
328 struct pcs_pingroup *group;
330 pcs = pinctrl_dev_get_drvdata(pctldev);
331 group = radix_tree_lookup(&pcs->pgtree, gselector);
333 dev_err(pcs->dev, "%s could not find pingroup%i\n",
334 __func__, gselector);
338 *pins = group->gpins;
339 *npins = group->ngpins;
344 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
348 struct pcs_device *pcs;
349 unsigned val, mux_bytes;
351 pcs = pinctrl_dev_get_drvdata(pctldev);
353 mux_bytes = pcs->width / BITS_PER_BYTE;
354 val = pcs->read(pcs->base + pin * mux_bytes);
356 seq_printf(s, "%08x %s " , val, DRIVER_NAME);
359 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
360 struct pinctrl_map *map, unsigned num_maps)
362 struct pcs_device *pcs;
364 pcs = pinctrl_dev_get_drvdata(pctldev);
365 devm_kfree(pcs->dev, map);
368 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
369 struct device_node *np_config,
370 struct pinctrl_map **map, unsigned *num_maps);
372 static const struct pinctrl_ops pcs_pinctrl_ops = {
373 .get_groups_count = pcs_get_groups_count,
374 .get_group_name = pcs_get_group_name,
375 .get_group_pins = pcs_get_group_pins,
376 .pin_dbg_show = pcs_pin_dbg_show,
377 .dt_node_to_map = pcs_dt_node_to_map,
378 .dt_free_map = pcs_dt_free_map,
381 static int pcs_get_functions_count(struct pinctrl_dev *pctldev)
383 struct pcs_device *pcs;
385 pcs = pinctrl_dev_get_drvdata(pctldev);
390 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev,
393 struct pcs_device *pcs;
394 struct pcs_function *func;
396 pcs = pinctrl_dev_get_drvdata(pctldev);
397 func = radix_tree_lookup(&pcs->ftree, fselector);
399 dev_err(pcs->dev, "%s could not find function%i\n",
400 __func__, fselector);
407 static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
409 const char * const **groups,
410 unsigned * const ngroups)
412 struct pcs_device *pcs;
413 struct pcs_function *func;
415 pcs = pinctrl_dev_get_drvdata(pctldev);
416 func = radix_tree_lookup(&pcs->ftree, fselector);
418 dev_err(pcs->dev, "%s could not find function%i\n",
419 __func__, fselector);
422 *groups = func->pgnames;
423 *ngroups = func->npgnames;
428 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
429 struct pcs_function **func)
431 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
432 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
433 const struct pinctrl_setting_mux *setting;
436 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
437 setting = pdesc->mux_setting;
440 fselector = setting->func;
441 *func = radix_tree_lookup(&pcs->ftree, fselector);
443 dev_err(pcs->dev, "%s could not find function%i\n",
444 __func__, fselector);
450 static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
453 struct pcs_device *pcs;
454 struct pcs_function *func;
457 pcs = pinctrl_dev_get_drvdata(pctldev);
458 /* If function mask is null, needn't enable it. */
461 func = radix_tree_lookup(&pcs->ftree, fselector);
465 dev_dbg(pcs->dev, "enabling %s function%i\n",
466 func->name, fselector);
468 for (i = 0; i < func->nvals; i++) {
469 struct pcs_func_vals *vals;
473 vals = &func->vals[i];
474 raw_spin_lock_irqsave(&pcs->lock, flags);
475 val = pcs->read(vals->reg);
477 if (pcs->bits_per_mux)
483 val |= (vals->val & mask);
484 pcs->write(val, vals->reg);
485 raw_spin_unlock_irqrestore(&pcs->lock, flags);
491 static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
494 struct pcs_device *pcs;
495 struct pcs_function *func;
498 pcs = pinctrl_dev_get_drvdata(pctldev);
499 /* If function mask is null, needn't disable it. */
503 func = radix_tree_lookup(&pcs->ftree, fselector);
505 dev_err(pcs->dev, "%s could not find function%i\n",
506 __func__, fselector);
511 * Ignore disable if function-off is not specified. Some hardware
512 * does not have clearly defined disable function. For pin specific
513 * off modes, you can use alternate named states as described in
514 * pinctrl-bindings.txt.
516 if (pcs->foff == PCS_OFF_DISABLED) {
517 dev_dbg(pcs->dev, "ignoring disable for %s function%i\n",
518 func->name, fselector);
522 dev_dbg(pcs->dev, "disabling function%i %s\n",
523 fselector, func->name);
525 for (i = 0; i < func->nvals; i++) {
526 struct pcs_func_vals *vals;
530 vals = &func->vals[i];
531 raw_spin_lock_irqsave(&pcs->lock, flags);
532 val = pcs->read(vals->reg);
534 val |= pcs->foff << pcs->fshift;
535 pcs->write(val, vals->reg);
536 raw_spin_unlock_irqrestore(&pcs->lock, flags);
540 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
541 struct pinctrl_gpio_range *range, unsigned pin)
543 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
544 struct pcs_gpiofunc_range *frange = NULL;
545 struct list_head *pos, *tmp;
549 /* If function mask is null, return directly. */
553 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
554 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
555 if (pin >= frange->offset + frange->npins
556 || pin < frange->offset)
558 mux_bytes = pcs->width / BITS_PER_BYTE;
559 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
560 data |= frange->gpiofunc;
561 pcs->write(data, pcs->base + pin * mux_bytes);
567 static const struct pinmux_ops pcs_pinmux_ops = {
568 .get_functions_count = pcs_get_functions_count,
569 .get_function_name = pcs_get_function_name,
570 .get_function_groups = pcs_get_function_groups,
571 .enable = pcs_enable,
572 .disable = pcs_disable,
573 .gpio_request_enable = pcs_request_gpio,
576 /* Clear BIAS value */
577 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
579 unsigned long config;
581 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
582 config = pinconf_to_config_packed(pcs_bias[i], 0);
583 pcs_pinconf_set(pctldev, pin, &config, 1);
588 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
589 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
591 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
593 unsigned long config;
596 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
597 config = pinconf_to_config_packed(pcs_bias[i], 0);
598 if (!pcs_pinconf_get(pctldev, pin, &config))
606 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
607 unsigned pin, unsigned long *config)
609 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
610 struct pcs_function *func;
611 enum pin_config_param param;
612 unsigned offset = 0, data = 0, i, j, ret;
614 ret = pcs_get_function(pctldev, pin, &func);
618 for (i = 0; i < func->nconfs; i++) {
619 param = pinconf_to_config_param(*config);
620 if (param == PIN_CONFIG_BIAS_DISABLE) {
621 if (pcs_pinconf_bias_disable(pctldev, pin)) {
627 } else if (param != func->conf[i].param) {
631 offset = pin * (pcs->width / BITS_PER_BYTE);
632 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
633 switch (func->conf[i].param) {
635 case PIN_CONFIG_BIAS_PULL_DOWN:
636 case PIN_CONFIG_BIAS_PULL_UP:
637 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
638 if ((data != func->conf[i].enable) ||
639 (data == func->conf[i].disable))
644 case PIN_CONFIG_INPUT_SCHMITT:
645 for (j = 0; j < func->nconfs; j++) {
646 switch (func->conf[j].param) {
647 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
648 if (data != func->conf[j].enable)
657 case PIN_CONFIG_DRIVE_STRENGTH:
658 case PIN_CONFIG_SLEW_RATE:
668 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
669 unsigned pin, unsigned long *configs,
670 unsigned num_configs)
672 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
673 struct pcs_function *func;
674 unsigned offset = 0, shift = 0, i, data, ret;
678 ret = pcs_get_function(pctldev, pin, &func);
682 for (j = 0; j < num_configs; j++) {
683 for (i = 0; i < func->nconfs; i++) {
684 if (pinconf_to_config_param(configs[j])
685 != func->conf[i].param)
688 offset = pin * (pcs->width / BITS_PER_BYTE);
689 data = pcs->read(pcs->base + offset);
690 arg = pinconf_to_config_argument(configs[j]);
691 switch (func->conf[i].param) {
693 case PIN_CONFIG_INPUT_SCHMITT:
694 case PIN_CONFIG_DRIVE_STRENGTH:
695 case PIN_CONFIG_SLEW_RATE:
696 shift = ffs(func->conf[i].mask) - 1;
697 data &= ~func->conf[i].mask;
698 data |= (arg << shift) & func->conf[i].mask;
701 case PIN_CONFIG_BIAS_DISABLE:
702 pcs_pinconf_clear_bias(pctldev, pin);
704 case PIN_CONFIG_BIAS_PULL_DOWN:
705 case PIN_CONFIG_BIAS_PULL_UP:
707 pcs_pinconf_clear_bias(pctldev, pin);
709 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
710 data &= ~func->conf[i].mask;
712 data |= func->conf[i].enable;
714 data |= func->conf[i].disable;
719 pcs->write(data, pcs->base + offset);
723 if (i >= func->nconfs)
725 } /* for each config */
730 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
731 unsigned group, unsigned long *config)
733 const unsigned *pins;
734 unsigned npins, old = 0;
737 ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
740 for (i = 0; i < npins; i++) {
741 if (pcs_pinconf_get(pctldev, pins[i], config))
743 /* configs do not match between two pins */
744 if (i && (old != *config))
751 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
752 unsigned group, unsigned long *configs,
753 unsigned num_configs)
755 const unsigned *pins;
759 ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
762 for (i = 0; i < npins; i++) {
763 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
769 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
770 struct seq_file *s, unsigned pin)
774 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
775 struct seq_file *s, unsigned selector)
779 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
781 unsigned long config)
783 pinconf_generic_dump_config(pctldev, s, config);
786 static const struct pinconf_ops pcs_pinconf_ops = {
787 .pin_config_get = pcs_pinconf_get,
788 .pin_config_set = pcs_pinconf_set,
789 .pin_config_group_get = pcs_pinconf_group_get,
790 .pin_config_group_set = pcs_pinconf_group_set,
791 .pin_config_dbg_show = pcs_pinconf_dbg_show,
792 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
793 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
798 * pcs_add_pin() - add a pin to the static per controller pin array
799 * @pcs: pcs driver instance
800 * @offset: register offset from base
802 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
805 struct pinctrl_pin_desc *pin;
810 if (i >= pcs->desc.npins) {
811 dev_err(pcs->dev, "too many pins, max %i\n",
816 pin = &pcs->pins.pa[i];
818 sprintf(pn->name, "%lx.%d",
819 (unsigned long)pcs->res->start + offset, pin_pos);
820 pin->name = pn->name;
828 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
829 * @pcs: pcs driver instance
831 * In case of errors, resources are freed in pcs_free_resources.
833 * If your hardware needs holes in the address space, then just set
834 * up multiple driver instances.
836 static int pcs_allocate_pin_table(struct pcs_device *pcs)
838 int mux_bytes, nr_pins, i;
839 int num_pins_in_register = 0;
841 mux_bytes = pcs->width / BITS_PER_BYTE;
843 if (pcs->bits_per_mux) {
844 pcs->bits_per_pin = fls(pcs->fmask);
845 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
846 num_pins_in_register = pcs->width / pcs->bits_per_pin;
848 nr_pins = pcs->size / mux_bytes;
851 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
852 pcs->pins.pa = devm_kzalloc(pcs->dev,
853 sizeof(*pcs->pins.pa) * nr_pins,
858 pcs->names = devm_kzalloc(pcs->dev,
859 sizeof(struct pcs_name) * nr_pins,
864 pcs->desc.pins = pcs->pins.pa;
865 pcs->desc.npins = nr_pins;
867 for (i = 0; i < pcs->desc.npins; i++) {
873 if (pcs->bits_per_mux) {
874 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
875 offset = (byte_num / mux_bytes) * mux_bytes;
876 pin_pos = i % num_pins_in_register;
878 offset = i * mux_bytes;
880 res = pcs_add_pin(pcs, offset, pin_pos);
882 dev_err(pcs->dev, "error adding pins: %i\n", res);
891 * pcs_add_function() - adds a new function to the function list
892 * @pcs: pcs driver instance
893 * @np: device node of the mux entry
894 * @name: name of the function
895 * @vals: array of mux register value pairs used by the function
896 * @nvals: number of mux register value pairs
897 * @pgnames: array of pingroup names for the function
898 * @npgnames: number of pingroup names
900 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
901 struct device_node *np,
903 struct pcs_func_vals *vals,
905 const char **pgnames,
908 struct pcs_function *function;
910 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
914 function->name = name;
915 function->vals = vals;
916 function->nvals = nvals;
917 function->pgnames = pgnames;
918 function->npgnames = npgnames;
920 mutex_lock(&pcs->mutex);
921 list_add_tail(&function->node, &pcs->functions);
922 radix_tree_insert(&pcs->ftree, pcs->nfuncs, function);
924 mutex_unlock(&pcs->mutex);
929 static void pcs_remove_function(struct pcs_device *pcs,
930 struct pcs_function *function)
934 mutex_lock(&pcs->mutex);
935 for (i = 0; i < pcs->nfuncs; i++) {
936 struct pcs_function *found;
938 found = radix_tree_lookup(&pcs->ftree, i);
939 if (found == function)
940 radix_tree_delete(&pcs->ftree, i);
942 list_del(&function->node);
943 mutex_unlock(&pcs->mutex);
947 * pcs_add_pingroup() - add a pingroup to the pingroup list
948 * @pcs: pcs driver instance
949 * @np: device node of the mux entry
950 * @name: name of the pingroup
951 * @gpins: array of the pins that belong to the group
952 * @ngpins: number of pins in the group
954 static int pcs_add_pingroup(struct pcs_device *pcs,
955 struct device_node *np,
960 struct pcs_pingroup *pingroup;
962 pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL);
966 pingroup->name = name;
968 pingroup->gpins = gpins;
969 pingroup->ngpins = ngpins;
971 mutex_lock(&pcs->mutex);
972 list_add_tail(&pingroup->node, &pcs->pingroups);
973 radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup);
975 mutex_unlock(&pcs->mutex);
981 * pcs_get_pin_by_offset() - get a pin index based on the register offset
982 * @pcs: pcs driver instance
983 * @offset: register offset from the base
985 * Note that this is OK as long as the pins are in a static array.
987 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
991 if (offset >= pcs->size) {
992 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
997 if (pcs->bits_per_mux)
998 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
1000 index = offset / (pcs->width / BITS_PER_BYTE);
1006 * check whether data matches enable bits or disable bits
1007 * Return value: 1 for matching enable bits, 0 for matching disable bits,
1008 * and negative value for matching failure.
1010 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
1016 else if (data == disable)
1021 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
1022 unsigned value, unsigned enable, unsigned disable,
1025 (*conf)->param = param;
1026 (*conf)->val = value;
1027 (*conf)->enable = enable;
1028 (*conf)->disable = disable;
1029 (*conf)->mask = mask;
1033 static void add_setting(unsigned long **setting, enum pin_config_param param,
1036 **setting = pinconf_to_config_packed(param, arg);
1040 /* add pinconf setting with 2 parameters */
1041 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
1042 const char *name, enum pin_config_param param,
1043 struct pcs_conf_vals **conf, unsigned long **settings)
1045 unsigned value[2], shift;
1048 ret = of_property_read_u32_array(np, name, value, 2);
1051 /* set value & mask */
1052 value[0] &= value[1];
1053 shift = ffs(value[1]) - 1;
1054 /* skip enable & disable */
1055 add_config(conf, param, value[0], 0, 0, value[1]);
1056 add_setting(settings, param, value[0] >> shift);
1059 /* add pinconf setting with 4 parameters */
1060 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
1061 const char *name, enum pin_config_param param,
1062 struct pcs_conf_vals **conf, unsigned long **settings)
1067 /* value to set, enable, disable, mask */
1068 ret = of_property_read_u32_array(np, name, value, 4);
1072 dev_err(pcs->dev, "mask field of the property can't be 0\n");
1075 value[0] &= value[3];
1076 value[1] &= value[3];
1077 value[2] &= value[3];
1078 ret = pcs_config_match(value[0], value[1], value[2]);
1080 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
1081 add_config(conf, param, value[0], value[1], value[2], value[3]);
1082 add_setting(settings, param, ret);
1085 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1086 struct pcs_function *func,
1087 struct pinctrl_map **map)
1090 struct pinctrl_map *m = *map;
1091 int i = 0, nconfs = 0;
1092 unsigned long *settings = NULL, *s = NULL;
1093 struct pcs_conf_vals *conf = NULL;
1094 struct pcs_conf_type prop2[] = {
1095 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
1096 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
1097 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
1099 struct pcs_conf_type prop4[] = {
1100 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
1101 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
1102 { "pinctrl-single,input-schmitt-enable",
1103 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
1106 /* If pinconf isn't supported, don't parse properties in below. */
1107 if (!PCS_HAS_PINCONF)
1110 /* cacluate how much properties are supported in current node */
1111 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
1112 if (of_find_property(np, prop2[i].name, NULL))
1115 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
1116 if (of_find_property(np, prop4[i].name, NULL))
1122 func->conf = devm_kzalloc(pcs->dev,
1123 sizeof(struct pcs_conf_vals) * nconfs,
1127 func->nconfs = nconfs;
1128 conf = &(func->conf[0]);
1130 settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
1136 for (i = 0; i < ARRAY_SIZE(prop2); i++)
1137 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
1139 for (i = 0; i < ARRAY_SIZE(prop4); i++)
1140 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
1142 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
1143 m->data.configs.group_or_pin = np->name;
1144 m->data.configs.configs = settings;
1145 m->data.configs.num_configs = nconfs;
1149 static void pcs_free_pingroups(struct pcs_device *pcs);
1152 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1153 * @pcs: pinctrl driver instance
1154 * @np: device node of the mux entry
1156 * @num_maps: number of map
1157 * @pgnames: pingroup names
1159 * Note that this binding currently supports only sets of one register + value.
1161 * Also note that this driver tries to avoid understanding pin and function
1162 * names because of the extra bloat they would cause especially in the case of
1163 * a large number of pins. This driver just sets what is specified for the board
1164 * in the .dts file. Further user space debugging tools can be developed to
1165 * decipher the pin and function names using debugfs.
1167 * If you are concerned about the boot time, set up the static pins in
1168 * the bootloader, and only set up selected pins as device tree entries.
1170 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1171 struct device_node *np,
1172 struct pinctrl_map **map,
1174 const char **pgnames)
1176 struct pcs_func_vals *vals;
1178 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1179 struct pcs_function *function;
1181 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
1182 if ((!mux) || (size < sizeof(*mux) * 2)) {
1183 dev_err(pcs->dev, "bad data for mux %s\n",
1188 size /= sizeof(*mux); /* Number of elements in array */
1191 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
1195 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
1199 while (index < size) {
1200 unsigned offset, val;
1203 offset = be32_to_cpup(mux + index++);
1204 val = be32_to_cpup(mux + index++);
1205 vals[found].reg = pcs->base + offset;
1206 vals[found].val = val;
1208 pin = pcs_get_pin_by_offset(pcs, offset);
1211 "could not add functions for %s %ux\n",
1215 pins[found++] = pin;
1218 pgnames[0] = np->name;
1219 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1223 res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1227 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1228 (*map)->data.mux.group = np->name;
1229 (*map)->data.mux.function = np->name;
1231 if (PCS_HAS_PINCONF) {
1232 res = pcs_parse_pinconf(pcs, np, function, map);
1234 goto free_pingroups;
1242 pcs_free_pingroups(pcs);
1245 pcs_remove_function(pcs, function);
1248 devm_kfree(pcs->dev, pins);
1251 devm_kfree(pcs->dev, vals);
1256 #define PARAMS_FOR_BITS_PER_MUX 3
1258 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1259 struct device_node *np,
1260 struct pinctrl_map **map,
1262 const char **pgnames)
1264 struct pcs_func_vals *vals;
1266 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1268 struct pcs_function *function;
1270 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
1273 dev_err(pcs->dev, "no valid property for %s\n", np->name);
1277 if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) {
1278 dev_err(pcs->dev, "bad data for %s\n", np->name);
1282 /* Number of elements in array */
1283 size /= sizeof(*mux);
1285 rows = size / PARAMS_FOR_BITS_PER_MUX;
1286 npins_in_row = pcs->width / pcs->bits_per_pin;
1288 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1293 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1298 while (index < size) {
1299 unsigned offset, val;
1300 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1301 unsigned pin_num_from_lsb;
1304 offset = be32_to_cpup(mux + index++);
1305 val = be32_to_cpup(mux + index++);
1306 mask = be32_to_cpup(mux + index++);
1308 /* Parse pins in each row from LSB */
1310 bit_pos = ffs(mask);
1311 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1312 mask_pos = ((pcs->fmask) << (bit_pos - 1));
1313 val_pos = val & mask_pos;
1314 submask = mask & mask_pos;
1317 if (submask != mask_pos) {
1319 "Invalid submask 0x%x for %s at 0x%x\n",
1320 submask, np->name, offset);
1324 vals[found].mask = submask;
1325 vals[found].reg = pcs->base + offset;
1326 vals[found].val = val_pos;
1328 pin = pcs_get_pin_by_offset(pcs, offset);
1331 "could not add functions for %s %ux\n",
1335 pins[found++] = pin + pin_num_from_lsb;
1339 pgnames[0] = np->name;
1340 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1344 res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1348 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1349 (*map)->data.mux.group = np->name;
1350 (*map)->data.mux.function = np->name;
1352 if (PCS_HAS_PINCONF) {
1353 dev_err(pcs->dev, "pinconf not supported\n");
1354 goto free_pingroups;
1361 pcs_free_pingroups(pcs);
1364 pcs_remove_function(pcs, function);
1367 devm_kfree(pcs->dev, pins);
1370 devm_kfree(pcs->dev, vals);
1375 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1376 * @pctldev: pinctrl instance
1377 * @np_config: device tree pinmux entry
1378 * @map: array of map entries
1379 * @num_maps: number of maps
1381 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1382 struct device_node *np_config,
1383 struct pinctrl_map **map, unsigned *num_maps)
1385 struct pcs_device *pcs;
1386 const char **pgnames;
1389 pcs = pinctrl_dev_get_drvdata(pctldev);
1391 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1392 *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1398 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1404 if (pcs->bits_per_mux) {
1405 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1408 dev_err(pcs->dev, "no pins entries for %s\n",
1413 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1416 dev_err(pcs->dev, "no pins entries for %s\n",
1425 devm_kfree(pcs->dev, pgnames);
1427 devm_kfree(pcs->dev, *map);
1433 * pcs_free_funcs() - free memory used by functions
1434 * @pcs: pcs driver instance
1436 static void pcs_free_funcs(struct pcs_device *pcs)
1438 struct list_head *pos, *tmp;
1441 mutex_lock(&pcs->mutex);
1442 for (i = 0; i < pcs->nfuncs; i++) {
1443 struct pcs_function *func;
1445 func = radix_tree_lookup(&pcs->ftree, i);
1448 radix_tree_delete(&pcs->ftree, i);
1450 list_for_each_safe(pos, tmp, &pcs->functions) {
1451 struct pcs_function *function;
1453 function = list_entry(pos, struct pcs_function, node);
1454 list_del(&function->node);
1456 mutex_unlock(&pcs->mutex);
1460 * pcs_free_pingroups() - free memory used by pingroups
1461 * @pcs: pcs driver instance
1463 static void pcs_free_pingroups(struct pcs_device *pcs)
1465 struct list_head *pos, *tmp;
1468 mutex_lock(&pcs->mutex);
1469 for (i = 0; i < pcs->ngroups; i++) {
1470 struct pcs_pingroup *pingroup;
1472 pingroup = radix_tree_lookup(&pcs->pgtree, i);
1475 radix_tree_delete(&pcs->pgtree, i);
1477 list_for_each_safe(pos, tmp, &pcs->pingroups) {
1478 struct pcs_pingroup *pingroup;
1480 pingroup = list_entry(pos, struct pcs_pingroup, node);
1481 list_del(&pingroup->node);
1483 mutex_unlock(&pcs->mutex);
1487 * pcs_irq_free() - free interrupt
1488 * @pcs: pcs driver instance
1490 static void pcs_irq_free(struct pcs_device *pcs)
1492 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1494 if (pcs_soc->irq < 0)
1498 irq_domain_remove(pcs->domain);
1500 if (PCS_QUIRK_HAS_SHARED_IRQ)
1501 free_irq(pcs_soc->irq, pcs_soc);
1503 irq_set_chained_handler(pcs_soc->irq, NULL);
1507 * pcs_free_resources() - free memory used by this driver
1508 * @pcs: pcs driver instance
1510 static void pcs_free_resources(struct pcs_device *pcs)
1515 pinctrl_unregister(pcs->pctl);
1517 pcs_free_funcs(pcs);
1518 pcs_free_pingroups(pcs);
1521 #define PCS_GET_PROP_U32(name, reg, err) \
1523 ret = of_property_read_u32(np, name, reg); \
1525 dev_err(pcs->dev, err); \
1530 static struct of_device_id pcs_of_match[];
1532 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1534 const char *propname = "pinctrl-single,gpio-range";
1535 const char *cellname = "#pinctrl-single,gpio-range-cells";
1536 struct of_phandle_args gpiospec;
1537 struct pcs_gpiofunc_range *range;
1540 for (i = 0; ; i++) {
1541 ret = of_parse_phandle_with_args(node, propname, cellname,
1543 /* Do not treat it as error. Only treat it as end condition. */
1548 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1553 range->offset = gpiospec.args[0];
1554 range->npins = gpiospec.args[1];
1555 range->gpiofunc = gpiospec.args[2];
1556 mutex_lock(&pcs->mutex);
1557 list_add_tail(&range->node, &pcs->gpiofuncs);
1558 mutex_unlock(&pcs->mutex);
1563 * @reg: virtual address of interrupt register
1564 * @hwirq: hardware irq number
1565 * @irq: virtual irq number
1568 struct pcs_interrupt {
1570 irq_hw_number_t hwirq;
1572 struct list_head node;
1576 * pcs_irq_set() - enables or disables an interrupt
1578 * Note that this currently assumes one interrupt per pinctrl
1579 * register that is typically used for wake-up events.
1581 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1582 int irq, const bool enable)
1584 struct pcs_device *pcs;
1585 struct list_head *pos;
1588 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1589 list_for_each(pos, &pcs->irqs) {
1590 struct pcs_interrupt *pcswi;
1593 pcswi = list_entry(pos, struct pcs_interrupt, node);
1594 if (irq != pcswi->irq)
1597 soc_mask = pcs_soc->irq_enable_mask;
1598 raw_spin_lock(&pcs->lock);
1599 mask = pcs->read(pcswi->reg);
1604 pcs->write(mask, pcswi->reg);
1605 raw_spin_unlock(&pcs->lock);
1613 * pcs_irq_mask() - mask pinctrl interrupt
1614 * @d: interrupt data
1616 static void pcs_irq_mask(struct irq_data *d)
1618 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1620 pcs_irq_set(pcs_soc, d->irq, false);
1624 * pcs_irq_unmask() - unmask pinctrl interrupt
1625 * @d: interrupt data
1627 static void pcs_irq_unmask(struct irq_data *d)
1629 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1631 pcs_irq_set(pcs_soc, d->irq, true);
1635 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1636 * @d: interrupt data
1637 * @state: wake-up state
1639 * Note that this should be called only for suspend and resume.
1640 * For runtime PM, the wake-up events should be enabled by default.
1642 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1653 * pcs_irq_handle() - common interrupt handler
1654 * @pcs_irq: interrupt data
1656 * Note that this currently assumes we have one interrupt bit per
1657 * mux register. This interrupt is typically used for wake-up events.
1658 * For more complex interrupts different handlers can be specified.
1660 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1662 struct pcs_device *pcs;
1663 struct list_head *pos;
1666 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1667 list_for_each(pos, &pcs->irqs) {
1668 struct pcs_interrupt *pcswi;
1671 pcswi = list_entry(pos, struct pcs_interrupt, node);
1672 raw_spin_lock(&pcs->lock);
1673 mask = pcs->read(pcswi->reg);
1674 raw_spin_unlock(&pcs->lock);
1675 if (mask & pcs_soc->irq_status_mask) {
1676 generic_handle_irq(irq_find_mapping(pcs->domain,
1686 * pcs_irq_handler() - handler for the shared interrupt case
1690 * Use this for cases where multiple instances of
1691 * pinctrl-single share a single interrupt like on omaps.
1693 static irqreturn_t pcs_irq_handler(int irq, void *d)
1695 struct pcs_soc_data *pcs_soc = d;
1697 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1701 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1703 * @desc: interrupt descriptor
1705 * Use this if you have a separate interrupt for each
1706 * pinctrl-single instance.
1708 static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
1710 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1711 struct irq_chip *chip;
1714 chip = irq_get_chip(irq);
1715 chained_irq_enter(chip, desc);
1716 res = pcs_irq_handle(pcs_soc);
1717 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1718 chained_irq_exit(chip, desc);
1723 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1724 irq_hw_number_t hwirq)
1726 struct pcs_soc_data *pcs_soc = d->host_data;
1727 struct pcs_device *pcs;
1728 struct pcs_interrupt *pcswi;
1730 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1731 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1735 pcswi->reg = pcs->base + hwirq;
1736 pcswi->hwirq = hwirq;
1739 mutex_lock(&pcs->mutex);
1740 list_add_tail(&pcswi->node, &pcs->irqs);
1741 mutex_unlock(&pcs->mutex);
1743 irq_set_chip_data(irq, pcs_soc);
1744 irq_set_chip_and_handler(irq, &pcs->chip,
1748 set_irq_flags(irq, IRQF_VALID);
1750 irq_set_noprobe(irq);
1756 static struct irq_domain_ops pcs_irqdomain_ops = {
1757 .map = pcs_irqdomain_map,
1758 .xlate = irq_domain_xlate_onecell,
1762 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1763 * @pcs: pcs driver instance
1764 * @np: device node pointer
1766 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1767 struct device_node *np)
1769 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1770 const char *name = "pinctrl";
1773 if (!pcs_soc->irq_enable_mask ||
1774 !pcs_soc->irq_status_mask) {
1779 INIT_LIST_HEAD(&pcs->irqs);
1780 pcs->chip.name = name;
1781 pcs->chip.irq_ack = pcs_irq_mask;
1782 pcs->chip.irq_mask = pcs_irq_mask;
1783 pcs->chip.irq_unmask = pcs_irq_unmask;
1784 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1786 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1789 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1790 IRQF_SHARED | IRQF_NO_SUSPEND,
1797 irq_set_handler_data(pcs_soc->irq, pcs_soc);
1798 irq_set_chained_handler(pcs_soc->irq,
1799 pcs_irq_chain_handler);
1803 * We can use the register offset as the hardirq
1804 * number as irq_domain_add_simple maps them lazily.
1805 * This way we can easily support more than one
1806 * interrupt per function if needed.
1808 num_irqs = pcs->size;
1810 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1814 irq_set_chained_handler(pcs_soc->irq, NULL);
1822 static int pinctrl_single_suspend(struct platform_device *pdev,
1825 struct pcs_device *pcs;
1827 pcs = platform_get_drvdata(pdev);
1831 return pinctrl_force_sleep(pcs->pctl);
1834 static int pinctrl_single_resume(struct platform_device *pdev)
1836 struct pcs_device *pcs;
1838 pcs = platform_get_drvdata(pdev);
1842 return pinctrl_force_default(pcs->pctl);
1846 static int pcs_probe(struct platform_device *pdev)
1848 struct device_node *np = pdev->dev.of_node;
1849 const struct of_device_id *match;
1850 struct pcs_pdata *pdata;
1851 struct resource *res;
1852 struct pcs_device *pcs;
1853 const struct pcs_soc_data *soc;
1856 match = of_match_device(pcs_of_match, &pdev->dev);
1860 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1862 dev_err(&pdev->dev, "could not allocate\n");
1865 pcs->dev = &pdev->dev;
1866 raw_spin_lock_init(&pcs->lock);
1867 mutex_init(&pcs->mutex);
1868 INIT_LIST_HEAD(&pcs->pingroups);
1869 INIT_LIST_HEAD(&pcs->functions);
1870 INIT_LIST_HEAD(&pcs->gpiofuncs);
1872 pcs->flags = soc->flags;
1873 memcpy(&pcs->socdata, soc, sizeof(*soc));
1875 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
1876 "register width not specified\n");
1878 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1881 pcs->fshift = ffs(pcs->fmask) - 1;
1882 pcs->fmax = pcs->fmask >> pcs->fshift;
1884 /* If mask property doesn't exist, function mux is invalid. */
1890 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1893 pcs->foff = PCS_OFF_DISABLED;
1895 pcs->bits_per_mux = of_property_read_bool(np,
1896 "pinctrl-single,bit-per-mux");
1898 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1900 dev_err(pcs->dev, "could not get resource\n");
1904 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1905 resource_size(res), DRIVER_NAME);
1907 dev_err(pcs->dev, "could not get mem_region\n");
1911 pcs->size = resource_size(pcs->res);
1912 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1914 dev_err(pcs->dev, "could not ioremap\n");
1918 INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL);
1919 INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL);
1920 platform_set_drvdata(pdev, pcs);
1922 switch (pcs->width) {
1924 pcs->read = pcs_readb;
1925 pcs->write = pcs_writeb;
1928 pcs->read = pcs_readw;
1929 pcs->write = pcs_writew;
1932 pcs->read = pcs_readl;
1933 pcs->write = pcs_writel;
1939 pcs->desc.name = DRIVER_NAME;
1940 pcs->desc.pctlops = &pcs_pinctrl_ops;
1941 pcs->desc.pmxops = &pcs_pinmux_ops;
1942 if (PCS_HAS_PINCONF)
1943 pcs->desc.confops = &pcs_pinconf_ops;
1944 pcs->desc.owner = THIS_MODULE;
1946 ret = pcs_allocate_pin_table(pcs);
1950 pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
1952 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1957 ret = pcs_add_gpio_func(np, pcs);
1961 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1962 if (pcs->socdata.irq)
1963 pcs->flags |= PCS_FEAT_IRQ;
1965 /* We still need auxdata for some omaps for PRM interrupts */
1966 pdata = dev_get_platdata(&pdev->dev);
1969 pcs->socdata.rearm = pdata->rearm;
1971 pcs->socdata.irq = pdata->irq;
1972 pcs->flags |= PCS_FEAT_IRQ;
1977 ret = pcs_irq_init_chained_handler(pcs, np);
1979 dev_warn(pcs->dev, "initialized with no interrupts\n");
1982 dev_info(pcs->dev, "%i pins at pa %p size %u\n",
1983 pcs->desc.npins, pcs->base, pcs->size);
1988 pcs_free_resources(pcs);
1993 static int pcs_remove(struct platform_device *pdev)
1995 struct pcs_device *pcs = platform_get_drvdata(pdev);
2000 pcs_free_resources(pcs);
2005 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
2006 .flags = PCS_QUIRK_SHARED_IRQ,
2007 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
2008 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
2011 static const struct pcs_soc_data pinctrl_single = {
2014 static const struct pcs_soc_data pinconf_single = {
2015 .flags = PCS_FEAT_PINCONF,
2018 static struct of_device_id pcs_of_match[] = {
2019 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
2020 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
2021 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
2022 { .compatible = "pinctrl-single", .data = &pinctrl_single },
2023 { .compatible = "pinconf-single", .data = &pinconf_single },
2026 MODULE_DEVICE_TABLE(of, pcs_of_match);
2028 static struct platform_driver pcs_driver = {
2030 .remove = pcs_remove,
2032 .owner = THIS_MODULE,
2033 .name = DRIVER_NAME,
2034 .of_match_table = pcs_of_match,
2037 .suspend = pinctrl_single_suspend,
2038 .resume = pinctrl_single_resume,
2042 module_platform_driver(pcs_driver);
2044 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
2045 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
2046 MODULE_LICENSE("GPL v2");