2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 #include <linux/delay.h>
16 #include <linux/module.h>
18 #include <linux/phy/phy.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/platform_device.h>
22 #include <linux/reset.h>
24 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
27 #include "pinctrl-utils.h"
29 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
30 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
31 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
32 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
34 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
35 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
36 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
37 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
39 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
40 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
41 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
42 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
44 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
45 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
46 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
47 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
48 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
49 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
51 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
52 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
53 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
55 struct tegra_xusb_padctl_function {
57 const char * const *groups;
58 unsigned int num_groups;
61 struct tegra_xusb_padctl_group {
62 const unsigned int *funcs;
63 unsigned int num_funcs;
66 struct tegra_xusb_padctl_soc {
67 const struct pinctrl_pin_desc *pins;
68 unsigned int num_pins;
70 const struct tegra_xusb_padctl_function *functions;
71 unsigned int num_functions;
73 const struct tegra_xusb_padctl_lane *lanes;
74 unsigned int num_lanes;
77 struct tegra_xusb_padctl_lane {
85 const unsigned int *funcs;
86 unsigned int num_funcs;
89 struct tegra_xusb_padctl {
93 struct reset_control *rst;
95 const struct tegra_xusb_padctl_soc *soc;
96 struct pinctrl_dev *pinctrl;
97 struct pinctrl_desc desc;
99 struct phy_provider *provider;
105 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
106 unsigned long offset)
108 writel(value, padctl->regs + offset);
111 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
112 unsigned long offset)
114 return readl(padctl->regs + offset);
117 static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
119 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
121 return padctl->soc->num_pins;
124 static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
127 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
129 return padctl->soc->pins[group].name;
132 enum tegra_xusb_padctl_param {
133 TEGRA_XUSB_PADCTL_IDDQ,
136 static const struct tegra_xusb_padctl_property {
138 enum tegra_xusb_padctl_param param;
140 { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
143 #define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
144 #define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
145 #define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
147 static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
148 struct device_node *np,
149 struct pinctrl_map **maps,
150 unsigned int *reserved_maps,
151 unsigned int *num_maps)
153 unsigned int i, reserve = 0, num_configs = 0;
154 unsigned long config, *configs = NULL;
155 const char *function, *group;
156 struct property *prop;
160 err = of_property_read_string(np, "nvidia,function", &function);
168 for (i = 0; i < ARRAY_SIZE(properties); i++) {
169 err = of_property_read_u32(np, properties[i].name, &value);
177 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
179 err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
180 &num_configs, config);
191 err = of_property_count_strings(np, "nvidia,lanes");
197 err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
202 of_property_for_each_string(np, "nvidia,lanes", prop, group) {
204 err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
205 reserved_maps, num_maps, group,
212 err = pinctrl_utils_add_map_configs(padctl->pinctrl,
213 maps, reserved_maps, num_maps, group,
214 configs, num_configs,
215 PIN_MAP_TYPE_CONFIGS_GROUP);
224 static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
225 struct device_node *parent,
226 struct pinctrl_map **maps,
227 unsigned int *num_maps)
229 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
230 unsigned int reserved_maps = 0;
231 struct device_node *np;
237 for_each_child_of_node(parent, np) {
238 err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
248 static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
249 .get_groups_count = tegra_xusb_padctl_get_groups_count,
250 .get_group_name = tegra_xusb_padctl_get_group_name,
251 .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
252 .dt_free_map = pinctrl_utils_dt_free_map,
255 static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
257 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
259 return padctl->soc->num_functions;
263 tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
264 unsigned int function)
266 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
268 return padctl->soc->functions[function].name;
271 static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
272 unsigned int function,
273 const char * const **groups,
274 unsigned * const num_groups)
276 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
278 *num_groups = padctl->soc->functions[function].num_groups;
279 *groups = padctl->soc->functions[function].groups;
284 static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
285 unsigned int function,
288 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
289 const struct tegra_xusb_padctl_lane *lane;
293 lane = &padctl->soc->lanes[group];
295 for (i = 0; i < lane->num_funcs; i++)
296 if (lane->funcs[i] == function)
299 if (i >= lane->num_funcs)
302 value = padctl_readl(padctl, lane->offset);
303 value &= ~(lane->mask << lane->shift);
304 value |= i << lane->shift;
305 padctl_writel(padctl, value, lane->offset);
310 static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
311 .get_functions_count = tegra_xusb_padctl_get_functions_count,
312 .get_function_name = tegra_xusb_padctl_get_function_name,
313 .get_function_groups = tegra_xusb_padctl_get_function_groups,
314 .set_mux = tegra_xusb_padctl_pinmux_set,
317 static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
319 unsigned long *config)
321 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
322 const struct tegra_xusb_padctl_lane *lane;
323 enum tegra_xusb_padctl_param param;
326 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
327 lane = &padctl->soc->lanes[group];
330 case TEGRA_XUSB_PADCTL_IDDQ:
331 /* lanes with iddq == 0 don't support this parameter */
335 value = padctl_readl(padctl, lane->offset);
337 if (value & BIT(lane->iddq))
342 *config = TEGRA_XUSB_PADCTL_PACK(param, value);
346 dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
354 static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
356 unsigned long *configs,
357 unsigned int num_configs)
359 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
360 const struct tegra_xusb_padctl_lane *lane;
361 enum tegra_xusb_padctl_param param;
366 lane = &padctl->soc->lanes[group];
368 for (i = 0; i < num_configs; i++) {
369 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
370 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
373 case TEGRA_XUSB_PADCTL_IDDQ:
374 /* lanes with iddq == 0 don't support this parameter */
378 regval = padctl_readl(padctl, lane->offset);
381 regval &= ~BIT(lane->iddq);
383 regval |= BIT(lane->iddq);
385 padctl_writel(padctl, regval, lane->offset);
390 "invalid configuration parameter: %04x\n",
399 #ifdef CONFIG_DEBUG_FS
400 static const char *strip_prefix(const char *s)
402 const char *comma = strchr(s, ',');
410 tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
416 for (i = 0; i < ARRAY_SIZE(properties); i++) {
417 unsigned long config, value;
420 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
422 err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
427 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
429 seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
435 tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
437 unsigned long config)
439 enum tegra_xusb_padctl_param param;
440 const char *name = "unknown";
444 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
445 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
447 for (i = 0; i < ARRAY_SIZE(properties); i++) {
448 if (properties[i].param == param) {
449 name = properties[i].name;
454 seq_printf(s, "%s=%lu", strip_prefix(name), value);
458 static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
459 .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
460 .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
461 #ifdef CONFIG_DEBUG_FS
462 .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
463 .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
467 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
471 mutex_lock(&padctl->lock);
473 if (padctl->enable++ > 0)
476 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
477 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
478 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
480 usleep_range(100, 200);
482 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
483 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
484 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
486 usleep_range(100, 200);
488 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
489 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
490 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
493 mutex_unlock(&padctl->lock);
497 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
501 mutex_lock(&padctl->lock);
503 if (WARN_ON(padctl->enable == 0))
506 if (--padctl->enable > 0)
509 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
510 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
511 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
513 usleep_range(100, 200);
515 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
516 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
517 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
519 usleep_range(100, 200);
521 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
522 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
523 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
526 mutex_unlock(&padctl->lock);
530 static int tegra_xusb_phy_init(struct phy *phy)
532 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
534 return tegra_xusb_padctl_enable(padctl);
537 static int tegra_xusb_phy_exit(struct phy *phy)
539 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
541 return tegra_xusb_padctl_disable(padctl);
544 static int pcie_phy_power_on(struct phy *phy)
546 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
547 unsigned long timeout;
548 int err = -ETIMEDOUT;
551 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
552 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
553 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
555 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
556 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
557 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
558 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
559 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
561 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
562 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
563 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
565 timeout = jiffies + msecs_to_jiffies(50);
567 while (time_before(jiffies, timeout)) {
568 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
569 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
574 usleep_range(100, 200);
580 static int pcie_phy_power_off(struct phy *phy)
582 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
585 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
586 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
587 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
592 static const struct phy_ops pcie_phy_ops = {
593 .init = tegra_xusb_phy_init,
594 .exit = tegra_xusb_phy_exit,
595 .power_on = pcie_phy_power_on,
596 .power_off = pcie_phy_power_off,
597 .owner = THIS_MODULE,
600 static int sata_phy_power_on(struct phy *phy)
602 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
603 unsigned long timeout;
604 int err = -ETIMEDOUT;
607 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
608 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
609 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
610 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
612 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
613 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
614 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
615 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
617 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
618 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
619 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
621 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
622 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
623 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
625 timeout = jiffies + msecs_to_jiffies(50);
627 while (time_before(jiffies, timeout)) {
628 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
629 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
634 usleep_range(100, 200);
640 static int sata_phy_power_off(struct phy *phy)
642 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
645 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
646 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
647 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
649 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
650 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
651 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
653 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
654 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
655 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
656 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
658 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
659 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
660 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
661 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
666 static const struct phy_ops sata_phy_ops = {
667 .init = tegra_xusb_phy_init,
668 .exit = tegra_xusb_phy_exit,
669 .power_on = sata_phy_power_on,
670 .power_off = sata_phy_power_off,
671 .owner = THIS_MODULE,
674 static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
675 struct of_phandle_args *args)
677 struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
678 unsigned int index = args->args[0];
680 if (args->args_count <= 0)
681 return ERR_PTR(-EINVAL);
683 if (index >= ARRAY_SIZE(padctl->phys))
684 return ERR_PTR(-EINVAL);
686 return padctl->phys[index];
699 #define PIN_PCIE_4 10
700 #define PIN_SATA_0 11
702 static const struct pinctrl_pin_desc tegra124_pins[] = {
703 PINCTRL_PIN(PIN_OTG_0, "otg-0"),
704 PINCTRL_PIN(PIN_OTG_1, "otg-1"),
705 PINCTRL_PIN(PIN_OTG_2, "otg-2"),
706 PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
707 PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
708 PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
709 PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
710 PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
711 PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
712 PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
713 PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
714 PINCTRL_PIN(PIN_SATA_0, "sata-0"),
717 static const char * const tegra124_snps_groups[] = {
726 static const char * const tegra124_xusb_groups[] = {
735 static const char * const tegra124_uart_groups[] = {
741 static const char * const tegra124_pcie_groups[] = {
750 static const char * const tegra124_usb3_groups[] = {
759 static const char * const tegra124_sata_groups[] = {
768 static const char * const tegra124_rsvd_groups[] = {
780 #define TEGRA124_FUNCTION(_name) \
783 .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \
784 .groups = tegra124_##_name##_groups, \
787 static struct tegra_xusb_padctl_function tegra124_functions[] = {
788 TEGRA124_FUNCTION(snps),
789 TEGRA124_FUNCTION(xusb),
790 TEGRA124_FUNCTION(uart),
791 TEGRA124_FUNCTION(pcie),
792 TEGRA124_FUNCTION(usb3),
793 TEGRA124_FUNCTION(sata),
794 TEGRA124_FUNCTION(rsvd),
797 enum tegra124_function {
807 static const unsigned int tegra124_otg_functions[] = {
814 static const unsigned int tegra124_usb_functions[] = {
819 static const unsigned int tegra124_pci_functions[] = {
826 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
833 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
834 .funcs = tegra124_##_funcs##_functions, \
837 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
838 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
839 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
840 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
841 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
842 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
843 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
844 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
845 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
846 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
847 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
848 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
849 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
852 static const struct tegra_xusb_padctl_soc tegra124_soc = {
853 .num_pins = ARRAY_SIZE(tegra124_pins),
854 .pins = tegra124_pins,
855 .num_functions = ARRAY_SIZE(tegra124_functions),
856 .functions = tegra124_functions,
857 .num_lanes = ARRAY_SIZE(tegra124_lanes),
858 .lanes = tegra124_lanes,
861 static const struct of_device_id tegra_xusb_padctl_of_match[] = {
862 { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
865 MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
867 static int tegra_xusb_padctl_probe(struct platform_device *pdev)
869 struct tegra_xusb_padctl *padctl;
870 const struct of_device_id *match;
871 struct resource *res;
875 padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
879 platform_set_drvdata(pdev, padctl);
880 mutex_init(&padctl->lock);
881 padctl->dev = &pdev->dev;
883 match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
884 padctl->soc = match->data;
886 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
887 padctl->regs = devm_ioremap_resource(&pdev->dev, res);
888 if (IS_ERR(padctl->regs))
889 return PTR_ERR(padctl->regs);
891 padctl->rst = devm_reset_control_get(&pdev->dev, NULL);
892 if (IS_ERR(padctl->rst))
893 return PTR_ERR(padctl->rst);
895 err = reset_control_deassert(padctl->rst);
899 memset(&padctl->desc, 0, sizeof(padctl->desc));
900 padctl->desc.name = dev_name(padctl->dev);
901 padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
902 padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
903 padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
904 padctl->desc.owner = THIS_MODULE;
906 padctl->pinctrl = pinctrl_register(&padctl->desc, &pdev->dev, padctl);
907 if (!padctl->pinctrl) {
908 dev_err(&pdev->dev, "failed to register pincontrol\n");
913 phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops, NULL);
919 padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
920 phy_set_drvdata(phy, padctl);
922 phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops, NULL);
928 padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
929 phy_set_drvdata(phy, padctl);
931 padctl->provider = devm_of_phy_provider_register(&pdev->dev,
932 tegra_xusb_padctl_xlate);
933 if (IS_ERR(padctl->provider)) {
934 err = PTR_ERR(padctl->provider);
935 dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
942 pinctrl_unregister(padctl->pinctrl);
944 reset_control_assert(padctl->rst);
948 static int tegra_xusb_padctl_remove(struct platform_device *pdev)
950 struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
953 pinctrl_unregister(padctl->pinctrl);
955 err = reset_control_assert(padctl->rst);
957 dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
962 static struct platform_driver tegra_xusb_padctl_driver = {
964 .name = "tegra-xusb-padctl",
965 .of_match_table = tegra_xusb_padctl_of_match,
967 .probe = tegra_xusb_padctl_probe,
968 .remove = tegra_xusb_padctl_remove,
970 module_platform_driver(tegra_xusb_padctl_driver);
972 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
973 MODULE_DESCRIPTION("Tegra 124 XUSB Pad Control driver");
974 MODULE_LICENSE("GPL v2");