drivers/pinctrl/pinctrl-tegra.c

   1 /*
   2  * Driver for the NVIDIA Tegra pinmux
   3  *
   4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Derived from code:
   7  * Copyright (C) 2010 Google, Inc.
   8  * Copyright (C) 2010 NVIDIA Corporation
   9  * Copyright (C) 2009-2011 ST-Ericsson AB
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms and conditions of the GNU General Public License,
  13  * version 2, as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  * more details.
  19  */
  20
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pinctrl/machine.h>
  28 #include <linux/pinctrl/pinctrl.h>
  29 #include <linux/pinctrl/pinmux.h>
  30 #include <linux/pinctrl/pinconf.h>
  31 #include <linux/slab.h>
  32
  33 #include "core.h"
  34 #include "pinctrl-tegra.h"
  35 #include "pinctrl-utils.h"
  36
  37 struct tegra_pmx {
  38         struct device *dev;
  39         struct pinctrl_dev *pctl;
  40
  41         const struct tegra_pinctrl_soc_data *soc;
  42
  43         int nbanks;
  44         void __iomem **regs;
  45 };
  46
  47 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
  48 {
  49         return readl(pmx->regs[bank] + reg);
  50 }
  51
  52 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
  53 {
  54         writel(val, pmx->regs[bank] + reg);
  55 }
  56
  57 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  58 {
  59         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  60
  61         return pmx->soc->ngroups;
  62 }
  63
  64 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  65                                                 unsigned group)
  66 {
  67         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  68
  69         return pmx->soc->groups[group].name;
  70 }
  71
  72 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  73                                         unsigned group,
  74                                         const unsigned **pins,
  75                                         unsigned *num_pins)
  76 {
  77         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  78
  79         *pins = pmx->soc->groups[group].pins;
  80         *num_pins = pmx->soc->groups[group].npins;
  81
  82         return 0;
  83 }
  84
  85 #ifdef CONFIG_DEBUG_FS
  86 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
  87                                        struct seq_file *s,
  88                                        unsigned offset)
  89 {
  90         seq_printf(s, " %s", dev_name(pctldev->dev));
  91 }
  92 #endif
  93
  94 static const struct cfg_param {
  95         const char *property;
  96         enum tegra_pinconf_param param;
  97 } cfg_params[] = {
  98         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
  99         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
 100         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
 101         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
 102         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
 103         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
 104         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
 105         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
 106         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
 107         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
 108         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
 109         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
 110         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
 111         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
 112         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
 113 };
 114
 115 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 116                                            struct device_node *np,
 117                                            struct pinctrl_map **map,
 118                                            unsigned *reserved_maps,
 119                                            unsigned *num_maps)
 120 {
 121         struct device *dev = pctldev->dev;
 122         int ret, i;
 123         const char *function;
 124         u32 val;
 125         unsigned long config;
 126         unsigned long *configs = NULL;
 127         unsigned num_configs = 0;
 128         unsigned reserve;
 129         struct property *prop;
 130         const char *group;
 131
 132         ret = of_property_read_string(np, "nvidia,function", &function);
 133         if (ret < 0) {
 134                 /* EINVAL=missing, which is fine since it's optional */
 135                 if (ret != -EINVAL)
 136                         dev_err(dev,
 137                                 "could not parse property nvidia,function\n");
 138                 function = NULL;
 139         }
 140
 141         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 142                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
 143                 if (!ret) {
 144                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
 145                         ret = pinctrl_utils_add_config(pctldev, &configs,
 146                                         &num_configs, config);
 147                         if (ret < 0)
 148                                 goto exit;
 149                 /* EINVAL=missing, which is fine since it's optional */
 150                 } else if (ret != -EINVAL) {
 151                         dev_err(dev, "could not parse property %s\n",
 152                                 cfg_params[i].property);
 153                 }
 154         }
 155
 156         reserve = 0;
 157         if (function != NULL)
 158                 reserve++;
 159         if (num_configs)
 160                 reserve++;
 161         ret = of_property_count_strings(np, "nvidia,pins");
 162         if (ret < 0) {
 163                 dev_err(dev, "could not parse property nvidia,pins\n");
 164                 goto exit;
 165         }
 166         reserve *= ret;
 167
 168         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
 169                                         num_maps, reserve);
 170         if (ret < 0)
 171                 goto exit;
 172
 173         of_property_for_each_string(np, "nvidia,pins", prop, group) {
 174                 if (function) {
 175                         ret = pinctrl_utils_add_map_mux(pctldev, map,
 176                                         reserved_maps, num_maps, group,
 177                                         function);
 178                         if (ret < 0)
 179                                 goto exit;
 180                 }
 181
 182                 if (num_configs) {
 183                         ret = pinctrl_utils_add_map_configs(pctldev, map,
 184                                         reserved_maps, num_maps, group,
 185                                         configs, num_configs,
 186                                         PIN_MAP_TYPE_CONFIGS_GROUP);
 187                         if (ret < 0)
 188                                 goto exit;
 189                 }
 190         }
 191
 192         ret = 0;
 193
 194 exit:
 195         kfree(configs);
 196         return ret;
 197 }
 198
 199 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 200                                         struct device_node *np_config,
 201                                         struct pinctrl_map **map,
 202                                         unsigned *num_maps)
 203 {
 204         unsigned reserved_maps;
 205         struct device_node *np;
 206         int ret;
 207
 208         reserved_maps = 0;
 209         *map = NULL;
 210         *num_maps = 0;
 211
 212         for_each_child_of_node(np_config, np) {
 213                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
 214                                                       &reserved_maps, num_maps);
 215                 if (ret < 0) {
 216                         pinctrl_utils_dt_free_map(pctldev, *map,
 217                                 *num_maps);
 218                         return ret;
 219                 }
 220         }
 221
 222         return 0;
 223 }
 224
 225 static const struct pinctrl_ops tegra_pinctrl_ops = {
 226         .get_groups_count = tegra_pinctrl_get_groups_count,
 227         .get_group_name = tegra_pinctrl_get_group_name,
 228         .get_group_pins = tegra_pinctrl_get_group_pins,
 229 #ifdef CONFIG_DEBUG_FS
 230         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 231 #endif
 232         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
 233         .dt_free_map = pinctrl_utils_dt_free_map,
 234 };
 235
 236 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 237 {
 238         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 239
 240         return pmx->soc->nfunctions;
 241 }
 242
 243 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 244                                                unsigned function)
 245 {
 246         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 247
 248         return pmx->soc->functions[function].name;
 249 }
 250
 251 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 252                                          unsigned function,
 253                                          const char * const **groups,
 254                                          unsigned * const num_groups)
 255 {
 256         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 257
 258         *groups = pmx->soc->functions[function].groups;
 259         *num_groups = pmx->soc->functions[function].ngroups;
 260
 261         return 0;
 262 }
 263
 264 static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
 265                                unsigned group)
 266 {
 267         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 268         const struct tegra_pingroup *g;
 269         int i;
 270         u32 val;
 271
 272         g = &pmx->soc->groups[group];
 273
 274         if (WARN_ON(g->mux_reg < 0))
 275                 return -EINVAL;
 276
 277         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 278                 if (g->funcs[i] == function)
 279                         break;
 280         }
 281         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 282                 return -EINVAL;
 283
 284         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 285         val &= ~(0x3 << g->mux_bit);
 286         val |= i << g->mux_bit;
 287         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 288
 289         return 0;
 290 }
 291
 292 static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
 293                                   unsigned function, unsigned group)
 294 {
 295         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 296         const struct tegra_pingroup *g;
 297         u32 val;
 298
 299         g = &pmx->soc->groups[group];
 300
 301         if (WARN_ON(g->mux_reg < 0))
 302                 return;
 303
 304         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 305         val &= ~(0x3 << g->mux_bit);
 306         val |= g->func_safe << g->mux_bit;
 307         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 308 }
 309
 310 static const struct pinmux_ops tegra_pinmux_ops = {
 311         .get_functions_count = tegra_pinctrl_get_funcs_count,
 312         .get_function_name = tegra_pinctrl_get_func_name,
 313         .get_function_groups = tegra_pinctrl_get_func_groups,
 314         .enable = tegra_pinctrl_enable,
 315         .disable = tegra_pinctrl_disable,
 316 };
 317
 318 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 319                              const struct tegra_pingroup *g,
 320                              enum tegra_pinconf_param param,
 321                              bool report_err,
 322                              s8 *bank, s16 *reg, s8 *bit, s8 *width)
 323 {
 324         switch (param) {
 325         case TEGRA_PINCONF_PARAM_PULL:
 326                 *bank = g->pupd_bank;
 327                 *reg = g->pupd_reg;
 328                 *bit = g->pupd_bit;
 329                 *width = 2;
 330                 break;
 331         case TEGRA_PINCONF_PARAM_TRISTATE:
 332                 *bank = g->tri_bank;
 333                 *reg = g->tri_reg;
 334                 *bit = g->tri_bit;
 335                 *width = 1;
 336                 break;
 337         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
 338                 *bank = g->einput_bank;
 339                 *reg = g->einput_reg;
 340                 *bit = g->einput_bit;
 341                 *width = 1;
 342                 break;
 343         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
 344                 *bank = g->odrain_bank;
 345                 *reg = g->odrain_reg;
 346                 *bit = g->odrain_bit;
 347                 *width = 1;
 348                 break;
 349         case TEGRA_PINCONF_PARAM_LOCK:
 350                 *bank = g->lock_bank;
 351                 *reg = g->lock_reg;
 352                 *bit = g->lock_bit;
 353                 *width = 1;
 354                 break;
 355         case TEGRA_PINCONF_PARAM_IORESET:
 356                 *bank = g->ioreset_bank;
 357                 *reg = g->ioreset_reg;
 358                 *bit = g->ioreset_bit;
 359                 *width = 1;
 360                 break;
 361         case TEGRA_PINCONF_PARAM_RCV_SEL:
 362                 *bank = g->rcv_sel_bank;
 363                 *reg = g->rcv_sel_reg;
 364                 *bit = g->rcv_sel_bit;
 365                 *width = 1;
 366                 break;
 367         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
 368                 *bank = g->drv_bank;
 369                 *reg = g->drv_reg;
 370                 *bit = g->hsm_bit;
 371                 *width = 1;
 372                 break;
 373         case TEGRA_PINCONF_PARAM_SCHMITT:
 374                 *bank = g->drv_bank;
 375                 *reg = g->drv_reg;
 376                 *bit = g->schmitt_bit;
 377                 *width = 1;
 378                 break;
 379         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
 380                 *bank = g->drv_bank;
 381                 *reg = g->drv_reg;
 382                 *bit = g->lpmd_bit;
 383                 *width = 2;
 384                 break;
 385         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
 386                 *bank = g->drv_bank;
 387                 *reg = g->drv_reg;
 388                 *bit = g->drvdn_bit;
 389                 *width = g->drvdn_width;
 390                 break;
 391         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
 392                 *bank = g->drv_bank;
 393                 *reg = g->drv_reg;
 394                 *bit = g->drvup_bit;
 395                 *width = g->drvup_width;
 396                 break;
 397         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
 398                 *bank = g->drv_bank;
 399                 *reg = g->drv_reg;
 400                 *bit = g->slwf_bit;
 401                 *width = g->slwf_width;
 402                 break;
 403         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
 404                 *bank = g->drv_bank;
 405                 *reg = g->drv_reg;
 406                 *bit = g->slwr_bit;
 407                 *width = g->slwr_width;
 408                 break;
 409         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
 410                 *bank = g->drvtype_bank;
 411                 *reg = g->drvtype_reg;
 412                 *bit = g->drvtype_bit;
 413                 *width = 2;
 414                 break;
 415         default:
 416                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
 417                 return -ENOTSUPP;
 418         }
 419
 420         if (*reg < 0) {
 421                 if (report_err)
 422                         dev_err(pmx->dev,
 423                                 "Config param %04x not supported on group %s\n",
 424                                 param, g->name);
 425                 return -ENOTSUPP;
 426         }
 427
 428         return 0;
 429 }
 430
 431 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
 432                              unsigned pin, unsigned long *config)
 433 {
 434         dev_err(pctldev->dev, "pin_config_get op not supported\n");
 435         return -ENOTSUPP;
 436 }
 437
 438 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
 439                              unsigned pin, unsigned long config)
 440 {
 441         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 442         return -ENOTSUPP;
 443 }
 444
 445 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
 446                                    unsigned group, unsigned long *config)
 447 {
 448         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 449         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
 450         u16 arg;
 451         const struct tegra_pingroup *g;
 452         int ret;
 453         s8 bank, bit, width;
 454         s16 reg;
 455         u32 val, mask;
 456
 457         g = &pmx->soc->groups[group];
 458
 459         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 460                                 &width);
 461         if (ret < 0)
 462                 return ret;
 463
 464         val = pmx_readl(pmx, bank, reg);
 465         mask = (1 << width) - 1;
 466         arg = (val >> bit) & mask;
 467
 468         *config = TEGRA_PINCONF_PACK(param, arg);
 469
 470         return 0;
 471 }
 472
 473 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 474                                    unsigned group, unsigned long config)
 475 {
 476         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 477         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 478         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 479         const struct tegra_pingroup *g;
 480         int ret;
 481         s8 bank, bit, width;
 482         s16 reg;
 483         u32 val, mask;
 484
 485         g = &pmx->soc->groups[group];
 486
 487         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 488                                 &width);
 489         if (ret < 0)
 490                 return ret;
 491
 492         val = pmx_readl(pmx, bank, reg);
 493
 494         /* LOCK can't be cleared */
 495         if (param == TEGRA_PINCONF_PARAM_LOCK) {
 496                 if ((val & BIT(bit)) && !arg) {
 497                         dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
 498                         return -EINVAL;
 499                 }
 500         }
 501
 502         /* Special-case Boolean values; allow any non-zero as true */
 503         if (width == 1)
 504                 arg = !!arg;
 505
 506         /* Range-check user-supplied value */
 507         mask = (1 << width) - 1;
 508         if (arg & ~mask) {
 509                 dev_err(pctldev->dev,
 510                         "config %lx: %x too big for %d bit register\n",
 511                         config, arg, width);
 512                 return -EINVAL;
 513         }
 514
 515         /* Update register */
 516         val &= ~(mask << bit);
 517         val |= arg << bit;
 518         pmx_writel(pmx, val, bank, reg);
 519
 520         return 0;
 521 }
 522
 523 #ifdef CONFIG_DEBUG_FS
 524 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 525                                    struct seq_file *s, unsigned offset)
 526 {
 527 }
 528
 529 static const char *strip_prefix(const char *s)
 530 {
 531         const char *comma = strchr(s, ',');
 532         if (!comma)
 533                 return s;
 534
 535         return comma + 1;
 536 }
 537
 538 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 539                                          struct seq_file *s, unsigned group)
 540 {
 541         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 542         const struct tegra_pingroup *g;
 543         int i, ret;
 544         s8 bank, bit, width;
 545         s16 reg;
 546         u32 val;
 547
 548         g = &pmx->soc->groups[group];
 549
 550         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 551                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
 552                                         &bank, &reg, &bit, &width);
 553                 if (ret < 0)
 554                         continue;
 555
 556                 val = pmx_readl(pmx, bank, reg);
 557                 val >>= bit;
 558                 val &= (1 << width) - 1;
 559
 560                 seq_printf(s, "\n\t%s=%u",
 561                            strip_prefix(cfg_params[i].property), val);
 562         }
 563 }
 564
 565 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 566                                           struct seq_file *s,
 567                                           unsigned long config)
 568 {
 569         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 570         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 571         const char *pname = "unknown";
 572         int i;
 573
 574         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 575                 if (cfg_params[i].param == param) {
 576                         pname = cfg_params[i].property;
 577                         break;
 578                 }
 579         }
 580
 581         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
 582 }
 583 #endif
 584
 585 static const struct pinconf_ops tegra_pinconf_ops = {
 586         .pin_config_get = tegra_pinconf_get,
 587         .pin_config_set = tegra_pinconf_set,
 588         .pin_config_group_get = tegra_pinconf_group_get,
 589         .pin_config_group_set = tegra_pinconf_group_set,
 590 #ifdef CONFIG_DEBUG_FS
 591         .pin_config_dbg_show = tegra_pinconf_dbg_show,
 592         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
 593         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
 594 #endif
 595 };
 596
 597 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
 598         .name = "Tegra GPIOs",
 599         .id = 0,
 600         .base = 0,
 601 };
 602
 603 static struct pinctrl_desc tegra_pinctrl_desc = {
 604         .pctlops = &tegra_pinctrl_ops,
 605         .pmxops = &tegra_pinmux_ops,
 606         .confops = &tegra_pinconf_ops,
 607         .owner = THIS_MODULE,
 608 };
 609
 610 int tegra_pinctrl_probe(struct platform_device *pdev,
 611                         const struct tegra_pinctrl_soc_data *soc_data)
 612 {
 613         struct tegra_pmx *pmx;
 614         struct resource *res;
 615         int i;
 616
 617         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
 618         if (!pmx) {
 619                 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
 620                 return -ENOMEM;
 621         }
 622         pmx->dev = &pdev->dev;
 623         pmx->soc = soc_data;
 624
 625         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
 626         tegra_pinctrl_desc.name = dev_name(&pdev->dev);
 627         tegra_pinctrl_desc.pins = pmx->soc->pins;
 628         tegra_pinctrl_desc.npins = pmx->soc->npins;
 629
 630         for (i = 0; ; i++) {
 631                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 632                 if (!res)
 633                         break;
 634         }
 635         pmx->nbanks = i;
 636
 637         pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
 638                                  GFP_KERNEL);
 639         if (!pmx->regs) {
 640                 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
 641                 return -ENODEV;
 642         }
 643
 644         for (i = 0; i < pmx->nbanks; i++) {
 645                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 646                 if (!res) {
 647                         dev_err(&pdev->dev, "Missing MEM resource\n");
 648                         return -ENODEV;
 649                 }
 650
 651                 if (!devm_request_mem_region(&pdev->dev, res->start,
 652                                             resource_size(res),
 653                                             dev_name(&pdev->dev))) {
 654                         dev_err(&pdev->dev,
 655                                 "Couldn't request MEM resource %d\n", i);
 656                         return -ENODEV;
 657                 }
 658
 659                 pmx->regs[i] = devm_ioremap(&pdev->dev, res->start,
 660                                             resource_size(res));
 661                 if (!pmx->regs[i]) {
 662                         dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
 663                         return -ENODEV;
 664                 }
 665         }
 666
 667         pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
 668         if (!pmx->pctl) {
 669                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 670                 return -ENODEV;
 671         }
 672
 673         pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
 674
 675         platform_set_drvdata(pdev, pmx);
 676
 677         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
 678
 679         return 0;
 680 }
 681 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
 682
 683 int tegra_pinctrl_remove(struct platform_device *pdev)
 684 {
 685         struct tegra_pmx *pmx = platform_get_drvdata(pdev);
 686
 687         pinctrl_unregister(pmx->pctl);
 688
 689         return 0;
 690 }
 691 EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);