2 * Driver for the NVIDIA Tegra pinmux
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
7 * Copyright (C) 2010 Google, Inc.
8 * Copyright (C) 2010 NVIDIA Corporation
9 * Copyright (C) 2009-2011 ST-Ericsson AB
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 #include <linux/err.h>
22 #include <linux/init.h>
24 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/slab.h>
34 #include "pinctrl-tegra.h"
35 #include "pinctrl-utils.h"
39 struct pinctrl_dev *pctl;
41 const struct tegra_pinctrl_soc_data *soc;
42 const char **group_pins;
48 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
50 return readl(pmx->regs[bank] + reg);
53 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
55 writel(val, pmx->regs[bank] + reg);
58 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
60 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
62 return pmx->soc->ngroups;
65 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
68 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
70 return pmx->soc->groups[group].name;
73 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
75 const unsigned **pins,
78 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
80 *pins = pmx->soc->groups[group].pins;
81 *num_pins = pmx->soc->groups[group].npins;
86 #ifdef CONFIG_DEBUG_FS
87 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
91 seq_printf(s, " %s", dev_name(pctldev->dev));
95 static const struct cfg_param {
97 enum tegra_pinconf_param param;
99 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
100 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
101 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
102 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
103 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
104 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
105 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
106 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
107 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
108 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
109 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
110 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
111 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
112 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
113 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
116 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
117 struct device_node *np,
118 struct pinctrl_map **map,
119 unsigned *reserved_maps,
122 struct device *dev = pctldev->dev;
124 const char *function;
126 unsigned long config;
127 unsigned long *configs = NULL;
128 unsigned num_configs = 0;
130 struct property *prop;
133 ret = of_property_read_string(np, "nvidia,function", &function);
135 /* EINVAL=missing, which is fine since it's optional */
138 "could not parse property nvidia,function\n");
142 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
143 ret = of_property_read_u32(np, cfg_params[i].property, &val);
145 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
146 ret = pinctrl_utils_add_config(pctldev, &configs,
147 &num_configs, config);
150 /* EINVAL=missing, which is fine since it's optional */
151 } else if (ret != -EINVAL) {
152 dev_err(dev, "could not parse property %s\n",
153 cfg_params[i].property);
158 if (function != NULL)
162 ret = of_property_count_strings(np, "nvidia,pins");
164 dev_err(dev, "could not parse property nvidia,pins\n");
169 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
174 of_property_for_each_string(np, "nvidia,pins", prop, group) {
176 ret = pinctrl_utils_add_map_mux(pctldev, map,
177 reserved_maps, num_maps, group,
184 ret = pinctrl_utils_add_map_configs(pctldev, map,
185 reserved_maps, num_maps, group,
186 configs, num_configs,
187 PIN_MAP_TYPE_CONFIGS_GROUP);
200 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
201 struct device_node *np_config,
202 struct pinctrl_map **map,
205 unsigned reserved_maps;
206 struct device_node *np;
213 for_each_child_of_node(np_config, np) {
214 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
215 &reserved_maps, num_maps);
217 pinctrl_utils_dt_free_map(pctldev, *map,
226 static const struct pinctrl_ops tegra_pinctrl_ops = {
227 .get_groups_count = tegra_pinctrl_get_groups_count,
228 .get_group_name = tegra_pinctrl_get_group_name,
229 .get_group_pins = tegra_pinctrl_get_group_pins,
230 #ifdef CONFIG_DEBUG_FS
231 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
233 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
234 .dt_free_map = pinctrl_utils_dt_free_map,
237 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
239 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
241 return pmx->soc->nfunctions;
244 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
247 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
249 return pmx->soc->functions[function].name;
252 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
254 const char * const **groups,
255 unsigned * const num_groups)
257 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
259 *groups = pmx->soc->functions[function].groups;
260 *num_groups = pmx->soc->functions[function].ngroups;
265 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
269 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
270 const struct tegra_pingroup *g;
274 g = &pmx->soc->groups[group];
276 if (WARN_ON(g->mux_reg < 0))
279 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
280 if (g->funcs[i] == function)
283 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
286 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
287 val &= ~(0x3 << g->mux_bit);
288 val |= i << g->mux_bit;
289 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
294 static const struct pinmux_ops tegra_pinmux_ops = {
295 .get_functions_count = tegra_pinctrl_get_funcs_count,
296 .get_function_name = tegra_pinctrl_get_func_name,
297 .get_function_groups = tegra_pinctrl_get_func_groups,
298 .set_mux = tegra_pinctrl_set_mux,
301 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
302 const struct tegra_pingroup *g,
303 enum tegra_pinconf_param param,
305 s8 *bank, s16 *reg, s8 *bit, s8 *width)
308 case TEGRA_PINCONF_PARAM_PULL:
309 *bank = g->pupd_bank;
314 case TEGRA_PINCONF_PARAM_TRISTATE:
320 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
323 *bit = g->einput_bit;
326 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
329 *bit = g->odrain_bit;
332 case TEGRA_PINCONF_PARAM_LOCK:
338 case TEGRA_PINCONF_PARAM_IORESET:
341 *bit = g->ioreset_bit;
344 case TEGRA_PINCONF_PARAM_RCV_SEL:
347 *bit = g->rcv_sel_bit;
350 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
356 case TEGRA_PINCONF_PARAM_SCHMITT:
359 *bit = g->schmitt_bit;
362 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
368 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
372 *width = g->drvdn_width;
374 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
378 *width = g->drvup_width;
380 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
384 *width = g->slwf_width;
386 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
390 *width = g->slwr_width;
392 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
395 *bit = g->drvtype_bit;
399 dev_err(pmx->dev, "Invalid config param %04x\n", param);
403 if (*reg < 0 || *bit > 31) {
405 const char *prop = "unknown";
408 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
409 if (cfg_params[i].param == param) {
410 prop = cfg_params[i].property;
416 "Config param %04x (%s) not supported on group %s\n",
417 param, prop, g->name);
425 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
426 unsigned pin, unsigned long *config)
428 dev_err(pctldev->dev, "pin_config_get op not supported\n");
432 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
433 unsigned pin, unsigned long *configs,
434 unsigned num_configs)
436 dev_err(pctldev->dev, "pin_config_set op not supported\n");
440 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
441 unsigned group, unsigned long *config)
443 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
444 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
446 const struct tegra_pingroup *g;
452 g = &pmx->soc->groups[group];
454 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
459 val = pmx_readl(pmx, bank, reg);
460 mask = (1 << width) - 1;
461 arg = (val >> bit) & mask;
463 *config = TEGRA_PINCONF_PACK(param, arg);
468 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
469 unsigned group, unsigned long *configs,
470 unsigned num_configs)
472 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
473 enum tegra_pinconf_param param;
475 const struct tegra_pingroup *g;
481 g = &pmx->soc->groups[group];
483 for (i = 0; i < num_configs; i++) {
484 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
485 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
487 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
492 val = pmx_readl(pmx, bank, reg);
494 /* LOCK can't be cleared */
495 if (param == TEGRA_PINCONF_PARAM_LOCK) {
496 if ((val & BIT(bit)) && !arg) {
497 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
502 /* Special-case Boolean values; allow any non-zero as true */
506 /* Range-check user-supplied value */
507 mask = (1 << width) - 1;
509 dev_err(pctldev->dev,
510 "config %lx: %x too big for %d bit register\n",
511 configs[i], arg, width);
515 /* Update register */
516 val &= ~(mask << bit);
518 pmx_writel(pmx, val, bank, reg);
519 } /* for each config */
524 #ifdef CONFIG_DEBUG_FS
525 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
526 struct seq_file *s, unsigned offset)
530 static const char *strip_prefix(const char *s)
532 const char *comma = strchr(s, ',');
539 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
540 struct seq_file *s, unsigned group)
542 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
543 const struct tegra_pingroup *g;
549 g = &pmx->soc->groups[group];
551 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
552 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
553 &bank, ®, &bit, &width);
557 val = pmx_readl(pmx, bank, reg);
559 val &= (1 << width) - 1;
561 seq_printf(s, "\n\t%s=%u",
562 strip_prefix(cfg_params[i].property), val);
566 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
568 unsigned long config)
570 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
571 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
572 const char *pname = "unknown";
575 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
576 if (cfg_params[i].param == param) {
577 pname = cfg_params[i].property;
582 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
586 static const struct pinconf_ops tegra_pinconf_ops = {
587 .pin_config_get = tegra_pinconf_get,
588 .pin_config_set = tegra_pinconf_set,
589 .pin_config_group_get = tegra_pinconf_group_get,
590 .pin_config_group_set = tegra_pinconf_group_set,
591 #ifdef CONFIG_DEBUG_FS
592 .pin_config_dbg_show = tegra_pinconf_dbg_show,
593 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
594 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
598 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
599 .name = "Tegra GPIOs",
604 static struct pinctrl_desc tegra_pinctrl_desc = {
605 .pctlops = &tegra_pinctrl_ops,
606 .pmxops = &tegra_pinmux_ops,
607 .confops = &tegra_pinconf_ops,
608 .owner = THIS_MODULE,
611 int tegra_pinctrl_probe(struct platform_device *pdev,
612 const struct tegra_pinctrl_soc_data *soc_data)
614 struct tegra_pmx *pmx;
615 struct resource *res;
617 const char **group_pins;
620 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
622 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
625 pmx->dev = &pdev->dev;
629 * Each mux group will appear in 4 functions' list of groups.
630 * This over-allocates slightly, since not all groups are mux groups.
632 pmx->group_pins = devm_kzalloc(&pdev->dev,
633 soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
635 if (!pmx->group_pins)
638 group_pins = pmx->group_pins;
639 for (fn = 0; fn < soc_data->nfunctions; fn++) {
640 struct tegra_function *func = &soc_data->functions[fn];
642 func->groups = group_pins;
644 for (gn = 0; gn < soc_data->ngroups; gn++) {
645 const struct tegra_pingroup *g = &soc_data->groups[gn];
647 if (g->mux_reg == -1)
650 for (gfn = 0; gfn < 4; gfn++)
651 if (g->funcs[gfn] == fn)
656 BUG_ON(group_pins - pmx->group_pins >=
657 soc_data->ngroups * 4);
658 *group_pins++ = g->name;
663 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
664 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
665 tegra_pinctrl_desc.pins = pmx->soc->pins;
666 tegra_pinctrl_desc.npins = pmx->soc->npins;
669 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
675 pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
678 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
682 for (i = 0; i < pmx->nbanks; i++) {
683 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
684 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
685 if (IS_ERR(pmx->regs[i]))
686 return PTR_ERR(pmx->regs[i]);
689 pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
691 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
695 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
697 platform_set_drvdata(pdev, pmx);
699 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
703 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
705 int tegra_pinctrl_remove(struct platform_device *pdev)
707 struct tegra_pmx *pmx = platform_get_drvdata(pdev);
709 pinctrl_unregister(pmx->pctl);
713 EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);