2 * Driver for the NVIDIA Tegra pinmux
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
7 * Copyright (C) 2010 Google, Inc.
8 * Copyright (C) 2010 NVIDIA Corporation
9 * Copyright (C) 2009-2011 ST-Ericsson AB
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 #include <linux/err.h>
22 #include <linux/init.h>
24 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/slab.h>
34 #include "pinctrl-tegra.h"
35 #include "pinctrl-utils.h"
39 struct pinctrl_dev *pctl;
41 const struct tegra_pinctrl_soc_data *soc;
47 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
49 return readl(pmx->regs[bank] + reg);
52 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
54 writel(val, pmx->regs[bank] + reg);
57 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
59 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
61 return pmx->soc->ngroups;
64 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
67 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
69 return pmx->soc->groups[group].name;
72 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
74 const unsigned **pins,
77 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
79 *pins = pmx->soc->groups[group].pins;
80 *num_pins = pmx->soc->groups[group].npins;
85 #ifdef CONFIG_DEBUG_FS
86 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
90 seq_printf(s, " %s", dev_name(pctldev->dev));
94 static const struct cfg_param {
96 enum tegra_pinconf_param param;
98 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
99 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
100 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
101 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
102 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
103 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
104 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
105 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
106 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
107 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
108 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
109 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
110 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
111 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
112 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
115 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
116 struct device_node *np,
117 struct pinctrl_map **map,
118 unsigned *reserved_maps,
121 struct device *dev = pctldev->dev;
123 const char *function;
125 unsigned long config;
126 unsigned long *configs = NULL;
127 unsigned num_configs = 0;
129 struct property *prop;
132 ret = of_property_read_string(np, "nvidia,function", &function);
134 /* EINVAL=missing, which is fine since it's optional */
137 "could not parse property nvidia,function\n");
141 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
142 ret = of_property_read_u32(np, cfg_params[i].property, &val);
144 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
145 ret = pinctrl_utils_add_config(pctldev, &configs,
146 &num_configs, config);
149 /* EINVAL=missing, which is fine since it's optional */
150 } else if (ret != -EINVAL) {
151 dev_err(dev, "could not parse property %s\n",
152 cfg_params[i].property);
157 if (function != NULL)
161 ret = of_property_count_strings(np, "nvidia,pins");
163 dev_err(dev, "could not parse property nvidia,pins\n");
168 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
173 of_property_for_each_string(np, "nvidia,pins", prop, group) {
175 ret = pinctrl_utils_add_map_mux(pctldev, map,
176 reserved_maps, num_maps, group,
183 ret = pinctrl_utils_add_map_configs(pctldev, map,
184 reserved_maps, num_maps, group,
185 configs, num_configs,
186 PIN_MAP_TYPE_CONFIGS_GROUP);
199 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
200 struct device_node *np_config,
201 struct pinctrl_map **map,
204 unsigned reserved_maps;
205 struct device_node *np;
212 for_each_child_of_node(np_config, np) {
213 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
214 &reserved_maps, num_maps);
216 pinctrl_utils_dt_free_map(pctldev, *map,
225 static const struct pinctrl_ops tegra_pinctrl_ops = {
226 .get_groups_count = tegra_pinctrl_get_groups_count,
227 .get_group_name = tegra_pinctrl_get_group_name,
228 .get_group_pins = tegra_pinctrl_get_group_pins,
229 #ifdef CONFIG_DEBUG_FS
230 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
232 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
233 .dt_free_map = pinctrl_utils_dt_free_map,
236 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
238 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
240 return pmx->soc->nfunctions;
243 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
246 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
248 return pmx->soc->functions[function].name;
251 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
253 const char * const **groups,
254 unsigned * const num_groups)
256 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
258 *groups = pmx->soc->functions[function].groups;
259 *num_groups = pmx->soc->functions[function].ngroups;
264 static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
267 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
268 const struct tegra_pingroup *g;
272 g = &pmx->soc->groups[group];
274 if (WARN_ON(g->mux_reg < 0))
277 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
278 if (g->funcs[i] == function)
281 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
284 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
285 val &= ~(0x3 << g->mux_bit);
286 val |= i << g->mux_bit;
287 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
292 static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
293 unsigned function, unsigned group)
295 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
296 const struct tegra_pingroup *g;
299 g = &pmx->soc->groups[group];
301 if (WARN_ON(g->mux_reg < 0))
304 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
305 val &= ~(0x3 << g->mux_bit);
306 val |= g->func_safe << g->mux_bit;
307 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
310 static const struct pinmux_ops tegra_pinmux_ops = {
311 .get_functions_count = tegra_pinctrl_get_funcs_count,
312 .get_function_name = tegra_pinctrl_get_func_name,
313 .get_function_groups = tegra_pinctrl_get_func_groups,
314 .enable = tegra_pinctrl_enable,
315 .disable = tegra_pinctrl_disable,
318 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
319 const struct tegra_pingroup *g,
320 enum tegra_pinconf_param param,
322 s8 *bank, s16 *reg, s8 *bit, s8 *width)
325 case TEGRA_PINCONF_PARAM_PULL:
326 *bank = g->pupd_bank;
331 case TEGRA_PINCONF_PARAM_TRISTATE:
337 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
338 *bank = g->einput_bank;
339 *reg = g->einput_reg;
340 *bit = g->einput_bit;
343 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
344 *bank = g->odrain_bank;
345 *reg = g->odrain_reg;
346 *bit = g->odrain_bit;
349 case TEGRA_PINCONF_PARAM_LOCK:
350 *bank = g->lock_bank;
355 case TEGRA_PINCONF_PARAM_IORESET:
356 *bank = g->ioreset_bank;
357 *reg = g->ioreset_reg;
358 *bit = g->ioreset_bit;
361 case TEGRA_PINCONF_PARAM_RCV_SEL:
362 *bank = g->rcv_sel_bank;
363 *reg = g->rcv_sel_reg;
364 *bit = g->rcv_sel_bit;
367 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
373 case TEGRA_PINCONF_PARAM_SCHMITT:
376 *bit = g->schmitt_bit;
379 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
385 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
389 *width = g->drvdn_width;
391 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
395 *width = g->drvup_width;
397 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
401 *width = g->slwf_width;
403 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
407 *width = g->slwr_width;
409 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
410 *bank = g->drvtype_bank;
411 *reg = g->drvtype_reg;
412 *bit = g->drvtype_bit;
416 dev_err(pmx->dev, "Invalid config param %04x\n", param);
423 "Config param %04x not supported on group %s\n",
431 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
432 unsigned pin, unsigned long *config)
434 dev_err(pctldev->dev, "pin_config_get op not supported\n");
438 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
439 unsigned pin, unsigned long config)
441 dev_err(pctldev->dev, "pin_config_set op not supported\n");
445 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
446 unsigned group, unsigned long *config)
448 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
449 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
451 const struct tegra_pingroup *g;
457 g = &pmx->soc->groups[group];
459 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
464 val = pmx_readl(pmx, bank, reg);
465 mask = (1 << width) - 1;
466 arg = (val >> bit) & mask;
468 *config = TEGRA_PINCONF_PACK(param, arg);
473 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
474 unsigned group, unsigned long config)
476 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
477 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
478 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
479 const struct tegra_pingroup *g;
485 g = &pmx->soc->groups[group];
487 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
492 val = pmx_readl(pmx, bank, reg);
494 /* LOCK can't be cleared */
495 if (param == TEGRA_PINCONF_PARAM_LOCK) {
496 if ((val & BIT(bit)) && !arg) {
497 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
502 /* Special-case Boolean values; allow any non-zero as true */
506 /* Range-check user-supplied value */
507 mask = (1 << width) - 1;
509 dev_err(pctldev->dev,
510 "config %lx: %x too big for %d bit register\n",
515 /* Update register */
516 val &= ~(mask << bit);
518 pmx_writel(pmx, val, bank, reg);
523 #ifdef CONFIG_DEBUG_FS
524 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
525 struct seq_file *s, unsigned offset)
529 static const char *strip_prefix(const char *s)
531 const char *comma = strchr(s, ',');
538 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
539 struct seq_file *s, unsigned group)
541 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
542 const struct tegra_pingroup *g;
548 g = &pmx->soc->groups[group];
550 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
551 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
552 &bank, ®, &bit, &width);
556 val = pmx_readl(pmx, bank, reg);
558 val &= (1 << width) - 1;
560 seq_printf(s, "\n\t%s=%u",
561 strip_prefix(cfg_params[i].property), val);
565 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
567 unsigned long config)
569 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
570 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
571 const char *pname = "unknown";
574 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
575 if (cfg_params[i].param == param) {
576 pname = cfg_params[i].property;
581 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
585 static const struct pinconf_ops tegra_pinconf_ops = {
586 .pin_config_get = tegra_pinconf_get,
587 .pin_config_set = tegra_pinconf_set,
588 .pin_config_group_get = tegra_pinconf_group_get,
589 .pin_config_group_set = tegra_pinconf_group_set,
590 #ifdef CONFIG_DEBUG_FS
591 .pin_config_dbg_show = tegra_pinconf_dbg_show,
592 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
593 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
597 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
598 .name = "Tegra GPIOs",
603 static struct pinctrl_desc tegra_pinctrl_desc = {
604 .pctlops = &tegra_pinctrl_ops,
605 .pmxops = &tegra_pinmux_ops,
606 .confops = &tegra_pinconf_ops,
607 .owner = THIS_MODULE,
610 int tegra_pinctrl_probe(struct platform_device *pdev,
611 const struct tegra_pinctrl_soc_data *soc_data)
613 struct tegra_pmx *pmx;
614 struct resource *res;
617 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
619 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
622 pmx->dev = &pdev->dev;
625 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
626 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
627 tegra_pinctrl_desc.pins = pmx->soc->pins;
628 tegra_pinctrl_desc.npins = pmx->soc->npins;
631 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
637 pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
640 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
644 for (i = 0; i < pmx->nbanks; i++) {
645 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
646 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
647 if (IS_ERR(pmx->regs[i]))
648 return PTR_ERR(pmx->regs[i]);
651 pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
653 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
657 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
659 platform_set_drvdata(pdev, pmx);
661 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
665 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
667 int tegra_pinctrl_remove(struct platform_device *pdev)
669 struct tegra_pmx *pmx = platform_get_drvdata(pdev);
671 pinctrl_unregister(pmx->pctl);
675 EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);