drivers/pinctrl/pinctrl-tegra114.c

   1 /*
   2  * Pinctrl data for the NVIDIA Tegra114 pinmux
   3  *
   4  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21
  22 #include "pinctrl-tegra.h"
  23
  24 /*
  25  * Most pins affected by the pinmux can also be GPIOs. Define these first.
  26  * These must match how the GPIO driver names/numbers its pins.
  27  */
  28 #define _GPIO(offset)                           (offset)
  29
  30 #define TEGRA_PIN_CLK_32K_OUT_PA0               _GPIO(0)
  31 #define TEGRA_PIN_UART3_CTS_N_PA1               _GPIO(1)
  32 #define TEGRA_PIN_DAP2_FS_PA2                   _GPIO(2)
  33 #define TEGRA_PIN_DAP2_SCLK_PA3                 _GPIO(3)
  34 #define TEGRA_PIN_DAP2_DIN_PA4                  _GPIO(4)
  35 #define TEGRA_PIN_DAP2_DOUT_PA5                 _GPIO(5)
  36 #define TEGRA_PIN_SDMMC3_CLK_PA6                _GPIO(6)
  37 #define TEGRA_PIN_SDMMC3_CMD_PA7                _GPIO(7)
  38 #define TEGRA_PIN_GMI_A17_PB0                   _GPIO(8)
  39 #define TEGRA_PIN_GMI_A18_PB1                   _GPIO(9)
  40 #define TEGRA_PIN_SDMMC3_DAT3_PB4               _GPIO(12)
  41 #define TEGRA_PIN_SDMMC3_DAT2_PB5               _GPIO(13)
  42 #define TEGRA_PIN_SDMMC3_DAT1_PB6               _GPIO(14)
  43 #define TEGRA_PIN_SDMMC3_DAT0_PB7               _GPIO(15)
  44 #define TEGRA_PIN_UART3_RTS_N_PC0               _GPIO(16)
  45 #define TEGRA_PIN_UART2_TXD_PC2                 _GPIO(18)
  46 #define TEGRA_PIN_UART2_RXD_PC3                 _GPIO(19)
  47 #define TEGRA_PIN_GEN1_I2C_SCL_PC4              _GPIO(20)
  48 #define TEGRA_PIN_GEN1_I2C_SDA_PC5              _GPIO(21)
  49 #define TEGRA_PIN_GMI_WP_N_PC7                  _GPIO(23)
  50 #define TEGRA_PIN_GMI_AD0_PG0                   _GPIO(48)
  51 #define TEGRA_PIN_GMI_AD1_PG1                   _GPIO(49)
  52 #define TEGRA_PIN_GMI_AD2_PG2                   _GPIO(50)
  53 #define TEGRA_PIN_GMI_AD3_PG3                   _GPIO(51)
  54 #define TEGRA_PIN_GMI_AD4_PG4                   _GPIO(52)
  55 #define TEGRA_PIN_GMI_AD5_PG5                   _GPIO(53)
  56 #define TEGRA_PIN_GMI_AD6_PG6                   _GPIO(54)
  57 #define TEGRA_PIN_GMI_AD7_PG7                   _GPIO(55)
  58 #define TEGRA_PIN_GMI_AD8_PH0                   _GPIO(56)
  59 #define TEGRA_PIN_GMI_AD9_PH1                   _GPIO(57)
  60 #define TEGRA_PIN_GMI_AD10_PH2                  _GPIO(58)
  61 #define TEGRA_PIN_GMI_AD11_PH3                  _GPIO(59)
  62 #define TEGRA_PIN_GMI_AD12_PH4                  _GPIO(60)
  63 #define TEGRA_PIN_GMI_AD13_PH5                  _GPIO(61)
  64 #define TEGRA_PIN_GMI_AD14_PH6                  _GPIO(62)
  65 #define TEGRA_PIN_GMI_AD15_PH7                  _GPIO(63)
  66 #define TEGRA_PIN_GMI_WR_N_PI0                  _GPIO(64)
  67 #define TEGRA_PIN_GMI_OE_N_PI1                  _GPIO(65)
  68 #define TEGRA_PIN_GMI_CS6_N_PI3                 _GPIO(67)
  69 #define TEGRA_PIN_GMI_RST_N_PI4                 _GPIO(68)
  70 #define TEGRA_PIN_GMI_IORDY_PI5                 _GPIO(69)
  71 #define TEGRA_PIN_GMI_CS7_N_PI6                 _GPIO(70)
  72 #define TEGRA_PIN_GMI_WAIT_PI7                  _GPIO(71)
  73 #define TEGRA_PIN_GMI_CS0_N_PJ0                 _GPIO(72)
  74 #define TEGRA_PIN_GMI_CS1_N_PJ2                 _GPIO(74)
  75 #define TEGRA_PIN_GMI_DQS_P_PJ3                 _GPIO(75)
  76 #define TEGRA_PIN_UART2_CTS_N_PJ5               _GPIO(77)
  77 #define TEGRA_PIN_UART2_RTS_N_PJ6               _GPIO(78)
  78 #define TEGRA_PIN_GMI_A16_PJ7                   _GPIO(79)
  79 #define TEGRA_PIN_GMI_ADV_N_PK0                 _GPIO(80)
  80 #define TEGRA_PIN_GMI_CLK_PK1                   _GPIO(81)
  81 #define TEGRA_PIN_GMI_CS4_N_PK2                 _GPIO(82)
  82 #define TEGRA_PIN_GMI_CS2_N_PK3                 _GPIO(83)
  83 #define TEGRA_PIN_GMI_CS3_N_PK4                 _GPIO(84)
  84 #define TEGRA_PIN_SPDIF_OUT_PK5                 _GPIO(85)
  85 #define TEGRA_PIN_SPDIF_IN_PK6                  _GPIO(86)
  86 #define TEGRA_PIN_GMI_A19_PK7                   _GPIO(87)
  87 #define TEGRA_PIN_DAP1_FS_PN0                   _GPIO(104)
  88 #define TEGRA_PIN_DAP1_DIN_PN1                  _GPIO(105)
  89 #define TEGRA_PIN_DAP1_DOUT_PN2                 _GPIO(106)
  90 #define TEGRA_PIN_DAP1_SCLK_PN3                 _GPIO(107)
  91 #define TEGRA_PIN_USB_VBUS_EN0_PN4              _GPIO(108)
  92 #define TEGRA_PIN_USB_VBUS_EN1_PN5              _GPIO(109)
  93 #define TEGRA_PIN_HDMI_INT_PN7                  _GPIO(111)
  94 #define TEGRA_PIN_ULPI_DATA7_PO0                _GPIO(112)
  95 #define TEGRA_PIN_ULPI_DATA0_PO1                _GPIO(113)
  96 #define TEGRA_PIN_ULPI_DATA1_PO2                _GPIO(114)
  97 #define TEGRA_PIN_ULPI_DATA2_PO3                _GPIO(115)
  98 #define TEGRA_PIN_ULPI_DATA3_PO4                _GPIO(116)
  99 #define TEGRA_PIN_ULPI_DATA4_PO5                _GPIO(117)
 100 #define TEGRA_PIN_ULPI_DATA5_PO6                _GPIO(118)
 101 #define TEGRA_PIN_ULPI_DATA6_PO7                _GPIO(119)
 102 #define TEGRA_PIN_DAP3_FS_PP0                   _GPIO(120)
 103 #define TEGRA_PIN_DAP3_DIN_PP1                  _GPIO(121)
 104 #define TEGRA_PIN_DAP3_DOUT_PP2                 _GPIO(122)
 105 #define TEGRA_PIN_DAP3_SCLK_PP3                 _GPIO(123)
 106 #define TEGRA_PIN_DAP4_FS_PP4                   _GPIO(124)
 107 #define TEGRA_PIN_DAP4_DIN_PP5                  _GPIO(125)
 108 #define TEGRA_PIN_DAP4_DOUT_PP6                 _GPIO(126)
 109 #define TEGRA_PIN_DAP4_SCLK_PP7                 _GPIO(127)
 110 #define TEGRA_PIN_KB_COL0_PQ0                   _GPIO(128)
 111 #define TEGRA_PIN_KB_COL1_PQ1                   _GPIO(129)
 112 #define TEGRA_PIN_KB_COL2_PQ2                   _GPIO(130)
 113 #define TEGRA_PIN_KB_COL3_PQ3                   _GPIO(131)
 114 #define TEGRA_PIN_KB_COL4_PQ4                   _GPIO(132)
 115 #define TEGRA_PIN_KB_COL5_PQ5                   _GPIO(133)
 116 #define TEGRA_PIN_KB_COL6_PQ6                   _GPIO(134)
 117 #define TEGRA_PIN_KB_COL7_PQ7                   _GPIO(135)
 118 #define TEGRA_PIN_KB_ROW0_PR0                   _GPIO(136)
 119 #define TEGRA_PIN_KB_ROW1_PR1                   _GPIO(137)
 120 #define TEGRA_PIN_KB_ROW2_PR2                   _GPIO(138)
 121 #define TEGRA_PIN_KB_ROW3_PR3                   _GPIO(139)
 122 #define TEGRA_PIN_KB_ROW4_PR4                   _GPIO(140)
 123 #define TEGRA_PIN_KB_ROW5_PR5                   _GPIO(141)
 124 #define TEGRA_PIN_KB_ROW6_PR6                   _GPIO(142)
 125 #define TEGRA_PIN_KB_ROW7_PR7                   _GPIO(143)
 126 #define TEGRA_PIN_KB_ROW8_PS0                   _GPIO(144)
 127 #define TEGRA_PIN_KB_ROW9_PS1                   _GPIO(145)
 128 #define TEGRA_PIN_KB_ROW10_PS2                  _GPIO(146)
 129 #define TEGRA_PIN_GEN2_I2C_SCL_PT5              _GPIO(157)
 130 #define TEGRA_PIN_GEN2_I2C_SDA_PT6              _GPIO(158)
 131 #define TEGRA_PIN_SDMMC4_CMD_PT7                _GPIO(159)
 132 #define TEGRA_PIN_PU0                           _GPIO(160)
 133 #define TEGRA_PIN_PU1                           _GPIO(161)
 134 #define TEGRA_PIN_PU2                           _GPIO(162)
 135 #define TEGRA_PIN_PU3                           _GPIO(163)
 136 #define TEGRA_PIN_PU4                           _GPIO(164)
 137 #define TEGRA_PIN_PU5                           _GPIO(165)
 138 #define TEGRA_PIN_PU6                           _GPIO(166)
 139 #define TEGRA_PIN_PV0                           _GPIO(168)
 140 #define TEGRA_PIN_PV1                           _GPIO(169)
 141 #define TEGRA_PIN_SDMMC3_CD_N_PV2               _GPIO(170)
 142 #define TEGRA_PIN_SDMMC1_WP_N_PV3               _GPIO(171)
 143 #define TEGRA_PIN_DDC_SCL_PV4                   _GPIO(172)
 144 #define TEGRA_PIN_DDC_SDA_PV5                   _GPIO(173)
 145 #define TEGRA_PIN_GPIO_W2_AUD_PW2               _GPIO(178)
 146 #define TEGRA_PIN_GPIO_W3_AUD_PW3               _GPIO(179)
 147 #define TEGRA_PIN_CLK1_OUT_PW4                  _GPIO(180)
 148 #define TEGRA_PIN_CLK2_OUT_PW5                  _GPIO(181)
 149 #define TEGRA_PIN_UART3_TXD_PW6                 _GPIO(182)
 150 #define TEGRA_PIN_UART3_RXD_PW7                 _GPIO(183)
 151 #define TEGRA_PIN_DVFS_PWM_PX0                  _GPIO(184)
 152 #define TEGRA_PIN_GPIO_X1_AUD_PX1               _GPIO(185)
 153 #define TEGRA_PIN_DVFS_CLK_PX2                  _GPIO(186)
 154 #define TEGRA_PIN_GPIO_X3_AUD_PX3               _GPIO(187)
 155 #define TEGRA_PIN_GPIO_X4_AUD_PX4               _GPIO(188)
 156 #define TEGRA_PIN_GPIO_X5_AUD_PX5               _GPIO(189)
 157 #define TEGRA_PIN_GPIO_X6_AUD_PX6               _GPIO(190)
 158 #define TEGRA_PIN_GPIO_X7_AUD_PX7               _GPIO(191)
 159 #define TEGRA_PIN_ULPI_CLK_PY0                  _GPIO(192)
 160 #define TEGRA_PIN_ULPI_DIR_PY1                  _GPIO(193)
 161 #define TEGRA_PIN_ULPI_NXT_PY2                  _GPIO(194)
 162 #define TEGRA_PIN_ULPI_STP_PY3                  _GPIO(195)
 163 #define TEGRA_PIN_SDMMC1_DAT3_PY4               _GPIO(196)
 164 #define TEGRA_PIN_SDMMC1_DAT2_PY5               _GPIO(197)
 165 #define TEGRA_PIN_SDMMC1_DAT1_PY6               _GPIO(198)
 166 #define TEGRA_PIN_SDMMC1_DAT0_PY7               _GPIO(199)
 167 #define TEGRA_PIN_SDMMC1_CLK_PZ0                _GPIO(200)
 168 #define TEGRA_PIN_SDMMC1_CMD_PZ1                _GPIO(201)
 169 #define TEGRA_PIN_SYS_CLK_REQ_PZ5               _GPIO(205)
 170 #define TEGRA_PIN_PWR_I2C_SCL_PZ6               _GPIO(206)
 171 #define TEGRA_PIN_PWR_I2C_SDA_PZ7               _GPIO(207)
 172 #define TEGRA_PIN_SDMMC4_DAT0_PAA0              _GPIO(208)
 173 #define TEGRA_PIN_SDMMC4_DAT1_PAA1              _GPIO(209)
 174 #define TEGRA_PIN_SDMMC4_DAT2_PAA2              _GPIO(210)
 175 #define TEGRA_PIN_SDMMC4_DAT3_PAA3              _GPIO(211)
 176 #define TEGRA_PIN_SDMMC4_DAT4_PAA4              _GPIO(212)
 177 #define TEGRA_PIN_SDMMC4_DAT5_PAA5              _GPIO(213)
 178 #define TEGRA_PIN_SDMMC4_DAT6_PAA6              _GPIO(214)
 179 #define TEGRA_PIN_SDMMC4_DAT7_PAA7              _GPIO(215)
 180 #define TEGRA_PIN_PBB0                          _GPIO(216)
 181 #define TEGRA_PIN_CAM_I2C_SCL_PBB1              _GPIO(217)
 182 #define TEGRA_PIN_CAM_I2C_SDA_PBB2              _GPIO(218)
 183 #define TEGRA_PIN_PBB3                          _GPIO(219)
 184 #define TEGRA_PIN_PBB4                          _GPIO(220)
 185 #define TEGRA_PIN_PBB5                          _GPIO(221)
 186 #define TEGRA_PIN_PBB6                          _GPIO(222)
 187 #define TEGRA_PIN_PBB7                          _GPIO(223)
 188 #define TEGRA_PIN_CAM_MCLK_PCC0                 _GPIO(224)
 189 #define TEGRA_PIN_PCC1                          _GPIO(225)
 190 #define TEGRA_PIN_PCC2                          _GPIO(226)
 191 #define TEGRA_PIN_SDMMC4_CLK_PCC4               _GPIO(228)
 192 #define TEGRA_PIN_CLK2_REQ_PCC5                 _GPIO(229)
 193 #define TEGRA_PIN_CLK3_OUT_PEE0                 _GPIO(240)
 194 #define TEGRA_PIN_CLK3_REQ_PEE1                 _GPIO(241)
 195 #define TEGRA_PIN_CLK1_REQ_PEE2                 _GPIO(242)
 196 #define TEGRA_PIN_HDMI_CEC_PEE3                 _GPIO(243)
 197 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4        _GPIO(244)
 198 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5         _GPIO(245)
 199
 200 /* All non-GPIO pins follow */
 201 #define NUM_GPIOS                               (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
 202 #define _PIN(offset)                            (NUM_GPIOS + (offset))
 203
 204 /* Non-GPIO pins */
 205 #define TEGRA_PIN_CORE_PWR_REQ                  _PIN(0)
 206 #define TEGRA_PIN_CPU_PWR_REQ                   _PIN(1)
 207 #define TEGRA_PIN_PWR_INT_N                     _PIN(2)
 208 #define TEGRA_PIN_RESET_OUT_N                   _PIN(3)
 209 #define TEGRA_PIN_OWR                           _PIN(4)
 210
 211 static const struct pinctrl_pin_desc tegra114_pins[] = {
 212         PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
 213         PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
 214         PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
 215         PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
 216         PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
 217         PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
 218         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
 219         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
 220         PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
 221         PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
 222         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
 223         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
 224         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
 225         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
 226         PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
 227         PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
 228         PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
 229         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
 230         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
 231         PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
 232         PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
 233         PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
 234         PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
 235         PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
 236         PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
 237         PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
 238         PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
 239         PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
 240         PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
 241         PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
 242         PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
 243         PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
 244         PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
 245         PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
 246         PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
 247         PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
 248         PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
 249         PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
 250         PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
 251         PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
 252         PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
 253         PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
 254         PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
 255         PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
 256         PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
 257         PINCTRL_PIN(TEGRA_PIN_GMI_DQS_P_PJ3, "GMI_DQS_P PJ3"),
 258         PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
 259         PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
 260         PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
 261         PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
 262         PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
 263         PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
 264         PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
 265         PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
 266         PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
 267         PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
 268         PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
 269         PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
 270         PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
 271         PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
 272         PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
 273         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
 274         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
 275         PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
 276         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
 277         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
 278         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
 279         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
 280         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
 281         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
 282         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
 283         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
 284         PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
 285         PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
 286         PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
 287         PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
 288         PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
 289         PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
 290         PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
 291         PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
 292         PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
 293         PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
 294         PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
 295         PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
 296         PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
 297         PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
 298         PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
 299         PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
 300         PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
 301         PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
 302         PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
 303         PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
 304         PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
 305         PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
 306         PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
 307         PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
 308         PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
 309         PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
 310         PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
 311         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
 312         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
 313         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
 314         PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
 315         PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
 316         PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
 317         PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
 318         PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
 319         PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
 320         PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
 321         PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
 322         PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
 323         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
 324         PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
 325         PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
 326         PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
 327         PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
 328         PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
 329         PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
 330         PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
 331         PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
 332         PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
 333         PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
 334         PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
 335         PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
 336         PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
 337         PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
 338         PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
 339         PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
 340         PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
 341         PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
 342         PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
 343         PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
 344         PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
 345         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
 346         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
 347         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
 348         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
 349         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
 350         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
 351         PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
 352         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
 353         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
 354         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
 355         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
 356         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
 357         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
 358         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
 359         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
 360         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
 361         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
 362         PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
 363         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
 364         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
 365         PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
 366         PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
 367         PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
 368         PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
 369         PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
 370         PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
 371         PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
 372         PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
 373         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
 374         PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
 375         PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
 376         PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
 377         PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
 378         PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
 379         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
 380         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
 381         PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
 382         PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
 383         PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
 384         PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
 385         PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
 386 };
 387
 388 static const unsigned clk_32k_out_pa0_pins[] = {
 389         TEGRA_PIN_CLK_32K_OUT_PA0,
 390 };
 391
 392 static const unsigned uart3_cts_n_pa1_pins[] = {
 393         TEGRA_PIN_UART3_CTS_N_PA1,
 394 };
 395
 396 static const unsigned dap2_fs_pa2_pins[] = {
 397         TEGRA_PIN_DAP2_FS_PA2,
 398 };
 399
 400 static const unsigned dap2_sclk_pa3_pins[] = {
 401         TEGRA_PIN_DAP2_SCLK_PA3,
 402 };
 403
 404 static const unsigned dap2_din_pa4_pins[] = {
 405         TEGRA_PIN_DAP2_DIN_PA4,
 406 };
 407
 408 static const unsigned dap2_dout_pa5_pins[] = {
 409         TEGRA_PIN_DAP2_DOUT_PA5,
 410 };
 411
 412 static const unsigned sdmmc3_clk_pa6_pins[] = {
 413         TEGRA_PIN_SDMMC3_CLK_PA6,
 414 };
 415
 416 static const unsigned sdmmc3_cmd_pa7_pins[] = {
 417         TEGRA_PIN_SDMMC3_CMD_PA7,
 418 };
 419
 420 static const unsigned gmi_a17_pb0_pins[] = {
 421         TEGRA_PIN_GMI_A17_PB0,
 422 };
 423
 424 static const unsigned gmi_a18_pb1_pins[] = {
 425         TEGRA_PIN_GMI_A18_PB1,
 426 };
 427
 428 static const unsigned sdmmc3_dat3_pb4_pins[] = {
 429         TEGRA_PIN_SDMMC3_DAT3_PB4,
 430 };
 431
 432 static const unsigned sdmmc3_dat2_pb5_pins[] = {
 433         TEGRA_PIN_SDMMC3_DAT2_PB5,
 434 };
 435
 436 static const unsigned sdmmc3_dat1_pb6_pins[] = {
 437         TEGRA_PIN_SDMMC3_DAT1_PB6,
 438 };
 439
 440 static const unsigned sdmmc3_dat0_pb7_pins[] = {
 441         TEGRA_PIN_SDMMC3_DAT0_PB7,
 442 };
 443
 444 static const unsigned uart3_rts_n_pc0_pins[] = {
 445         TEGRA_PIN_UART3_RTS_N_PC0,
 446 };
 447
 448 static const unsigned uart2_txd_pc2_pins[] = {
 449         TEGRA_PIN_UART2_TXD_PC2,
 450 };
 451
 452 static const unsigned uart2_rxd_pc3_pins[] = {
 453         TEGRA_PIN_UART2_RXD_PC3,
 454 };
 455
 456 static const unsigned gen1_i2c_scl_pc4_pins[] = {
 457         TEGRA_PIN_GEN1_I2C_SCL_PC4,
 458 };
 459
 460 static const unsigned gen1_i2c_sda_pc5_pins[] = {
 461         TEGRA_PIN_GEN1_I2C_SDA_PC5,
 462 };
 463
 464 static const unsigned gmi_wp_n_pc7_pins[] = {
 465         TEGRA_PIN_GMI_WP_N_PC7,
 466 };
 467
 468 static const unsigned gmi_ad0_pg0_pins[] = {
 469         TEGRA_PIN_GMI_AD0_PG0,
 470 };
 471
 472 static const unsigned gmi_ad1_pg1_pins[] = {
 473         TEGRA_PIN_GMI_AD1_PG1,
 474 };
 475
 476 static const unsigned gmi_ad2_pg2_pins[] = {
 477         TEGRA_PIN_GMI_AD2_PG2,
 478 };
 479
 480 static const unsigned gmi_ad3_pg3_pins[] = {
 481         TEGRA_PIN_GMI_AD3_PG3,
 482 };
 483
 484 static const unsigned gmi_ad4_pg4_pins[] = {
 485         TEGRA_PIN_GMI_AD4_PG4,
 486 };
 487
 488 static const unsigned gmi_ad5_pg5_pins[] = {
 489         TEGRA_PIN_GMI_AD5_PG5,
 490 };
 491
 492 static const unsigned gmi_ad6_pg6_pins[] = {
 493         TEGRA_PIN_GMI_AD6_PG6,
 494 };
 495
 496 static const unsigned gmi_ad7_pg7_pins[] = {
 497         TEGRA_PIN_GMI_AD7_PG7,
 498 };
 499
 500 static const unsigned gmi_ad8_ph0_pins[] = {
 501         TEGRA_PIN_GMI_AD8_PH0,
 502 };
 503
 504 static const unsigned gmi_ad9_ph1_pins[] = {
 505         TEGRA_PIN_GMI_AD9_PH1,
 506 };
 507
 508 static const unsigned gmi_ad10_ph2_pins[] = {
 509         TEGRA_PIN_GMI_AD10_PH2,
 510 };
 511
 512 static const unsigned gmi_ad11_ph3_pins[] = {
 513         TEGRA_PIN_GMI_AD11_PH3,
 514 };
 515
 516 static const unsigned gmi_ad12_ph4_pins[] = {
 517         TEGRA_PIN_GMI_AD12_PH4,
 518 };
 519
 520 static const unsigned gmi_ad13_ph5_pins[] = {
 521         TEGRA_PIN_GMI_AD13_PH5,
 522 };
 523
 524 static const unsigned gmi_ad14_ph6_pins[] = {
 525         TEGRA_PIN_GMI_AD14_PH6,
 526 };
 527
 528 static const unsigned gmi_ad15_ph7_pins[] = {
 529         TEGRA_PIN_GMI_AD15_PH7,
 530 };
 531
 532 static const unsigned gmi_wr_n_pi0_pins[] = {
 533         TEGRA_PIN_GMI_WR_N_PI0,
 534 };
 535
 536 static const unsigned gmi_oe_n_pi1_pins[] = {
 537         TEGRA_PIN_GMI_OE_N_PI1,
 538 };
 539
 540 static const unsigned gmi_cs6_n_pi3_pins[] = {
 541         TEGRA_PIN_GMI_CS6_N_PI3,
 542 };
 543
 544 static const unsigned gmi_rst_n_pi4_pins[] = {
 545         TEGRA_PIN_GMI_RST_N_PI4,
 546 };
 547
 548 static const unsigned gmi_iordy_pi5_pins[] = {
 549         TEGRA_PIN_GMI_IORDY_PI5,
 550 };
 551
 552 static const unsigned gmi_cs7_n_pi6_pins[] = {
 553         TEGRA_PIN_GMI_CS7_N_PI6,
 554 };
 555
 556 static const unsigned gmi_wait_pi7_pins[] = {
 557         TEGRA_PIN_GMI_WAIT_PI7,
 558 };
 559
 560 static const unsigned gmi_cs0_n_pj0_pins[] = {
 561         TEGRA_PIN_GMI_CS0_N_PJ0,
 562 };
 563
 564 static const unsigned gmi_cs1_n_pj2_pins[] = {
 565         TEGRA_PIN_GMI_CS1_N_PJ2,
 566 };
 567
 568 static const unsigned gmi_dqs_p_pj3_pins[] = {
 569         TEGRA_PIN_GMI_DQS_P_PJ3,
 570 };
 571
 572 static const unsigned uart2_cts_n_pj5_pins[] = {
 573         TEGRA_PIN_UART2_CTS_N_PJ5,
 574 };
 575
 576 static const unsigned uart2_rts_n_pj6_pins[] = {
 577         TEGRA_PIN_UART2_RTS_N_PJ6,
 578 };
 579
 580 static const unsigned gmi_a16_pj7_pins[] = {
 581         TEGRA_PIN_GMI_A16_PJ7,
 582 };
 583
 584 static const unsigned gmi_adv_n_pk0_pins[] = {
 585         TEGRA_PIN_GMI_ADV_N_PK0,
 586 };
 587
 588 static const unsigned gmi_clk_pk1_pins[] = {
 589         TEGRA_PIN_GMI_CLK_PK1,
 590 };
 591
 592 static const unsigned gmi_cs4_n_pk2_pins[] = {
 593         TEGRA_PIN_GMI_CS4_N_PK2,
 594 };
 595
 596 static const unsigned gmi_cs2_n_pk3_pins[] = {
 597         TEGRA_PIN_GMI_CS2_N_PK3,
 598 };
 599
 600 static const unsigned gmi_cs3_n_pk4_pins[] = {
 601         TEGRA_PIN_GMI_CS3_N_PK4,
 602 };
 603
 604 static const unsigned spdif_out_pk5_pins[] = {
 605         TEGRA_PIN_SPDIF_OUT_PK5,
 606 };
 607
 608 static const unsigned spdif_in_pk6_pins[] = {
 609         TEGRA_PIN_SPDIF_IN_PK6,
 610 };
 611
 612 static const unsigned gmi_a19_pk7_pins[] = {
 613         TEGRA_PIN_GMI_A19_PK7,
 614 };
 615
 616 static const unsigned dap1_fs_pn0_pins[] = {
 617         TEGRA_PIN_DAP1_FS_PN0,
 618 };
 619
 620 static const unsigned dap1_din_pn1_pins[] = {
 621         TEGRA_PIN_DAP1_DIN_PN1,
 622 };
 623
 624 static const unsigned dap1_dout_pn2_pins[] = {
 625         TEGRA_PIN_DAP1_DOUT_PN2,
 626 };
 627
 628 static const unsigned dap1_sclk_pn3_pins[] = {
 629         TEGRA_PIN_DAP1_SCLK_PN3,
 630 };
 631
 632 static const unsigned usb_vbus_en0_pn4_pins[] = {
 633         TEGRA_PIN_USB_VBUS_EN0_PN4,
 634 };
 635
 636 static const unsigned usb_vbus_en1_pn5_pins[] = {
 637         TEGRA_PIN_USB_VBUS_EN1_PN5,
 638 };
 639
 640 static const unsigned hdmi_int_pn7_pins[] = {
 641         TEGRA_PIN_HDMI_INT_PN7,
 642 };
 643
 644 static const unsigned ulpi_data7_po0_pins[] = {
 645         TEGRA_PIN_ULPI_DATA7_PO0,
 646 };
 647
 648 static const unsigned ulpi_data0_po1_pins[] = {
 649         TEGRA_PIN_ULPI_DATA0_PO1,
 650 };
 651
 652 static const unsigned ulpi_data1_po2_pins[] = {
 653         TEGRA_PIN_ULPI_DATA1_PO2,
 654 };
 655
 656 static const unsigned ulpi_data2_po3_pins[] = {
 657         TEGRA_PIN_ULPI_DATA2_PO3,
 658 };
 659
 660 static const unsigned ulpi_data3_po4_pins[] = {
 661         TEGRA_PIN_ULPI_DATA3_PO4,
 662 };
 663
 664 static const unsigned ulpi_data4_po5_pins[] = {
 665         TEGRA_PIN_ULPI_DATA4_PO5,
 666 };
 667
 668 static const unsigned ulpi_data5_po6_pins[] = {
 669         TEGRA_PIN_ULPI_DATA5_PO6,
 670 };
 671
 672 static const unsigned ulpi_data6_po7_pins[] = {
 673         TEGRA_PIN_ULPI_DATA6_PO7,
 674 };
 675
 676 static const unsigned dap3_fs_pp0_pins[] = {
 677         TEGRA_PIN_DAP3_FS_PP0,
 678 };
 679
 680 static const unsigned dap3_din_pp1_pins[] = {
 681         TEGRA_PIN_DAP3_DIN_PP1,
 682 };
 683
 684 static const unsigned dap3_dout_pp2_pins[] = {
 685         TEGRA_PIN_DAP3_DOUT_PP2,
 686 };
 687
 688 static const unsigned dap3_sclk_pp3_pins[] = {
 689         TEGRA_PIN_DAP3_SCLK_PP3,
 690 };
 691
 692 static const unsigned dap4_fs_pp4_pins[] = {
 693         TEGRA_PIN_DAP4_FS_PP4,
 694 };
 695
 696 static const unsigned dap4_din_pp5_pins[] = {
 697         TEGRA_PIN_DAP4_DIN_PP5,
 698 };
 699
 700 static const unsigned dap4_dout_pp6_pins[] = {
 701         TEGRA_PIN_DAP4_DOUT_PP6,
 702 };
 703
 704 static const unsigned dap4_sclk_pp7_pins[] = {
 705         TEGRA_PIN_DAP4_SCLK_PP7,
 706 };
 707
 708 static const unsigned kb_col0_pq0_pins[] = {
 709         TEGRA_PIN_KB_COL0_PQ0,
 710 };
 711
 712 static const unsigned kb_col1_pq1_pins[] = {
 713         TEGRA_PIN_KB_COL1_PQ1,
 714 };
 715
 716 static const unsigned kb_col2_pq2_pins[] = {
 717         TEGRA_PIN_KB_COL2_PQ2,
 718 };
 719
 720 static const unsigned kb_col3_pq3_pins[] = {
 721         TEGRA_PIN_KB_COL3_PQ3,
 722 };
 723
 724 static const unsigned kb_col4_pq4_pins[] = {
 725         TEGRA_PIN_KB_COL4_PQ4,
 726 };
 727
 728 static const unsigned kb_col5_pq5_pins[] = {
 729         TEGRA_PIN_KB_COL5_PQ5,
 730 };
 731
 732 static const unsigned kb_col6_pq6_pins[] = {
 733         TEGRA_PIN_KB_COL6_PQ6,
 734 };
 735
 736 static const unsigned kb_col7_pq7_pins[] = {
 737         TEGRA_PIN_KB_COL7_PQ7,
 738 };
 739
 740 static const unsigned kb_row0_pr0_pins[] = {
 741         TEGRA_PIN_KB_ROW0_PR0,
 742 };
 743
 744 static const unsigned kb_row1_pr1_pins[] = {
 745         TEGRA_PIN_KB_ROW1_PR1,
 746 };
 747
 748 static const unsigned kb_row2_pr2_pins[] = {
 749         TEGRA_PIN_KB_ROW2_PR2,
 750 };
 751
 752 static const unsigned kb_row3_pr3_pins[] = {
 753         TEGRA_PIN_KB_ROW3_PR3,
 754 };
 755
 756 static const unsigned kb_row4_pr4_pins[] = {
 757         TEGRA_PIN_KB_ROW4_PR4,
 758 };
 759
 760 static const unsigned kb_row5_pr5_pins[] = {
 761         TEGRA_PIN_KB_ROW5_PR5,
 762 };
 763
 764 static const unsigned kb_row6_pr6_pins[] = {
 765         TEGRA_PIN_KB_ROW6_PR6,
 766 };
 767
 768 static const unsigned kb_row7_pr7_pins[] = {
 769         TEGRA_PIN_KB_ROW7_PR7,
 770 };
 771
 772 static const unsigned kb_row8_ps0_pins[] = {
 773         TEGRA_PIN_KB_ROW8_PS0,
 774 };
 775
 776 static const unsigned kb_row9_ps1_pins[] = {
 777         TEGRA_PIN_KB_ROW9_PS1,
 778 };
 779
 780 static const unsigned kb_row10_ps2_pins[] = {
 781         TEGRA_PIN_KB_ROW10_PS2,
 782 };
 783
 784 static const unsigned gen2_i2c_scl_pt5_pins[] = {
 785         TEGRA_PIN_GEN2_I2C_SCL_PT5,
 786 };
 787
 788 static const unsigned gen2_i2c_sda_pt6_pins[] = {
 789         TEGRA_PIN_GEN2_I2C_SDA_PT6,
 790 };
 791
 792 static const unsigned sdmmc4_cmd_pt7_pins[] = {
 793         TEGRA_PIN_SDMMC4_CMD_PT7,
 794 };
 795
 796 static const unsigned pu0_pins[] = {
 797         TEGRA_PIN_PU0,
 798 };
 799
 800 static const unsigned pu1_pins[] = {
 801         TEGRA_PIN_PU1,
 802 };
 803
 804 static const unsigned pu2_pins[] = {
 805         TEGRA_PIN_PU2,
 806 };
 807
 808 static const unsigned pu3_pins[] = {
 809         TEGRA_PIN_PU3,
 810 };
 811
 812 static const unsigned pu4_pins[] = {
 813         TEGRA_PIN_PU4,
 814 };
 815
 816 static const unsigned pu5_pins[] = {
 817         TEGRA_PIN_PU5,
 818 };
 819
 820 static const unsigned pu6_pins[] = {
 821         TEGRA_PIN_PU6,
 822 };
 823
 824 static const unsigned pv0_pins[] = {
 825         TEGRA_PIN_PV0,
 826 };
 827
 828 static const unsigned pv1_pins[] = {
 829         TEGRA_PIN_PV1,
 830 };
 831
 832 static const unsigned sdmmc3_cd_n_pv2_pins[] = {
 833         TEGRA_PIN_SDMMC3_CD_N_PV2,
 834 };
 835
 836 static const unsigned sdmmc1_wp_n_pv3_pins[] = {
 837         TEGRA_PIN_SDMMC1_WP_N_PV3,
 838 };
 839
 840 static const unsigned ddc_scl_pv4_pins[] = {
 841         TEGRA_PIN_DDC_SCL_PV4,
 842 };
 843
 844 static const unsigned ddc_sda_pv5_pins[] = {
 845         TEGRA_PIN_DDC_SDA_PV5,
 846 };
 847
 848 static const unsigned gpio_w2_aud_pw2_pins[] = {
 849         TEGRA_PIN_GPIO_W2_AUD_PW2,
 850 };
 851
 852 static const unsigned gpio_w3_aud_pw3_pins[] = {
 853         TEGRA_PIN_GPIO_W3_AUD_PW3,
 854 };
 855
 856 static const unsigned clk1_out_pw4_pins[] = {
 857         TEGRA_PIN_CLK1_OUT_PW4,
 858 };
 859
 860 static const unsigned clk2_out_pw5_pins[] = {
 861         TEGRA_PIN_CLK2_OUT_PW5,
 862 };
 863
 864 static const unsigned uart3_txd_pw6_pins[] = {
 865         TEGRA_PIN_UART3_TXD_PW6,
 866 };
 867
 868 static const unsigned uart3_rxd_pw7_pins[] = {
 869         TEGRA_PIN_UART3_RXD_PW7,
 870 };
 871
 872 static const unsigned dvfs_pwm_px0_pins[] = {
 873         TEGRA_PIN_DVFS_PWM_PX0,
 874 };
 875
 876 static const unsigned gpio_x1_aud_px1_pins[] = {
 877         TEGRA_PIN_GPIO_X1_AUD_PX1,
 878 };
 879
 880 static const unsigned dvfs_clk_px2_pins[] = {
 881         TEGRA_PIN_DVFS_CLK_PX2,
 882 };
 883
 884 static const unsigned gpio_x3_aud_px3_pins[] = {
 885         TEGRA_PIN_GPIO_X3_AUD_PX3,
 886 };
 887
 888 static const unsigned gpio_x4_aud_px4_pins[] = {
 889         TEGRA_PIN_GPIO_X4_AUD_PX4,
 890 };
 891
 892 static const unsigned gpio_x5_aud_px5_pins[] = {
 893         TEGRA_PIN_GPIO_X5_AUD_PX5,
 894 };
 895
 896 static const unsigned gpio_x6_aud_px6_pins[] = {
 897         TEGRA_PIN_GPIO_X6_AUD_PX6,
 898 };
 899
 900 static const unsigned gpio_x7_aud_px7_pins[] = {
 901         TEGRA_PIN_GPIO_X7_AUD_PX7,
 902 };
 903
 904 static const unsigned ulpi_clk_py0_pins[] = {
 905         TEGRA_PIN_ULPI_CLK_PY0,
 906 };
 907
 908 static const unsigned ulpi_dir_py1_pins[] = {
 909         TEGRA_PIN_ULPI_DIR_PY1,
 910 };
 911
 912 static const unsigned ulpi_nxt_py2_pins[] = {
 913         TEGRA_PIN_ULPI_NXT_PY2,
 914 };
 915
 916 static const unsigned ulpi_stp_py3_pins[] = {
 917         TEGRA_PIN_ULPI_STP_PY3,
 918 };
 919
 920 static const unsigned sdmmc1_dat3_py4_pins[] = {
 921         TEGRA_PIN_SDMMC1_DAT3_PY4,
 922 };
 923
 924 static const unsigned sdmmc1_dat2_py5_pins[] = {
 925         TEGRA_PIN_SDMMC1_DAT2_PY5,
 926 };
 927
 928 static const unsigned sdmmc1_dat1_py6_pins[] = {
 929         TEGRA_PIN_SDMMC1_DAT1_PY6,
 930 };
 931
 932 static const unsigned sdmmc1_dat0_py7_pins[] = {
 933         TEGRA_PIN_SDMMC1_DAT0_PY7,
 934 };
 935
 936 static const unsigned sdmmc1_clk_pz0_pins[] = {
 937         TEGRA_PIN_SDMMC1_CLK_PZ0,
 938 };
 939
 940 static const unsigned sdmmc1_cmd_pz1_pins[] = {
 941         TEGRA_PIN_SDMMC1_CMD_PZ1,
 942 };
 943
 944 static const unsigned sys_clk_req_pz5_pins[] = {
 945         TEGRA_PIN_SYS_CLK_REQ_PZ5,
 946 };
 947
 948 static const unsigned pwr_i2c_scl_pz6_pins[] = {
 949         TEGRA_PIN_PWR_I2C_SCL_PZ6,
 950 };
 951
 952 static const unsigned pwr_i2c_sda_pz7_pins[] = {
 953         TEGRA_PIN_PWR_I2C_SDA_PZ7,
 954 };
 955
 956 static const unsigned sdmmc4_dat0_paa0_pins[] = {
 957         TEGRA_PIN_SDMMC4_DAT0_PAA0,
 958 };
 959
 960 static const unsigned sdmmc4_dat1_paa1_pins[] = {
 961         TEGRA_PIN_SDMMC4_DAT1_PAA1,
 962 };
 963
 964 static const unsigned sdmmc4_dat2_paa2_pins[] = {
 965         TEGRA_PIN_SDMMC4_DAT2_PAA2,
 966 };
 967
 968 static const unsigned sdmmc4_dat3_paa3_pins[] = {
 969         TEGRA_PIN_SDMMC4_DAT3_PAA3,
 970 };
 971
 972 static const unsigned sdmmc4_dat4_paa4_pins[] = {
 973         TEGRA_PIN_SDMMC4_DAT4_PAA4,
 974 };
 975
 976 static const unsigned sdmmc4_dat5_paa5_pins[] = {
 977         TEGRA_PIN_SDMMC4_DAT5_PAA5,
 978 };
 979
 980 static const unsigned sdmmc4_dat6_paa6_pins[] = {
 981         TEGRA_PIN_SDMMC4_DAT6_PAA6,
 982 };
 983
 984 static const unsigned sdmmc4_dat7_paa7_pins[] = {
 985         TEGRA_PIN_SDMMC4_DAT7_PAA7,
 986 };
 987
 988 static const unsigned pbb0_pins[] = {
 989         TEGRA_PIN_PBB0,
 990 };
 991
 992 static const unsigned cam_i2c_scl_pbb1_pins[] = {
 993         TEGRA_PIN_CAM_I2C_SCL_PBB1,
 994 };
 995
 996 static const unsigned cam_i2c_sda_pbb2_pins[] = {
 997         TEGRA_PIN_CAM_I2C_SDA_PBB2,
 998 };
 999
1000 static const unsigned pbb3_pins[] = {
1001         TEGRA_PIN_PBB3,
1002 };
1003
1004 static const unsigned pbb4_pins[] = {
1005         TEGRA_PIN_PBB4,
1006 };
1007
1008 static const unsigned pbb5_pins[] = {
1009         TEGRA_PIN_PBB5,
1010 };
1011
1012 static const unsigned pbb6_pins[] = {
1013         TEGRA_PIN_PBB6,
1014 };
1015
1016 static const unsigned pbb7_pins[] = {
1017         TEGRA_PIN_PBB7,
1018 };
1019
1020 static const unsigned cam_mclk_pcc0_pins[] = {
1021         TEGRA_PIN_CAM_MCLK_PCC0,
1022 };
1023
1024 static const unsigned pcc1_pins[] = {
1025         TEGRA_PIN_PCC1,
1026 };
1027
1028 static const unsigned pcc2_pins[] = {
1029         TEGRA_PIN_PCC2,
1030 };
1031
1032 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1033         TEGRA_PIN_SDMMC4_CLK_PCC4,
1034 };
1035
1036 static const unsigned clk2_req_pcc5_pins[] = {
1037         TEGRA_PIN_CLK2_REQ_PCC5,
1038 };
1039
1040 static const unsigned clk3_out_pee0_pins[] = {
1041         TEGRA_PIN_CLK3_OUT_PEE0,
1042 };
1043
1044 static const unsigned clk3_req_pee1_pins[] = {
1045         TEGRA_PIN_CLK3_REQ_PEE1,
1046 };
1047
1048 static const unsigned clk1_req_pee2_pins[] = {
1049         TEGRA_PIN_CLK1_REQ_PEE2,
1050 };
1051
1052 static const unsigned hdmi_cec_pee3_pins[] = {
1053         TEGRA_PIN_HDMI_CEC_PEE3,
1054 };
1055
1056 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1057         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1058 };
1059
1060 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1061         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1062 };
1063
1064 static const unsigned core_pwr_req_pins[] = {
1065         TEGRA_PIN_CORE_PWR_REQ,
1066 };
1067
1068 static const unsigned cpu_pwr_req_pins[] = {
1069         TEGRA_PIN_CPU_PWR_REQ,
1070 };
1071
1072 static const unsigned pwr_int_n_pins[] = {
1073         TEGRA_PIN_PWR_INT_N,
1074 };
1075
1076 static const unsigned reset_out_n_pins[] = {
1077         TEGRA_PIN_RESET_OUT_N,
1078 };
1079
1080 static const unsigned owr_pins[] = {
1081         TEGRA_PIN_OWR,
1082 };
1083
1084 static const unsigned drive_ao1_pins[] = {
1085         TEGRA_PIN_KB_ROW0_PR0,
1086         TEGRA_PIN_KB_ROW1_PR1,
1087         TEGRA_PIN_KB_ROW2_PR2,
1088         TEGRA_PIN_KB_ROW3_PR3,
1089         TEGRA_PIN_KB_ROW4_PR4,
1090         TEGRA_PIN_KB_ROW5_PR5,
1091         TEGRA_PIN_KB_ROW6_PR6,
1092         TEGRA_PIN_KB_ROW7_PR7,
1093         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1094         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1095 };
1096
1097 static const unsigned drive_ao2_pins[] = {
1098         TEGRA_PIN_CLK_32K_OUT_PA0,
1099         TEGRA_PIN_KB_COL0_PQ0,
1100         TEGRA_PIN_KB_COL1_PQ1,
1101         TEGRA_PIN_KB_COL2_PQ2,
1102         TEGRA_PIN_KB_COL3_PQ3,
1103         TEGRA_PIN_KB_COL4_PQ4,
1104         TEGRA_PIN_KB_COL5_PQ5,
1105         TEGRA_PIN_KB_COL6_PQ6,
1106         TEGRA_PIN_KB_COL7_PQ7,
1107         TEGRA_PIN_KB_ROW8_PS0,
1108         TEGRA_PIN_KB_ROW9_PS1,
1109         TEGRA_PIN_KB_ROW10_PS2,
1110         TEGRA_PIN_SYS_CLK_REQ_PZ5,
1111         TEGRA_PIN_CORE_PWR_REQ,
1112         TEGRA_PIN_CPU_PWR_REQ,
1113         TEGRA_PIN_RESET_OUT_N,
1114 };
1115
1116 static const unsigned drive_at1_pins[] = {
1117         TEGRA_PIN_GMI_AD8_PH0,
1118         TEGRA_PIN_GMI_AD9_PH1,
1119         TEGRA_PIN_GMI_AD10_PH2,
1120         TEGRA_PIN_GMI_AD11_PH3,
1121         TEGRA_PIN_GMI_AD12_PH4,
1122         TEGRA_PIN_GMI_AD13_PH5,
1123         TEGRA_PIN_GMI_AD14_PH6,
1124         TEGRA_PIN_GMI_AD15_PH7,
1125         TEGRA_PIN_GMI_IORDY_PI5,
1126         TEGRA_PIN_GMI_CS7_N_PI6,
1127 };
1128
1129 static const unsigned drive_at2_pins[] = {
1130         TEGRA_PIN_GMI_AD0_PG0,
1131         TEGRA_PIN_GMI_AD1_PG1,
1132         TEGRA_PIN_GMI_AD2_PG2,
1133         TEGRA_PIN_GMI_AD3_PG3,
1134         TEGRA_PIN_GMI_AD4_PG4,
1135         TEGRA_PIN_GMI_AD5_PG5,
1136         TEGRA_PIN_GMI_AD6_PG6,
1137         TEGRA_PIN_GMI_AD7_PG7,
1138         TEGRA_PIN_GMI_WR_N_PI0,
1139         TEGRA_PIN_GMI_OE_N_PI1,
1140         TEGRA_PIN_GMI_CS6_N_PI3,
1141         TEGRA_PIN_GMI_RST_N_PI4,
1142         TEGRA_PIN_GMI_WAIT_PI7,
1143         TEGRA_PIN_GMI_DQS_P_PJ3,
1144         TEGRA_PIN_GMI_ADV_N_PK0,
1145         TEGRA_PIN_GMI_CLK_PK1,
1146         TEGRA_PIN_GMI_CS4_N_PK2,
1147         TEGRA_PIN_GMI_CS2_N_PK3,
1148         TEGRA_PIN_GMI_CS3_N_PK4,
1149 };
1150
1151 static const unsigned drive_at3_pins[] = {
1152         TEGRA_PIN_GMI_WP_N_PC7,
1153         TEGRA_PIN_GMI_CS0_N_PJ0,
1154 };
1155
1156 static const unsigned drive_at4_pins[] = {
1157         TEGRA_PIN_GMI_A17_PB0,
1158         TEGRA_PIN_GMI_A18_PB1,
1159         TEGRA_PIN_GMI_CS1_N_PJ2,
1160         TEGRA_PIN_GMI_A16_PJ7,
1161         TEGRA_PIN_GMI_A19_PK7,
1162 };
1163
1164 static const unsigned drive_at5_pins[] = {
1165         TEGRA_PIN_GEN2_I2C_SCL_PT5,
1166         TEGRA_PIN_GEN2_I2C_SDA_PT6,
1167 };
1168
1169 static const unsigned drive_cdev1_pins[] = {
1170         TEGRA_PIN_CLK1_OUT_PW4,
1171         TEGRA_PIN_CLK1_REQ_PEE2,
1172 };
1173
1174 static const unsigned drive_cdev2_pins[] = {
1175         TEGRA_PIN_CLK2_OUT_PW5,
1176         TEGRA_PIN_CLK2_REQ_PCC5,
1177         TEGRA_PIN_SDMMC1_WP_N_PV3,
1178 };
1179
1180 static const unsigned drive_dap1_pins[] = {
1181         TEGRA_PIN_DAP1_FS_PN0,
1182         TEGRA_PIN_DAP1_DIN_PN1,
1183         TEGRA_PIN_DAP1_DOUT_PN2,
1184         TEGRA_PIN_DAP1_SCLK_PN3,
1185 };
1186
1187 static const unsigned drive_dap2_pins[] = {
1188         TEGRA_PIN_DAP2_FS_PA2,
1189         TEGRA_PIN_DAP2_SCLK_PA3,
1190         TEGRA_PIN_DAP2_DIN_PA4,
1191         TEGRA_PIN_DAP2_DOUT_PA5,
1192 };
1193
1194 static const unsigned drive_dap3_pins[] = {
1195         TEGRA_PIN_DAP3_FS_PP0,
1196         TEGRA_PIN_DAP3_DIN_PP1,
1197         TEGRA_PIN_DAP3_DOUT_PP2,
1198         TEGRA_PIN_DAP3_SCLK_PP3,
1199 };
1200
1201 static const unsigned drive_dap4_pins[] = {
1202         TEGRA_PIN_DAP4_FS_PP4,
1203         TEGRA_PIN_DAP4_DIN_PP5,
1204         TEGRA_PIN_DAP4_DOUT_PP6,
1205         TEGRA_PIN_DAP4_SCLK_PP7,
1206 };
1207
1208 static const unsigned drive_dbg_pins[] = {
1209         TEGRA_PIN_GEN1_I2C_SCL_PC4,
1210         TEGRA_PIN_GEN1_I2C_SDA_PC5,
1211         TEGRA_PIN_PU0,
1212         TEGRA_PIN_PU1,
1213         TEGRA_PIN_PU2,
1214         TEGRA_PIN_PU3,
1215         TEGRA_PIN_PU4,
1216         TEGRA_PIN_PU5,
1217         TEGRA_PIN_PU6,
1218 };
1219
1220 static const unsigned drive_sdio3_pins[] = {
1221         TEGRA_PIN_SDMMC3_CLK_PA6,
1222         TEGRA_PIN_SDMMC3_CMD_PA7,
1223         TEGRA_PIN_SDMMC3_DAT3_PB4,
1224         TEGRA_PIN_SDMMC3_DAT2_PB5,
1225         TEGRA_PIN_SDMMC3_DAT1_PB6,
1226         TEGRA_PIN_SDMMC3_DAT0_PB7,
1227         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1228         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1229 };
1230
1231 static const unsigned drive_spi_pins[] = {
1232         TEGRA_PIN_DVFS_PWM_PX0,
1233         TEGRA_PIN_GPIO_X1_AUD_PX1,
1234         TEGRA_PIN_DVFS_CLK_PX2,
1235         TEGRA_PIN_GPIO_X3_AUD_PX3,
1236         TEGRA_PIN_GPIO_X4_AUD_PX4,
1237         TEGRA_PIN_GPIO_X5_AUD_PX5,
1238         TEGRA_PIN_GPIO_X6_AUD_PX6,
1239         TEGRA_PIN_GPIO_X7_AUD_PX7,
1240         TEGRA_PIN_GPIO_W2_AUD_PW2,
1241         TEGRA_PIN_GPIO_W3_AUD_PW3,
1242 };
1243
1244 static const unsigned drive_uaa_pins[] = {
1245         TEGRA_PIN_ULPI_DATA0_PO1,
1246         TEGRA_PIN_ULPI_DATA1_PO2,
1247         TEGRA_PIN_ULPI_DATA2_PO3,
1248         TEGRA_PIN_ULPI_DATA3_PO4,
1249 };
1250
1251 static const unsigned drive_uab_pins[] = {
1252         TEGRA_PIN_ULPI_DATA7_PO0,
1253         TEGRA_PIN_ULPI_DATA4_PO5,
1254         TEGRA_PIN_ULPI_DATA5_PO6,
1255         TEGRA_PIN_ULPI_DATA6_PO7,
1256         TEGRA_PIN_PV0,
1257         TEGRA_PIN_PV1,
1258 };
1259
1260 static const unsigned drive_uart2_pins[] = {
1261         TEGRA_PIN_UART2_TXD_PC2,
1262         TEGRA_PIN_UART2_RXD_PC3,
1263         TEGRA_PIN_UART2_CTS_N_PJ5,
1264         TEGRA_PIN_UART2_RTS_N_PJ6,
1265 };
1266
1267 static const unsigned drive_uart3_pins[] = {
1268         TEGRA_PIN_UART3_CTS_N_PA1,
1269         TEGRA_PIN_UART3_RTS_N_PC0,
1270         TEGRA_PIN_UART3_TXD_PW6,
1271         TEGRA_PIN_UART3_RXD_PW7,
1272 };
1273
1274 static const unsigned drive_sdio1_pins[] = {
1275         TEGRA_PIN_SDMMC1_DAT3_PY4,
1276         TEGRA_PIN_SDMMC1_DAT2_PY5,
1277         TEGRA_PIN_SDMMC1_DAT1_PY6,
1278         TEGRA_PIN_SDMMC1_DAT0_PY7,
1279         TEGRA_PIN_SDMMC1_CLK_PZ0,
1280         TEGRA_PIN_SDMMC1_CMD_PZ1,
1281 };
1282
1283 static const unsigned drive_ddc_pins[] = {
1284         TEGRA_PIN_DDC_SCL_PV4,
1285         TEGRA_PIN_DDC_SDA_PV5,
1286 };
1287
1288 static const unsigned drive_gma_pins[] = {
1289         TEGRA_PIN_SDMMC4_CLK_PCC4,
1290         TEGRA_PIN_SDMMC4_CMD_PT7,
1291         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1292         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1293         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1294         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1295         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1296         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1297         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1298         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1299 };
1300
1301 static const unsigned drive_gme_pins[] = {
1302         TEGRA_PIN_PBB0,
1303         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1304         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1305         TEGRA_PIN_PBB3,
1306         TEGRA_PIN_PCC2,
1307 };
1308
1309 static const unsigned drive_gmf_pins[] = {
1310         TEGRA_PIN_PBB4,
1311         TEGRA_PIN_PBB5,
1312         TEGRA_PIN_PBB6,
1313         TEGRA_PIN_PBB7,
1314 };
1315
1316 static const unsigned drive_gmg_pins[] = {
1317         TEGRA_PIN_CAM_MCLK_PCC0,
1318 };
1319
1320 static const unsigned drive_gmh_pins[] = {
1321         TEGRA_PIN_PCC1,
1322 };
1323
1324 static const unsigned drive_owr_pins[] = {
1325         TEGRA_PIN_SDMMC3_CD_N_PV2,
1326 };
1327
1328 static const unsigned drive_uda_pins[] = {
1329         TEGRA_PIN_ULPI_CLK_PY0,
1330         TEGRA_PIN_ULPI_DIR_PY1,
1331         TEGRA_PIN_ULPI_NXT_PY2,
1332         TEGRA_PIN_ULPI_STP_PY3,
1333 };
1334
1335 enum tegra_mux {
1336         TEGRA_MUX_BLINK,
1337         TEGRA_MUX_CEC,
1338         TEGRA_MUX_CLDVFS,
1339         TEGRA_MUX_CLK12,
1340         TEGRA_MUX_CPU,
1341         TEGRA_MUX_DAP,
1342         TEGRA_MUX_DAP1,
1343         TEGRA_MUX_DAP2,
1344         TEGRA_MUX_DEV3,
1345         TEGRA_MUX_DISPLAYA,
1346         TEGRA_MUX_DISPLAYA_ALT,
1347         TEGRA_MUX_DISPLAYB,
1348         TEGRA_MUX_DTV,
1349         TEGRA_MUX_EMC_DLL,
1350         TEGRA_MUX_EXTPERIPH1,
1351         TEGRA_MUX_EXTPERIPH2,
1352         TEGRA_MUX_EXTPERIPH3,
1353         TEGRA_MUX_GMI,
1354         TEGRA_MUX_GMI_ALT,
1355         TEGRA_MUX_HDA,
1356         TEGRA_MUX_HSI,
1357         TEGRA_MUX_I2C1,
1358         TEGRA_MUX_I2C2,
1359         TEGRA_MUX_I2C3,
1360         TEGRA_MUX_I2C4,
1361         TEGRA_MUX_I2CPWR,
1362         TEGRA_MUX_I2S0,
1363         TEGRA_MUX_I2S1,
1364         TEGRA_MUX_I2S2,
1365         TEGRA_MUX_I2S3,
1366         TEGRA_MUX_I2S4,
1367         TEGRA_MUX_IRDA,
1368         TEGRA_MUX_KBC,
1369         TEGRA_MUX_NAND,
1370         TEGRA_MUX_NAND_ALT,
1371         TEGRA_MUX_OWR,
1372         TEGRA_MUX_PMI,
1373         TEGRA_MUX_PWM0,
1374         TEGRA_MUX_PWM1,
1375         TEGRA_MUX_PWM2,
1376         TEGRA_MUX_PWM3,
1377         TEGRA_MUX_PWRON,
1378         TEGRA_MUX_RESET_OUT_N,
1379         TEGRA_MUX_RSVD1,
1380         TEGRA_MUX_RSVD2,
1381         TEGRA_MUX_RSVD3,
1382         TEGRA_MUX_RSVD4,
1383         TEGRA_MUX_SDMMC1,
1384         TEGRA_MUX_SDMMC2,
1385         TEGRA_MUX_SDMMC3,
1386         TEGRA_MUX_SDMMC4,
1387         TEGRA_MUX_SOC,
1388         TEGRA_MUX_SPDIF,
1389         TEGRA_MUX_SPI1,
1390         TEGRA_MUX_SPI2,
1391         TEGRA_MUX_SPI3,
1392         TEGRA_MUX_SPI4,
1393         TEGRA_MUX_SPI5,
1394         TEGRA_MUX_SPI6,
1395         TEGRA_MUX_SYSCLK,
1396         TEGRA_MUX_TRACE,
1397         TEGRA_MUX_UARTA,
1398         TEGRA_MUX_UARTB,
1399         TEGRA_MUX_UARTC,
1400         TEGRA_MUX_UARTD,
1401         TEGRA_MUX_ULPI,
1402         TEGRA_MUX_USB,
1403         TEGRA_MUX_VGP1,
1404         TEGRA_MUX_VGP2,
1405         TEGRA_MUX_VGP3,
1406         TEGRA_MUX_VGP4,
1407         TEGRA_MUX_VGP5,
1408         TEGRA_MUX_VGP6,
1409         TEGRA_MUX_VI,
1410         TEGRA_MUX_VI_ALT1,
1411         TEGRA_MUX_VI_ALT3,
1412 };
1413
1414 #define FUNCTION(fname)                                 \
1415         {                                               \
1416                 .name = #fname,                         \
1417         }
1418
1419 static struct tegra_function tegra114_functions[] = {
1420         FUNCTION(blink),
1421         FUNCTION(cec),
1422         FUNCTION(cldvfs),
1423         FUNCTION(clk12),
1424         FUNCTION(cpu),
1425         FUNCTION(dap),
1426         FUNCTION(dap1),
1427         FUNCTION(dap2),
1428         FUNCTION(dev3),
1429         FUNCTION(displaya),
1430         FUNCTION(displaya_alt),
1431         FUNCTION(displayb),
1432         FUNCTION(dtv),
1433         FUNCTION(emc_dll),
1434         FUNCTION(extperiph1),
1435         FUNCTION(extperiph2),
1436         FUNCTION(extperiph3),
1437         FUNCTION(gmi),
1438         FUNCTION(gmi_alt),
1439         FUNCTION(hda),
1440         FUNCTION(hsi),
1441         FUNCTION(i2c1),
1442         FUNCTION(i2c2),
1443         FUNCTION(i2c3),
1444         FUNCTION(i2c4),
1445         FUNCTION(i2cpwr),
1446         FUNCTION(i2s0),
1447         FUNCTION(i2s1),
1448         FUNCTION(i2s2),
1449         FUNCTION(i2s3),
1450         FUNCTION(i2s4),
1451         FUNCTION(irda),
1452         FUNCTION(kbc),
1453         FUNCTION(nand),
1454         FUNCTION(nand_alt),
1455         FUNCTION(owr),
1456         FUNCTION(pmi),
1457         FUNCTION(pwm0),
1458         FUNCTION(pwm1),
1459         FUNCTION(pwm2),
1460         FUNCTION(pwm3),
1461         FUNCTION(pwron),
1462         FUNCTION(reset_out_n),
1463         FUNCTION(rsvd1),
1464         FUNCTION(rsvd2),
1465         FUNCTION(rsvd3),
1466         FUNCTION(rsvd4),
1467         FUNCTION(sdmmc1),
1468         FUNCTION(sdmmc2),
1469         FUNCTION(sdmmc3),
1470         FUNCTION(sdmmc4),
1471         FUNCTION(soc),
1472         FUNCTION(spdif),
1473         FUNCTION(spi1),
1474         FUNCTION(spi2),
1475         FUNCTION(spi3),
1476         FUNCTION(spi4),
1477         FUNCTION(spi5),
1478         FUNCTION(spi6),
1479         FUNCTION(sysclk),
1480         FUNCTION(trace),
1481         FUNCTION(uarta),
1482         FUNCTION(uartb),
1483         FUNCTION(uartc),
1484         FUNCTION(uartd),
1485         FUNCTION(ulpi),
1486         FUNCTION(usb),
1487         FUNCTION(vgp1),
1488         FUNCTION(vgp2),
1489         FUNCTION(vgp3),
1490         FUNCTION(vgp4),
1491         FUNCTION(vgp5),
1492         FUNCTION(vgp6),
1493         FUNCTION(vi),
1494         FUNCTION(vi_alt1),
1495         FUNCTION(vi_alt3),
1496 };
1497
1498 #define DRV_PINGROUP_REG_A              0x868   /* bank 0 */
1499 #define PINGROUP_REG_A                  0x3000  /* bank 1 */
1500
1501 #define PINGROUP_REG_Y(r)               ((r) - PINGROUP_REG_A)
1502 #define PINGROUP_REG_N(r)               -1
1503
1504 #define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel)  \
1505         {                                                               \
1506                 .name = #pg_name,                                       \
1507                 .pins = pg_name##_pins,                                 \
1508                 .npins = ARRAY_SIZE(pg_name##_pins),                    \
1509                 .funcs = {                                              \
1510                         TEGRA_MUX_##f0,                                 \
1511                         TEGRA_MUX_##f1,                                 \
1512                         TEGRA_MUX_##f2,                                 \
1513                         TEGRA_MUX_##f3,                                 \
1514                 },                                                      \
1515                 .func_safe = TEGRA_MUX_##f_safe,                        \
1516                 .mux_reg = PINGROUP_REG_Y(r),                           \
1517                 .mux_bank = 1,                                          \
1518                 .mux_bit = 0,                                           \
1519                 .pupd_reg = PINGROUP_REG_Y(r),                          \
1520                 .pupd_bank = 1,                                         \
1521                 .pupd_bit = 2,                                          \
1522                 .tri_reg = PINGROUP_REG_Y(r),                           \
1523                 .tri_bank = 1,                                          \
1524                 .tri_bit = 4,                                           \
1525                 .einput_reg = PINGROUP_REG_Y(r),                        \
1526                 .einput_bank = 1,                                       \
1527                 .einput_bit = 5,                                        \
1528                 .odrain_reg = PINGROUP_REG_##od(r),                     \
1529                 .odrain_bank = 1,                                       \
1530                 .odrain_bit = 6,                                        \
1531                 .lock_reg = PINGROUP_REG_Y(r),                          \
1532                 .lock_bank = 1,                                         \
1533                 .lock_bit = 7,                                          \
1534                 .ioreset_reg = PINGROUP_REG_##ior(r),                   \
1535                 .ioreset_bank = 1,                                      \
1536                 .ioreset_bit = 8,                                       \
1537                 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r),               \
1538                 .rcv_sel_bank = 1,                                      \
1539                 .rcv_sel_bit = 9,                                       \
1540                 .drv_reg = -1,                                          \
1541                 .drvtype_reg = -1,                                      \
1542         }
1543
1544 #define DRV_PINGROUP_REG_Y(r)           ((r) - DRV_PINGROUP_REG_A)
1545 #define DRV_PINGROUP_REG_N(r)           -1
1546
1547
1548 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b,              \
1549                      drvdn_b, drvdn_w, drvup_b, drvup_w,                \
1550                      slwr_b, slwr_w, slwf_b, slwf_w,                    \
1551                      drvtype)                                           \
1552         {                                                               \
1553                 .name = "drive_" #pg_name,                              \
1554                 .pins = drive_##pg_name##_pins,                         \
1555                 .npins = ARRAY_SIZE(drive_##pg_name##_pins),            \
1556                 .mux_reg = -1,                                          \
1557                 .pupd_reg = -1,                                         \
1558                 .tri_reg = -1,                                          \
1559                 .einput_reg = -1,                                       \
1560                 .odrain_reg = -1,                                       \
1561                 .lock_reg = -1,                                         \
1562                 .ioreset_reg = -1,                                      \
1563                 .rcv_sel_reg = -1,                                      \
1564                 .drv_reg = DRV_PINGROUP_REG_Y(r),                       \
1565                 .drv_bank = 0,                                          \
1566                 .hsm_bit = hsm_b,                                       \
1567                 .schmitt_bit = schmitt_b,                               \
1568                 .lpmd_bit = lpmd_b,                                     \
1569                 .drvdn_bit = drvdn_b,                                   \
1570                 .drvdn_width = drvdn_w,                                 \
1571                 .drvup_bit = drvup_b,                                   \
1572                 .drvup_width = drvup_w,                                 \
1573                 .slwr_bit = slwr_b,                                     \
1574                 .slwr_width = slwr_w,                                   \
1575                 .slwf_bit = slwf_b,                                     \
1576                 .slwf_width = slwf_w,                                   \
1577                 .drvtype_reg = DRV_PINGROUP_REG_##drvtype(r),           \
1578                 .drvtype_bank = 0,                                      \
1579                 .drvtype_bit = 6,                                       \
1580         }
1581
1582 static const struct tegra_pingroup tegra114_groups[] = {
1583         /*       pg_name,                f0,         f1,         f2,           f3,          safe,     r,      od, ior, rcv_sel */
1584         PINGROUP(ulpi_data0_po1,         SPI3,       HSI,        UARTA,        ULPI,        ULPI,     0x3000,  N,  N,  N),
1585         PINGROUP(ulpi_data1_po2,         SPI3,       HSI,        UARTA,        ULPI,        ULPI,     0x3004,  N,  N,  N),
1586         PINGROUP(ulpi_data2_po3,         SPI3,       HSI,        UARTA,        ULPI,        ULPI,     0x3008,  N,  N,  N),
1587         PINGROUP(ulpi_data3_po4,         SPI3,       HSI,        UARTA,        ULPI,        ULPI,     0x300c,  N,  N,  N),
1588         PINGROUP(ulpi_data4_po5,         SPI2,       HSI,        UARTA,        ULPI,        ULPI,     0x3010,  N,  N,  N),
1589         PINGROUP(ulpi_data5_po6,         SPI2,       HSI,        UARTA,        ULPI,        ULPI,     0x3014,  N,  N,  N),
1590         PINGROUP(ulpi_data6_po7,         SPI2,       HSI,        UARTA,        ULPI,        ULPI,     0x3018,  N,  N,  N),
1591         PINGROUP(ulpi_data7_po0,         SPI2,       HSI,        UARTA,        ULPI,        ULPI,     0x301c,  N,  N,  N),
1592         PINGROUP(ulpi_clk_py0,           SPI1,       SPI5,       UARTD,        ULPI,        ULPI,     0x3020,  N,  N,  N),
1593         PINGROUP(ulpi_dir_py1,           SPI1,       SPI5,       UARTD,        ULPI,        ULPI,     0x3024,  N,  N,  N),
1594         PINGROUP(ulpi_nxt_py2,           SPI1,       SPI5,       UARTD,        ULPI,        ULPI,     0x3028,  N,  N,  N),
1595         PINGROUP(ulpi_stp_py3,           SPI1,       SPI5,       UARTD,        ULPI,        ULPI,     0x302c,  N,  N,  N),
1596         PINGROUP(dap3_fs_pp0,            I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    I2S2,     0x3030,  N,  N,  N),
1597         PINGROUP(dap3_din_pp1,           I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    I2S2,     0x3034,  N,  N,  N),
1598         PINGROUP(dap3_dout_pp2,          I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    I2S2,     0x3038,  N,  N,  N),
1599         PINGROUP(dap3_sclk_pp3,          I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    I2S2,     0x303c,  N,  N,  N),
1600         PINGROUP(pv0,                    USB,        RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3040,  N,  N,  N),
1601         PINGROUP(pv1,                    RSVD1,      RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3044,  N,  N,  N),
1602         PINGROUP(sdmmc1_clk_pz0,         SDMMC1,     CLK12,      RSVD3,        RSVD4,       RSVD4,    0x3048,  N,  N,  N),
1603         PINGROUP(sdmmc1_cmd_pz1,         SDMMC1,     SPDIF,      SPI4,         UARTA,       SDMMC1,   0x304c,  N,  N,  N),
1604         PINGROUP(sdmmc1_dat3_py4,        SDMMC1,     SPDIF,      SPI4,         UARTA,       SDMMC1,   0x3050,  N,  N,  N),
1605         PINGROUP(sdmmc1_dat2_py5,        SDMMC1,     PWM0,       SPI4,         UARTA,       SDMMC1,   0x3054,  N,  N,  N),
1606         PINGROUP(sdmmc1_dat1_py6,        SDMMC1,     PWM1,       SPI4,         UARTA,       SDMMC1,   0x3058,  N,  N,  N),
1607         PINGROUP(sdmmc1_dat0_py7,        SDMMC1,     RSVD2,      SPI4,         UARTA,       RSVD2,    0x305c,  N,  N,  N),
1608         PINGROUP(clk2_out_pw5,           EXTPERIPH2, RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3068,  N,  N,  N),
1609         PINGROUP(clk2_req_pcc5,          DAP,        RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x306c,  N,  N,  N),
1610         PINGROUP(hdmi_int_pn7,           RSVD1,      RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3110,  N,  N,  Y),
1611         PINGROUP(ddc_scl_pv4,            I2C4,       RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3114,  N,  N,  Y),
1612         PINGROUP(ddc_sda_pv5,            I2C4,       RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3118,  N,  N,  Y),
1613         PINGROUP(uart2_rxd_pc3,          IRDA,       SPDIF,      UARTA,        SPI4,        IRDA,     0x3164,  N,  N,  N),
1614         PINGROUP(uart2_txd_pc2,          IRDA,       SPDIF,      UARTA,        SPI4,        IRDA,     0x3168,  N,  N,  N),
1615         PINGROUP(uart2_rts_n_pj6,        UARTA,      UARTB,      RSVD3,        SPI4,        RSVD3,    0x316c,  N,  N,  N),
1616         PINGROUP(uart2_cts_n_pj5,        UARTA,      UARTB,      RSVD3,        SPI4,        RSVD3,    0x3170,  N,  N,  N),
1617         PINGROUP(uart3_txd_pw6,          UARTC,      RSVD2,      RSVD3,        SPI4,        RSVD3,    0x3174,  N,  N,  N),
1618         PINGROUP(uart3_rxd_pw7,          UARTC,      RSVD2,      RSVD3,        SPI4,        RSVD3,    0x3178,  N,  N,  N),
1619         PINGROUP(uart3_cts_n_pa1,        UARTC,      SDMMC1,     DTV,          SPI4,        UARTC,    0x317c,  N,  N,  N),
1620         PINGROUP(uart3_rts_n_pc0,        UARTC,      PWM0,       DTV,          DISPLAYA,    UARTC,    0x3180,  N,  N,  N),
1621         PINGROUP(pu0,                    OWR,        UARTA,      RSVD3,        RSVD4,       RSVD4,    0x3184,  N,  N,  N),
1622         PINGROUP(pu1,                    RSVD1,      UARTA,      RSVD3,        RSVD4,       RSVD4,    0x3188,  N,  N,  N),
1623         PINGROUP(pu2,                    RSVD1,      UARTA,      RSVD3,        RSVD4,       RSVD4,    0x318c,  N,  N,  N),
1624         PINGROUP(pu3,                    PWM0,       UARTA,      DISPLAYA,     DISPLAYB,    PWM0,     0x3190,  N,  N,  N),
1625         PINGROUP(pu4,                    PWM1,       UARTA,      DISPLAYA,     DISPLAYB,    PWM1,     0x3194,  N,  N,  N),
1626         PINGROUP(pu5,                    PWM2,       UARTA,      DISPLAYA,     DISPLAYB,    PWM2,     0x3198,  N,  N,  N),
1627         PINGROUP(pu6,                    PWM3,       UARTA,      USB,          DISPLAYB,    PWM3,     0x319c,  N,  N,  N),
1628         PINGROUP(gen1_i2c_sda_pc5,       I2C1,       RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x31a0,  Y,  N,  N),
1629         PINGROUP(gen1_i2c_scl_pc4,       I2C1,       RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x31a4,  Y,  N,  N),
1630         PINGROUP(dap4_fs_pp4,            I2S3,       RSVD2,      DTV,          RSVD4,       RSVD4,    0x31a8,  N,  N,  N),
1631         PINGROUP(dap4_din_pp5,           I2S3,       RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x31ac,  N,  N,  N),
1632         PINGROUP(dap4_dout_pp6,          I2S3,       RSVD2,      DTV,          RSVD4,       RSVD4,    0x31b0,  N,  N,  N),
1633         PINGROUP(dap4_sclk_pp7,          I2S3,       RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x31b4,  N,  N,  N),
1634         PINGROUP(clk3_out_pee0,          EXTPERIPH3, RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x31b8,  N,  N,  N),
1635         PINGROUP(clk3_req_pee1,          DEV3,       RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x31bc,  N,  N,  N),
1636         PINGROUP(gmi_wp_n_pc7,           RSVD1,      NAND,       GMI,          GMI_ALT,     RSVD1,    0x31c0,  N,  N,  N),
1637         PINGROUP(gmi_iordy_pi5,          SDMMC2,     RSVD2,      GMI,          TRACE,       RSVD2,    0x31c4,  N,  N,  N),
1638         PINGROUP(gmi_wait_pi7,           SPI4,       NAND,       GMI,          DTV,         NAND,     0x31c8,  N,  N,  N),
1639         PINGROUP(gmi_adv_n_pk0,          RSVD1,      NAND,       GMI,          TRACE,       RSVD1,    0x31cc,  N,  N,  N),
1640         PINGROUP(gmi_clk_pk1,            SDMMC2,     NAND,       GMI,          TRACE,       GMI,      0x31d0,  N,  N,  N),
1641         PINGROUP(gmi_cs0_n_pj0,          RSVD1,      NAND,       GMI,          USB,         RSVD1,    0x31d4,  N,  N,  N),
1642         PINGROUP(gmi_cs1_n_pj2,          RSVD1,      NAND,       GMI,          SOC,         RSVD1,    0x31d8,  N,  N,  N),
1643         PINGROUP(gmi_cs2_n_pk3,          SDMMC2,     NAND,       GMI,          TRACE,       GMI,      0x31dc,  N,  N,  N),
1644         PINGROUP(gmi_cs3_n_pk4,          SDMMC2,     NAND,       GMI,          GMI_ALT,     GMI,      0x31e0,  N,  N,  N),
1645         PINGROUP(gmi_cs4_n_pk2,          USB,        NAND,       GMI,          TRACE,       GMI,      0x31e4,  N,  N,  N),
1646         PINGROUP(gmi_cs6_n_pi3,          NAND,       NAND_ALT,   GMI,          SPI4,        NAND,     0x31e8,  N,  N,  N),
1647         PINGROUP(gmi_cs7_n_pi6,          NAND,       NAND_ALT,   GMI,          SDMMC2,      NAND,     0x31ec,  N,  N,  N),
1648         PINGROUP(gmi_ad0_pg0,            RSVD1,      NAND,       GMI,          RSVD4,       RSVD4,    0x31f0,  N,  N,  N),
1649         PINGROUP(gmi_ad1_pg1,            RSVD1,      NAND,       GMI,          RSVD4,       RSVD4,    0x31f4,  N,  N,  N),
1650         PINGROUP(gmi_ad2_pg2,            RSVD1,      NAND,       GMI,          RSVD4,       RSVD4,    0x31f8,  N,  N,  N),
1651         PINGROUP(gmi_ad3_pg3,            RSVD1,      NAND,       GMI,          RSVD4,       RSVD4,    0x31fc,  N,  N,  N),
1652         PINGROUP(gmi_ad4_pg4,            RSVD1,      NAND,       GMI,          RSVD4,       RSVD4,    0x3200,  N,  N,  N),
1653         PINGROUP(gmi_ad5_pg5,            RSVD1,      NAND,       GMI,          SPI4,        RSVD1,    0x3204,  N,  N,  N),
1654         PINGROUP(gmi_ad6_pg6,            RSVD1,      NAND,       GMI,          SPI4,        RSVD1,    0x3208,  N,  N,  N),
1655         PINGROUP(gmi_ad7_pg7,            RSVD1,      NAND,       GMI,          SPI4,        RSVD1,    0x320c,  N,  N,  N),
1656         PINGROUP(gmi_ad8_ph0,            PWM0,       NAND,       GMI,          DTV,         GMI,      0x3210,  N,  N,  N),
1657         PINGROUP(gmi_ad9_ph1,            PWM1,       NAND,       GMI,          CLDVFS,      GMI,      0x3214,  N,  N,  N),
1658         PINGROUP(gmi_ad10_ph2,           PWM2,       NAND,       GMI,          CLDVFS,      GMI,      0x3218,  N,  N,  N),
1659         PINGROUP(gmi_ad11_ph3,           PWM3,       NAND,       GMI,          USB,         GMI,      0x321c,  N,  N,  N),
1660         PINGROUP(gmi_ad12_ph4,           SDMMC2,     NAND,       GMI,          RSVD4,       RSVD4,    0x3220,  N,  N,  N),
1661         PINGROUP(gmi_ad13_ph5,           SDMMC2,     NAND,       GMI,          RSVD4,       RSVD4,    0x3224,  N,  N,  N),
1662         PINGROUP(gmi_ad14_ph6,           SDMMC2,     NAND,       GMI,          DTV,         GMI,      0x3228,  N,  N,  N),
1663         PINGROUP(gmi_ad15_ph7,           SDMMC2,     NAND,       GMI,          DTV,         GMI,      0x322c,  N,  N,  N),
1664         PINGROUP(gmi_a16_pj7,            UARTD,      TRACE,      GMI,          GMI_ALT,     GMI,      0x3230,  N,  N,  N),
1665         PINGROUP(gmi_a17_pb0,            UARTD,      RSVD2,      GMI,          TRACE,       RSVD2,    0x3234,  N,  N,  N),
1666         PINGROUP(gmi_a18_pb1,            UARTD,      RSVD2,      GMI,          TRACE,       RSVD2,    0x3238,  N,  N,  N),
1667         PINGROUP(gmi_a19_pk7,            UARTD,      SPI4,       GMI,          TRACE,       GMI,      0x323c,  N,  N,  N),
1668         PINGROUP(gmi_wr_n_pi0,           RSVD1,      NAND,       GMI,          SPI4,        RSVD1,    0x3240,  N,  N,  N),
1669         PINGROUP(gmi_oe_n_pi1,           RSVD1,      NAND,       GMI,          SOC,         RSVD1,    0x3244,  N,  N,  N),
1670         PINGROUP(gmi_dqs_p_pj3,          SDMMC2,     NAND,       GMI,          TRACE,       NAND,     0x3248,  N,  N,  N),
1671         PINGROUP(gmi_rst_n_pi4,          NAND,       NAND_ALT,   GMI,          RSVD4,       RSVD4,    0x324c,  N,  N,  N),
1672         PINGROUP(gen2_i2c_scl_pt5,       I2C2,       RSVD2,      GMI,          RSVD4,       RSVD4,    0x3250,  Y,  N,  N),
1673         PINGROUP(gen2_i2c_sda_pt6,       I2C2,       RSVD2,      GMI,          RSVD4,       RSVD4,    0x3254,  Y,  N,  N),
1674         PINGROUP(sdmmc4_clk_pcc4,        SDMMC4,     RSVD2,      GMI,          RSVD4,       RSVD4,    0x3258,  N,  Y,  N),
1675         PINGROUP(sdmmc4_cmd_pt7,         SDMMC4,     RSVD2,      GMI,          RSVD4,       RSVD4,    0x325c,  N,  Y,  N),
1676         PINGROUP(sdmmc4_dat0_paa0,       SDMMC4,     SPI3,       GMI,          RSVD4,       RSVD4,    0x3260,  N,  Y,  N),
1677         PINGROUP(sdmmc4_dat1_paa1,       SDMMC4,     SPI3,       GMI,          RSVD4,       RSVD4,    0x3264,  N,  Y,  N),
1678         PINGROUP(sdmmc4_dat2_paa2,       SDMMC4,     SPI3,       GMI,          RSVD4,       RSVD4,    0x3268,  N,  Y,  N),
1679         PINGROUP(sdmmc4_dat3_paa3,       SDMMC4,     SPI3,       GMI,          RSVD4,       RSVD4,    0x326c,  N,  Y,  N),
1680         PINGROUP(sdmmc4_dat4_paa4,       SDMMC4,     SPI3,       GMI,          RSVD4,       RSVD4,    0x3270,  N,  Y,  N),
1681         PINGROUP(sdmmc4_dat5_paa5,       SDMMC4,     SPI3,       GMI,          RSVD4,       RSVD4,    0x3274,  N,  Y,  N),
1682         PINGROUP(sdmmc4_dat6_paa6,       SDMMC4,     SPI3,       GMI,          RSVD4,       RSVD4,    0x3278,  N,  Y,  N),
1683         PINGROUP(sdmmc4_dat7_paa7,       SDMMC4,     RSVD2,      GMI,          RSVD4,       RSVD4,    0x327c,  N,  Y,  N),
1684         PINGROUP(cam_mclk_pcc0,          VI,         VI_ALT1,    VI_ALT3,      RSVD4,       RSVD4,    0x3284,  N,  N,  N),
1685         PINGROUP(pcc1,                   I2S4,       RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3288,  N,  N,  N),
1686         PINGROUP(pbb0,                   I2S4,       VI,         VI_ALT1,      VI_ALT3,     I2S4,     0x328c,  N,  N,  N),
1687         PINGROUP(cam_i2c_scl_pbb1,       VGP1,       I2C3,       RSVD3,        RSVD4,       RSVD4,    0x3290,  Y,  N,  N),
1688         PINGROUP(cam_i2c_sda_pbb2,       VGP2,       I2C3,       RSVD3,        RSVD4,       RSVD4,    0x3294,  Y,  N,  N),
1689         PINGROUP(pbb3,                   VGP3,       DISPLAYA,   DISPLAYB,     RSVD4,       RSVD4,    0x3298,  N,  N,  N),
1690         PINGROUP(pbb4,                   VGP4,       DISPLAYA,   DISPLAYB,     RSVD4,       RSVD4,    0x329c,  N,  N,  N),
1691         PINGROUP(pbb5,                   VGP5,       DISPLAYA,   DISPLAYB,     RSVD4,       RSVD4,    0x32a0,  N,  N,  N),
1692         PINGROUP(pbb6,                   VGP6,       DISPLAYA,   DISPLAYB,     RSVD4,       RSVD4,    0x32a4,  N,  N,  N),
1693         PINGROUP(pbb7,                   I2S4,       RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x32a8,  N,  N,  N),
1694         PINGROUP(pcc2,                   I2S4,       RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x32ac,  N,  N,  N),
1695         PINGROUP(pwr_i2c_scl_pz6,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x32b4,  Y,  N,  N),
1696         PINGROUP(pwr_i2c_sda_pz7,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x32b8,  Y,  N,  N),
1697         PINGROUP(kb_row0_pr0,            KBC,        RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x32bc,  N,  N,  N),
1698         PINGROUP(kb_row1_pr1,            KBC,        RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x32c0,  N,  N,  N),
1699         PINGROUP(kb_row2_pr2,            KBC,        RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x32c4,  N,  N,  N),
1700         PINGROUP(kb_row3_pr3,            KBC,        DISPLAYA,   RSVD3,        DISPLAYB,    RSVD3,    0x32c8,  N,  N,  N),
1701         PINGROUP(kb_row4_pr4,            KBC,        DISPLAYA,   SPI2,         DISPLAYB,    KBC,      0x32cc,  N,  N,  N),
1702         PINGROUP(kb_row5_pr5,            KBC,        DISPLAYA,   SPI2,         DISPLAYB,    KBC,      0x32d0,  N,  N,  N),
1703         PINGROUP(kb_row6_pr6,            KBC,        DISPLAYA,   DISPLAYA_ALT, DISPLAYB,    KBC,      0x32d4,  N,  N,  N),
1704         PINGROUP(kb_row7_pr7,            KBC,        RSVD2,      CLDVFS,       UARTA,       RSVD2,    0x32d8,  N,  N,  N),
1705         PINGROUP(kb_row8_ps0,            KBC,        RSVD2,      CLDVFS,       UARTA,       RSVD2,    0x32dc,  N,  N,  N),
1706         PINGROUP(kb_row9_ps1,            KBC,        RSVD2,      RSVD3,        UARTA,       RSVD3,    0x32e0,  N,  N,  N),
1707         PINGROUP(kb_row10_ps2,           KBC,        RSVD2,      RSVD3,        UARTA,       RSVD3,    0x32e4,  N,  N,  N),
1708         PINGROUP(kb_col0_pq0,            KBC,        USB,        SPI2,         EMC_DLL,     KBC,      0x32fc,  N,  N,  N),
1709         PINGROUP(kb_col1_pq1,            KBC,        RSVD2,      SPI2,         EMC_DLL,     RSVD2,    0x3300,  N,  N,  N),
1710         PINGROUP(kb_col2_pq2,            KBC,        RSVD2,      SPI2,         RSVD4,       RSVD2,    0x3304,  N,  N,  N),
1711         PINGROUP(kb_col3_pq3,            KBC,        DISPLAYA,   PWM2,         UARTA,       KBC,      0x3308,  N,  N,  N),
1712         PINGROUP(kb_col4_pq4,            KBC,        OWR,        SDMMC3,       UARTA,       KBC,      0x330c,  N,  N,  N),
1713         PINGROUP(kb_col5_pq5,            KBC,        RSVD2,      SDMMC1,       RSVD4,       RSVD4,    0x3310,  N,  N,  N),
1714         PINGROUP(kb_col6_pq6,            KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,    0x3314,  N,  N,  N),
1715         PINGROUP(kb_col7_pq7,            KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,    0x3318,  N,  N,  N),
1716         PINGROUP(clk_32k_out_pa0,        BLINK,      SOC,        RSVD3,        RSVD4,       RSVD4,    0x331c,  N,  N,  N),
1717         PINGROUP(sys_clk_req_pz5,        SYSCLK,     RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3320,  N,  N,  N),
1718         PINGROUP(core_pwr_req,           PWRON,      RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3324,  N,  N,  N),
1719         PINGROUP(cpu_pwr_req,            CPU,        RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3328,  N,  N,  N),
1720         PINGROUP(pwr_int_n,              PMI,        RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x332c,  N,  N,  N),
1721         PINGROUP(owr,                    OWR,        RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3334,  N,  N,  Y),
1722         PINGROUP(dap1_fs_pn0,            I2S0,       HDA,        GMI,          RSVD4,       RSVD4,    0x3338,  N,  N,  N),
1723         PINGROUP(dap1_din_pn1,           I2S0,       HDA,        GMI,          RSVD4,       RSVD4,    0x333c,  N,  N,  N),
1724         PINGROUP(dap1_dout_pn2,          I2S0,       HDA,        GMI,          RSVD4,       RSVD4,    0x3340,  N,  N,  N),
1725         PINGROUP(dap1_sclk_pn3,          I2S0,       HDA,        GMI,          RSVD4,       RSVD4,    0x3344,  N,  N,  N),
1726         PINGROUP(clk1_req_pee2,          DAP,        DAP1,       RSVD3,        RSVD4,       RSVD4,    0x3348,  N,  N,  N),
1727         PINGROUP(clk1_out_pw4,           EXTPERIPH1, DAP2,       RSVD3,        RSVD4,       RSVD4,    0x334c,  N,  N,  N),
1728         PINGROUP(spdif_in_pk6,           SPDIF,      USB,        RSVD3,        RSVD4,       RSVD4,    0x3350,  N,  N,  N),
1729         PINGROUP(spdif_out_pk5,          SPDIF,      RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3354,  N,  N,  N),
1730         PINGROUP(dap2_fs_pa2,            I2S1,       HDA,        RSVD3,        RSVD4,       RSVD4,    0x3358,  N,  N,  N),
1731         PINGROUP(dap2_din_pa4,           I2S1,       HDA,        RSVD3,        RSVD4,       RSVD4,    0x335c,  N,  N,  N),
1732         PINGROUP(dap2_dout_pa5,          I2S1,       HDA,        RSVD3,        RSVD4,       RSVD4,    0x3360,  N,  N,  N),
1733         PINGROUP(dap2_sclk_pa3,          I2S1,       HDA,        RSVD3,        RSVD4,       RSVD4,    0x3364,  N,  N,  N),
1734         PINGROUP(dvfs_pwm_px0,           SPI6,       CLDVFS,     RSVD3,        RSVD4,       RSVD4,    0x3368,  N,  N,  N),
1735         PINGROUP(gpio_x1_aud_px1,        SPI6,       RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x336c,  N,  N,  N),
1736         PINGROUP(gpio_x3_aud_px3,        SPI6,       SPI1,       RSVD3,        RSVD4,       RSVD4,    0x3370,  N,  N,  N),
1737         PINGROUP(dvfs_clk_px2,           SPI6,       CLDVFS,     RSVD3,        RSVD4,       RSVD4,    0x3374,  N,  N,  N),
1738         PINGROUP(gpio_x4_aud_px4,        RSVD1,      SPI1,       SPI2,         DAP2,        RSVD1,    0x3378,  N,  N,  N),
1739         PINGROUP(gpio_x5_aud_px5,        RSVD1,      SPI1,       SPI2,         RSVD4,       RSVD1,    0x337c,  N,  N,  N),
1740         PINGROUP(gpio_x6_aud_px6,        SPI6,       SPI1,       SPI2,         RSVD4,       RSVD4,    0x3380,  N,  N,  N),
1741         PINGROUP(gpio_x7_aud_px7,        RSVD1,      SPI1,       SPI2,         RSVD4,       RSVD4,    0x3384,  N,  N,  N),
1742         PINGROUP(sdmmc3_clk_pa6,         SDMMC3,     RSVD2,      RSVD3,        SPI3,        RSVD3,    0x3390,  N,  N,  N),
1743         PINGROUP(sdmmc3_cmd_pa7,         SDMMC3,     PWM3,       UARTA,        SPI3,        SDMMC3,   0x3394,  N,  N,  N),
1744         PINGROUP(sdmmc3_dat0_pb7,        SDMMC3,     RSVD2,      RSVD3,        SPI3,        RSVD3,    0x3398,  N,  N,  N),
1745         PINGROUP(sdmmc3_dat1_pb6,        SDMMC3,     PWM2,       UARTA,        SPI3,        SDMMC3,   0x339c,  N,  N,  N),
1746         PINGROUP(sdmmc3_dat2_pb5,        SDMMC3,     PWM1,       DISPLAYA,     SPI3,        SDMMC3,   0x33a0,  N,  N,  N),
1747         PINGROUP(sdmmc3_dat3_pb4,        SDMMC3,     PWM0,       DISPLAYB,     SPI3,        SDMMC3,   0x33a4,  N,  N,  N),
1748         PINGROUP(hdmi_cec_pee3,          CEC,        SDMMC3,     RSVD3,        SOC,         RSVD3,    0x33e0,  Y,  N,  N),
1749         PINGROUP(sdmmc1_wp_n_pv3,        SDMMC1,     CLK12,      SPI4,         UARTA,       SDMMC1,   0x33e4,  N,  N,  N),
1750         PINGROUP(sdmmc3_cd_n_pv2,        SDMMC3,     OWR,        RSVD3,        RSVD4,       RSVD4,    0x33e8,  N,  N,  N),
1751         PINGROUP(gpio_w2_aud_pw2,        SPI6,       RSVD2,      SPI2,         I2C1,        RSVD2,    0x33ec,  N,  N,  N),
1752         PINGROUP(gpio_w3_aud_pw3,        SPI6,       SPI1,       SPI2,         I2C1,        SPI6,     0x33f0,  N,  N,  N),
1753         PINGROUP(usb_vbus_en0_pn4,       USB,        RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x33f4,  Y,  N,  N),
1754         PINGROUP(usb_vbus_en1_pn5,       USB,        RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x33f8,  Y,  N,  N),
1755         PINGROUP(sdmmc3_clk_lb_in_pee5,  SDMMC3,     RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x33fc,  N,  N,  N),
1756         PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3,     RSVD2,      RSVD3,        RSVD4,       RSVD4,    0x3400,  N,  N,  N),
1757         PINGROUP(reset_out_n,            RSVD1,      RSVD2,      RSVD3,        RESET_OUT_N, RSVD3,    0x3408,  N,  N,  N),
1758
1759         /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
1760         DRV_PINGROUP(ao1,   0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1761         DRV_PINGROUP(ao2,   0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1762         DRV_PINGROUP(at1,   0x870,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1763         DRV_PINGROUP(at2,   0x874,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1764         DRV_PINGROUP(at3,   0x878,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1765         DRV_PINGROUP(at4,   0x87c,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1766         DRV_PINGROUP(at5,   0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1767         DRV_PINGROUP(cdev1, 0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1768         DRV_PINGROUP(cdev2, 0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1769         DRV_PINGROUP(dap1,  0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1770         DRV_PINGROUP(dap2,  0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1771         DRV_PINGROUP(dap3,  0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1772         DRV_PINGROUP(dap4,  0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1773         DRV_PINGROUP(dbg,   0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1774         DRV_PINGROUP(sdio3, 0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
1775         DRV_PINGROUP(spi,   0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1776         DRV_PINGROUP(uaa,   0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1777         DRV_PINGROUP(uab,   0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1778         DRV_PINGROUP(uart2, 0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1779         DRV_PINGROUP(uart3, 0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1780         DRV_PINGROUP(sdio1, 0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
1781         DRV_PINGROUP(ddc,   0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1782         DRV_PINGROUP(gma,   0x900,  2,  3,  4,  14,  5,  20,  5,  28,  2,  30,  2,  Y),
1783         DRV_PINGROUP(gme,   0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1784         DRV_PINGROUP(gmf,   0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1785         DRV_PINGROUP(gmg,   0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1786         DRV_PINGROUP(gmh,   0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1787         DRV_PINGROUP(owr,   0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1788         DRV_PINGROUP(uda,   0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1789 };
1790
1791 static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
1792         .ngpios = NUM_GPIOS,
1793         .pins = tegra114_pins,
1794         .npins = ARRAY_SIZE(tegra114_pins),
1795         .functions = tegra114_functions,
1796         .nfunctions = ARRAY_SIZE(tegra114_functions),
1797         .groups = tegra114_groups,
1798         .ngroups = ARRAY_SIZE(tegra114_groups),
1799 };
1800
1801 static int tegra114_pinctrl_probe(struct platform_device *pdev)
1802 {
1803         return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
1804 }
1805
1806 static struct of_device_id tegra114_pinctrl_of_match[] = {
1807         { .compatible = "nvidia,tegra114-pinmux", },
1808         { },
1809 };
1810 MODULE_DEVICE_TABLE(of, tegra114_pinctrl_of_match);
1811
1812 static struct platform_driver tegra114_pinctrl_driver = {
1813         .driver = {
1814                 .name = "tegra114-pinctrl",
1815                 .owner = THIS_MODULE,
1816                 .of_match_table = tegra114_pinctrl_of_match,
1817         },
1818         .probe = tegra114_pinctrl_probe,
1819         .remove = tegra_pinctrl_remove,
1820 };
1821 module_platform_driver(tegra114_pinctrl_driver);
1822
1823 MODULE_AUTHOR("Pritesh Raithatha <praithatha@nvidia.com>");
1824 MODULE_DESCRIPTION("NVIDIA Tegra114 pinctrl driver");
1825 MODULE_LICENSE("GPL v2");