2 * Pinctrl driver for the Toumaz Xenif TZ1090 PowerDown Controller pins
4 * Copyright (c) 2013, Imagination Technologies Ltd.
6 * Derived from Tegra code:
7 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
10 * Copyright (C) 2010 Google, Inc.
11 * Copyright (C) 2010 NVIDIA Corporation
12 * Copyright (C) 2009-2011 ST-Ericsson AB
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms and conditions of the GNU General Public License,
16 * version 2, as published by the Free Software Foundation.
18 * This program is distributed in the hope it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 #include <linux/bitops.h>
26 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/pinctrl/machine.h>
30 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/pinctrl/pinctrl.h>
32 #include <linux/pinctrl/pinmux.h>
33 #include <linux/slab.h>
36 * The registers may be shared with other threads/cores, so we need to use the
37 * metag global lock2 for atomicity.
39 #include <asm/global_lock.h>
44 /* Register offsets from bank base address */
45 #define REG_GPIO_CONTROL0 0x00
46 #define REG_GPIO_CONTROL2 0x08
48 /* Register field information */
49 #define REG_GPIO_CONTROL2_PU_PD_S 16
50 #define REG_GPIO_CONTROL2_PDC_POS_S 4
51 #define REG_GPIO_CONTROL2_PDC_DR_S 2
52 #define REG_GPIO_CONTROL2_PDC_SR_S 1
53 #define REG_GPIO_CONTROL2_PDC_SCHMITT_S 0
55 /* PU_PD field values */
56 #define REG_PU_PD_TRISTATE 0
57 #define REG_PU_PD_UP 1
58 #define REG_PU_PD_DOWN 2
59 #define REG_PU_PD_REPEATER 3
68 * struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function
69 * @name: The name of the function, exported to pinctrl core.
70 * @groups: An array of pin groups that may select this function.
71 * @ngroups: The number of entries in @groups.
73 struct tz1090_pdc_function {
75 const char * const *groups;
80 * struct tz1090_pdc_pingroup - TZ1090 PDC pin group
81 * @name: Name of pin group.
82 * @pins: Array of pin numbers in this pin group.
83 * @npins: Number of pins in this pin group.
84 * @func: Function enabled by the mux.
85 * @reg: Mux register offset.
86 * @bit: Mux register bit.
87 * @drv: Drive control supported, otherwise it's a mux.
88 * This means Schmitt, Slew, and Drive strength.
90 * A representation of a group of pins (possibly just one pin) in the TZ1090
91 * PDC pin controller. Each group allows some parameter or parameters to be
92 * configured. The most common is mux function selection.
94 struct tz1090_pdc_pingroup {
96 const unsigned int *pins;
105 * All PDC pins can be GPIOs. Define these first to match how the GPIO driver
106 * names/numbers its pins.
109 enum tz1090_pdc_pin {
110 TZ1090_PDC_PIN_GPIO0,
111 TZ1090_PDC_PIN_GPIO1,
112 TZ1090_PDC_PIN_SYS_WAKE0,
113 TZ1090_PDC_PIN_SYS_WAKE1,
114 TZ1090_PDC_PIN_SYS_WAKE2,
115 TZ1090_PDC_PIN_IR_DATA,
116 TZ1090_PDC_PIN_EXT_POWER,
121 static const struct pinctrl_pin_desc tz1090_pdc_pins[] = {
123 PINCTRL_PIN(TZ1090_PDC_PIN_GPIO0, "gpio0"),
124 PINCTRL_PIN(TZ1090_PDC_PIN_GPIO1, "gpio1"),
125 PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE0, "sys_wake0"),
126 PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE1, "sys_wake1"),
127 PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE2, "sys_wake2"),
128 PINCTRL_PIN(TZ1090_PDC_PIN_IR_DATA, "ir_data"),
129 PINCTRL_PIN(TZ1090_PDC_PIN_EXT_POWER, "ext_power"),
134 static const unsigned int gpio0_pins[] = {
135 TZ1090_PDC_PIN_GPIO0,
138 static const unsigned int gpio1_pins[] = {
139 TZ1090_PDC_PIN_GPIO1,
142 static const unsigned int pdc_pins[] = {
143 TZ1090_PDC_PIN_GPIO0,
144 TZ1090_PDC_PIN_GPIO1,
145 TZ1090_PDC_PIN_SYS_WAKE0,
146 TZ1090_PDC_PIN_SYS_WAKE1,
147 TZ1090_PDC_PIN_SYS_WAKE2,
148 TZ1090_PDC_PIN_IR_DATA,
149 TZ1090_PDC_PIN_EXT_POWER,
154 enum tz1090_pdc_mux {
156 TZ1090_PDC_MUX_IR_MOD_STABLE_OUT,
158 TZ1090_PDC_MUX_IR_MOD_POWER_OUT,
161 /* Pin groups a function can be muxed to */
163 static const char * const gpio0_groups[] = {
167 static const char * const gpio1_groups[] = {
171 #define FUNCTION(mux, fname, group) \
172 [(TZ1090_PDC_MUX_ ## mux)] = { \
174 .groups = group##_groups, \
175 .ngroups = ARRAY_SIZE(group##_groups), \
178 /* Must correlate with enum tz1090_pdc_mux */
179 static const struct tz1090_pdc_function tz1090_pdc_functions[] = {
180 /* MUX fn pingroups */
181 FUNCTION(IR_MOD_STABLE_OUT, ir_mod_stable_out, gpio0),
182 FUNCTION(IR_MOD_POWER_OUT, ir_mod_power_out, gpio1),
186 * MUX_PG() - Initialise a pin group with mux control
187 * @pg_name: Pin group name (stringified, _pins appended to get pins array)
188 * @f0: Function 0 (TZ1090_PDC_MUX_ is prepended)
189 * @mux_r: Mux register (REG_PINCTRL_ is prepended)
190 * @mux_b: Bit number in register of mux field
192 #define MUX_PG(pg_name, f0, mux_r, mux_b) \
195 .pins = pg_name##_pins, \
196 .npins = ARRAY_SIZE(pg_name##_pins), \
197 .func = TZ1090_PDC_MUX_ ## f0, \
198 .reg = (REG_ ## mux_r), \
203 * DRV_PG() - Initialise a pin group with drive control
204 * @pg_name: Pin group name (stringified, _pins appended to get pins array)
206 #define DRV_PG(pg_name) \
209 .pins = pg_name##_pins, \
210 .npins = ARRAY_SIZE(pg_name##_pins), \
214 static const struct tz1090_pdc_pingroup tz1090_pdc_groups[] = {
215 /* Muxing pin groups */
216 /* pg_name, f0, mux register, mux bit */
217 MUX_PG(gpio0, IR_MOD_STABLE_OUT, GPIO_CONTROL0, 7),
218 MUX_PG(gpio1, IR_MOD_POWER_OUT, GPIO_CONTROL0, 6),
220 /* Drive pin groups */
226 * struct tz1090_pdc_pmx - Private pinctrl data
227 * @dev: Platform device
228 * @pctl: Pin control device
229 * @regs: Register region
230 * @lock: Lock protecting coherency of mux_en and gpio_en
231 * @mux_en: Muxes that have been enabled
232 * @gpio_en: Muxable GPIOs that have been enabled
234 struct tz1090_pdc_pmx {
236 struct pinctrl_dev *pctl;
243 static inline u32 pmx_read(struct tz1090_pdc_pmx *pmx, u32 reg)
245 return ioread32(pmx->regs + reg);
248 static inline void pmx_write(struct tz1090_pdc_pmx *pmx, u32 val, u32 reg)
250 iowrite32(val, pmx->regs + reg);
254 * Pin control operations
257 static int tz1090_pdc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
259 return ARRAY_SIZE(tz1090_pdc_groups);
262 static const char *tz1090_pdc_pinctrl_get_group_name(struct pinctrl_dev *pctl,
265 return tz1090_pdc_groups[group].name;
268 static int tz1090_pdc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
270 const unsigned int **pins,
271 unsigned int *num_pins)
273 *pins = tz1090_pdc_groups[group].pins;
274 *num_pins = tz1090_pdc_groups[group].npins;
279 #ifdef CONFIG_DEBUG_FS
280 static void tz1090_pdc_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
284 seq_printf(s, " %s", dev_name(pctldev->dev));
288 static int reserve_map(struct device *dev, struct pinctrl_map **map,
289 unsigned int *reserved_maps, unsigned int *num_maps,
290 unsigned int reserve)
292 unsigned int old_num = *reserved_maps;
293 unsigned int new_num = *num_maps + reserve;
294 struct pinctrl_map *new_map;
296 if (old_num >= new_num)
299 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
301 dev_err(dev, "krealloc(map) failed\n");
305 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
308 *reserved_maps = new_num;
313 static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps,
314 unsigned int *num_maps, const char *group,
315 const char *function)
317 if (WARN_ON(*num_maps == *reserved_maps))
320 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
321 (*map)[*num_maps].data.mux.group = group;
322 (*map)[*num_maps].data.mux.function = function;
329 * get_group_selector() - returns the group selector for a group
330 * @pin_group: the pin group to look up
332 * This is the same as pinctrl_get_group_selector except it doesn't produce an
333 * error message if the group isn't found or debug messages.
335 static int get_group_selector(const char *pin_group)
339 for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group)
340 if (!strcmp(tz1090_pdc_groups[group].name, pin_group))
346 static int add_map_configs(struct device *dev,
347 struct pinctrl_map **map,
348 unsigned int *reserved_maps, unsigned int *num_maps,
349 const char *group, unsigned long *configs,
350 unsigned int num_configs)
352 unsigned long *dup_configs;
353 enum pinctrl_map_type type;
355 if (WARN_ON(*num_maps == *reserved_maps))
358 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
361 dev_err(dev, "kmemdup(configs) failed\n");
366 * We support both pins and pin groups, but we need to figure out which
369 if (get_group_selector(group) >= 0)
370 type = PIN_MAP_TYPE_CONFIGS_GROUP;
372 type = PIN_MAP_TYPE_CONFIGS_PIN;
373 (*map)[*num_maps].type = type;
374 (*map)[*num_maps].data.configs.group_or_pin = group;
375 (*map)[*num_maps].data.configs.configs = dup_configs;
376 (*map)[*num_maps].data.configs.num_configs = num_configs;
382 static void tz1090_pdc_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
383 struct pinctrl_map *map,
384 unsigned int num_maps)
388 for (i = 0; i < num_maps; i++)
389 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
390 kfree(map[i].data.configs.configs);
395 static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev,
396 struct device_node *np,
397 struct pinctrl_map **map,
398 unsigned int *reserved_maps,
399 unsigned int *num_maps)
402 const char *function;
403 unsigned long *configs = NULL;
404 unsigned int num_configs = 0;
405 unsigned int reserve;
406 struct property *prop;
409 ret = of_property_read_string(np, "tz1090,function", &function);
411 /* EINVAL=missing, which is fine since it's optional */
414 "could not parse property function\n");
418 ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs);
423 if (function != NULL)
427 ret = of_property_count_strings(np, "tz1090,pins");
429 dev_err(dev, "could not parse property pins\n");
434 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
438 of_property_for_each_string(np, "tz1090,pins", prop, group) {
440 ret = add_map_mux(map, reserved_maps, num_maps,
447 ret = add_map_configs(dev, map, reserved_maps,
448 num_maps, group, configs,
462 static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
463 struct device_node *np_config,
464 struct pinctrl_map **map,
465 unsigned int *num_maps)
467 unsigned int reserved_maps;
468 struct device_node *np;
475 for_each_child_of_node(np_config, np) {
476 ret = tz1090_pdc_pinctrl_dt_subnode_to_map(pctldev->dev, np,
480 tz1090_pdc_pinctrl_dt_free_map(pctldev, *map,
489 static struct pinctrl_ops tz1090_pdc_pinctrl_ops = {
490 .get_groups_count = tz1090_pdc_pinctrl_get_groups_count,
491 .get_group_name = tz1090_pdc_pinctrl_get_group_name,
492 .get_group_pins = tz1090_pdc_pinctrl_get_group_pins,
493 #ifdef CONFIG_DEBUG_FS
494 .pin_dbg_show = tz1090_pdc_pinctrl_pin_dbg_show,
496 .dt_node_to_map = tz1090_pdc_pinctrl_dt_node_to_map,
497 .dt_free_map = tz1090_pdc_pinctrl_dt_free_map,
504 static int tz1090_pdc_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
506 return ARRAY_SIZE(tz1090_pdc_functions);
509 static const char *tz1090_pdc_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
510 unsigned int function)
512 return tz1090_pdc_functions[function].name;
515 static int tz1090_pdc_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
516 unsigned int function,
517 const char * const **groups,
518 unsigned int * const num_groups)
520 *groups = tz1090_pdc_functions[function].groups;
521 *num_groups = tz1090_pdc_functions[function].ngroups;
527 * tz1090_pdc_pinctrl_mux() - update mux bit
529 * @grp: Pin mux group
531 static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx,
532 const struct tz1090_pdc_pingroup *grp)
535 unsigned int pin_shift = grp->pins[0];
538 /* select = mux && !gpio */
539 select = ((pmx->mux_en & ~pmx->gpio_en) >> pin_shift) & 1;
542 __global_lock2(flags);
543 reg = pmx_read(pmx, grp->reg);
544 reg &= ~BIT(grp->bit);
545 reg |= select << grp->bit;
546 pmx_write(pmx, reg, grp->reg);
547 __global_unlock2(flags);
550 static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev,
551 unsigned int function, unsigned int group)
553 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
554 const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
556 dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n",
558 function, tz1090_pdc_functions[function].name,
559 group, tz1090_pdc_groups[group].name);
561 /* is it even a mux? */
565 /* does this group even control the function? */
566 if (function != grp->func)
569 /* record the pin being muxed and update mux bit */
570 spin_lock(&pmx->lock);
571 pmx->mux_en |= BIT(grp->pins[0]);
572 tz1090_pdc_pinctrl_mux(pmx, grp);
573 spin_unlock(&pmx->lock);
577 static void tz1090_pdc_pinctrl_disable(struct pinctrl_dev *pctldev,
578 unsigned int function,
581 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
582 const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
584 dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n",
586 function, tz1090_pdc_functions[function].name,
587 group, tz1090_pdc_groups[group].name);
589 /* is it even a mux? */
593 /* does this group even control the function? */
594 if (function != grp->func)
597 /* record the pin being unmuxed and update mux bit */
598 spin_lock(&pmx->lock);
599 pmx->mux_en &= ~BIT(grp->pins[0]);
600 tz1090_pdc_pinctrl_mux(pmx, grp);
601 spin_unlock(&pmx->lock);
604 static const struct tz1090_pdc_pingroup *find_mux_group(
605 struct tz1090_pdc_pmx *pmx,
608 const struct tz1090_pdc_pingroup *grp;
611 grp = tz1090_pdc_groups;
612 for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group, ++grp) {
613 /* only match muxes */
617 /* with a matching pin */
618 if (grp->pins[0] == pin)
625 static int tz1090_pdc_pinctrl_gpio_request_enable(
626 struct pinctrl_dev *pctldev,
627 struct pinctrl_gpio_range *range,
630 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
631 const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin);
634 /* record the pin in GPIO use and update mux bit */
635 spin_lock(&pmx->lock);
636 pmx->gpio_en |= BIT(pin);
637 tz1090_pdc_pinctrl_mux(pmx, grp);
638 spin_unlock(&pmx->lock);
643 static void tz1090_pdc_pinctrl_gpio_disable_free(
644 struct pinctrl_dev *pctldev,
645 struct pinctrl_gpio_range *range,
648 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
649 const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin);
652 /* record the pin not in GPIO use and update mux bit */
653 spin_lock(&pmx->lock);
654 pmx->gpio_en &= ~BIT(pin);
655 tz1090_pdc_pinctrl_mux(pmx, grp);
656 spin_unlock(&pmx->lock);
660 static struct pinmux_ops tz1090_pdc_pinmux_ops = {
661 .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count,
662 .get_function_name = tz1090_pdc_pinctrl_get_func_name,
663 .get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
664 .enable = tz1090_pdc_pinctrl_enable,
665 .disable = tz1090_pdc_pinctrl_disable,
666 .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable,
667 .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free,
671 * Pin config operations
674 static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev,
676 enum pin_config_param param,
678 u32 *reg, u32 *width, u32 *mask, u32 *shift,
681 /* Find information about parameter's register */
683 case PIN_CONFIG_BIAS_DISABLE:
684 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
685 *val = REG_PU_PD_TRISTATE;
687 case PIN_CONFIG_BIAS_PULL_UP:
690 case PIN_CONFIG_BIAS_PULL_DOWN:
691 *val = REG_PU_PD_DOWN;
693 case PIN_CONFIG_BIAS_BUS_HOLD:
694 *val = REG_PU_PD_REPEATER;
700 /* Only input bias parameters supported */
701 *reg = REG_GPIO_CONTROL2;
702 *shift = REG_GPIO_CONTROL2_PU_PD_S + pin*2;
705 /* Calculate field information */
706 *mask = (BIT(*width) - 1) << *shift;
711 static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev,
712 unsigned int pin, unsigned long *config)
714 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
715 enum pin_config_param param = pinconf_to_config_param(*config);
717 u32 reg, width, mask, shift, val, tmp, arg;
719 /* Get register information */
720 ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
721 ®, &width, &mask, &shift, &val);
725 /* Extract field from register */
726 tmp = pmx_read(pmx, reg);
727 arg = ((tmp & mask) >> shift) == val;
729 /* Config not active */
733 /* And pack config */
734 *config = pinconf_to_config_packed(param, arg);
739 static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev,
740 unsigned int pin, unsigned long config)
742 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
743 enum pin_config_param param = pinconf_to_config_param(config);
744 unsigned int arg = pinconf_to_config_argument(config);
746 u32 reg, width, mask, shift, val, tmp;
749 dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
750 __func__, tz1090_pdc_pins[pin].name, config);
752 /* Get register information */
753 ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
754 ®, &width, &mask, &shift, &val);
758 /* Unpack argument and range check it */
760 dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
765 /* Write register field */
766 __global_lock2(flags);
767 tmp = pmx_read(pmx, reg);
771 pmx_write(pmx, tmp, reg);
772 __global_unlock2(flags);
777 static const int tz1090_pdc_boolean_map[] = {
782 static const int tz1090_pdc_dr_map[] = {
789 static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev,
790 const struct tz1090_pdc_pingroup *g,
791 enum pin_config_param param,
792 bool report_err, u32 *reg, u32 *width,
793 u32 *mask, u32 *shift, const int **map)
795 /* Drive configuration applies in groups, but not to all groups. */
798 dev_dbg(pctldev->dev,
799 "%s: group %s has no drive control\n",
804 /* Find information about drive parameter's register */
805 *reg = REG_GPIO_CONTROL2;
807 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
808 *shift = REG_GPIO_CONTROL2_PDC_SCHMITT_S;
810 *map = tz1090_pdc_boolean_map;
812 case PIN_CONFIG_DRIVE_STRENGTH:
813 *shift = REG_GPIO_CONTROL2_PDC_DR_S;
815 *map = tz1090_pdc_dr_map;
817 case PIN_CONFIG_LOW_POWER_MODE:
818 *shift = REG_GPIO_CONTROL2_PDC_POS_S;
820 *map = tz1090_pdc_boolean_map;
826 /* Calculate field information */
827 *mask = (BIT(*width) - 1) << *shift;
832 static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev,
834 unsigned long *config)
836 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
837 const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group];
838 enum pin_config_param param = pinconf_to_config_param(*config);
840 u32 reg, width, mask, shift, val;
843 /* Get register information */
844 ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
845 ®, &width, &mask, &shift, &map);
849 /* Extract field from register */
850 val = pmx_read(pmx, reg);
851 arg = map[(val & mask) >> shift];
855 /* And pack config */
856 *config = pinconf_to_config_packed(param, arg);
861 static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev,
863 unsigned long config)
865 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
866 const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group];
867 enum pin_config_param param = pinconf_to_config_param(config);
868 const unsigned int *pit;
871 u32 reg, width, mask, shift, val;
875 dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
876 __func__, g->name, config);
878 /* Get register information */
879 ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
880 ®, &width, &mask, &shift, &map);
883 * Maybe we're trying to set a per-pin configuration of a group,
884 * so do the pins one by one. This is mainly as a convenience.
886 for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
887 ret = tz1090_pdc_pinconf_set(pctldev, *pit, config);
894 /* Unpack argument and map it to register value */
895 arg = pinconf_to_config_argument(config);
896 for (i = 0; i < BIT(width); ++i) {
897 if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
898 /* Write register field */
899 __global_lock2(flags);
900 val = pmx_read(pmx, reg);
903 pmx_write(pmx, val, reg);
904 __global_unlock2(flags);
909 dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
914 static struct pinconf_ops tz1090_pdc_pinconf_ops = {
916 .pin_config_get = tz1090_pdc_pinconf_get,
917 .pin_config_set = tz1090_pdc_pinconf_set,
918 .pin_config_group_get = tz1090_pdc_pinconf_group_get,
919 .pin_config_group_set = tz1090_pdc_pinconf_group_set,
920 .pin_config_config_dbg_show = pinconf_generic_dump_config,
924 * Pin control driver setup
927 static struct pinctrl_desc tz1090_pdc_pinctrl_desc = {
928 .pctlops = &tz1090_pdc_pinctrl_ops,
929 .pmxops = &tz1090_pdc_pinmux_ops,
930 .confops = &tz1090_pdc_pinconf_ops,
931 .owner = THIS_MODULE,
934 static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev)
936 struct tz1090_pdc_pmx *pmx;
937 struct resource *res;
939 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
941 dev_err(&pdev->dev, "Can't alloc tz1090_pdc_pmx\n");
944 pmx->dev = &pdev->dev;
945 spin_lock_init(&pmx->lock);
947 tz1090_pdc_pinctrl_desc.name = dev_name(&pdev->dev);
948 tz1090_pdc_pinctrl_desc.pins = tz1090_pdc_pins;
949 tz1090_pdc_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pdc_pins);
951 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
953 dev_err(&pdev->dev, "Missing MEM resource\n");
957 if (!devm_request_mem_region(&pdev->dev, res->start,
959 dev_name(&pdev->dev))) {
961 "Couldn't request MEM resource\n");
965 pmx->regs = devm_ioremap(&pdev->dev, res->start,
968 dev_err(&pdev->dev, "Couldn't ioremap regs\n");
972 pmx->pctl = pinctrl_register(&tz1090_pdc_pinctrl_desc, &pdev->dev, pmx);
974 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
978 platform_set_drvdata(pdev, pmx);
980 dev_info(&pdev->dev, "TZ1090 PDC pinctrl driver initialised\n");
985 static int tz1090_pdc_pinctrl_remove(struct platform_device *pdev)
987 struct tz1090_pdc_pmx *pmx = platform_get_drvdata(pdev);
989 pinctrl_unregister(pmx->pctl);
994 static struct of_device_id tz1090_pdc_pinctrl_of_match[] = {
995 { .compatible = "img,tz1090-pdc-pinctrl", },
999 static struct platform_driver tz1090_pdc_pinctrl_driver = {
1001 .name = "tz1090-pdc-pinctrl",
1002 .owner = THIS_MODULE,
1003 .of_match_table = tz1090_pdc_pinctrl_of_match,
1005 .probe = tz1090_pdc_pinctrl_probe,
1006 .remove = tz1090_pdc_pinctrl_remove,
1009 static int __init tz1090_pdc_pinctrl_init(void)
1011 return platform_driver_register(&tz1090_pdc_pinctrl_driver);
1013 arch_initcall(tz1090_pdc_pinctrl_init);
1015 static void __exit tz1090_pdc_pinctrl_exit(void)
1017 platform_driver_unregister(&tz1090_pdc_pinctrl_driver);
1019 module_exit(tz1090_pdc_pinctrl_exit);
1021 MODULE_AUTHOR("Imagination Technologies Ltd.");
1022 MODULE_DESCRIPTION("Toumaz Xenif TZ1090 PDC pinctrl driver");
1023 MODULE_LICENSE("GPL v2");
1024 MODULE_DEVICE_TABLE(of, tz1090_pdc_pinctrl_of_match);